Circuit assembly and packaging technologies for power electronics have not kept pace with those for digital electronics. Inside those packaged power devices as well as the state-of-the-art power modules, interconnection of power chips is accomplished with wirebonds. Wirebonds in power devices and modules are prone to resistance, noise, parasitic oscillations, fatigue and eventual failure. Furthermore, there has been an increase demand for higher power density and better efficiency for power converters. Power semiconductor suppliers have been concentrating on improving device structure, density, and process technology to lower the on-resistance of MOSFETs and voltage drop of IGBTs. Recent advances made in power semiconductor technology are pushing packaging technology to the limits for performance of these power systems since the resistance and parasitics contribution by the package and the wirebonds are roughly the same as that on the silicon. In recent years, an integrated systems approach to standardizing power electronics components and packaging techniques in the form of power electronics building blocks has emerged as a new concept in the area of power electronics. As a result, it has been envisioned that the packaging of three-dimensional high-density multichip modules (MCMs) can meet the requirement for future power electronics systems. However, the conventional wirebond interconnected power devices are excluded from three-dimensional MCMs because of their large size, limited thermal management, and incompatible processing techniques. On the other hand, advanced solder joint area-array technologies, such as flip-chip technology, has emerged in microelectronics industry due to increased speed, higher packaging density, and performance, improved reliability and low cost these technologies offer. With all these benefits to offer, solder joint area-array technology has yet to be implemented for power electronics packaging. Therefore, the first objective of this study is to design and develop a solder joint area-array interconnection technique for power chips. Solder joint reliability is a major concern for area array technologies and power chip interconnection, thus the second objective of this study is to evaluate solder joint reliability, investigate the fatigue failure behavior of solder joint and improve solder joint reliability by developing a new solder bumping process for improved solder joint geometry, underfilling solder joint with encapsulant and applying flexible substrate in the assembly. The third objective is the implementation of solder joint interconnection technique in developing chip-scale power packages and a three-dimensional integrated power electronics module structure. Solder joint area array interconnection for power chips has been designed with the considerations of parasitic resistance and inductance reduction, current handling capability, thermal management, reliability improvement and manufacturability. A new solder joint fabrication process, which is able to produce high standoff hourglass-shaped solder joint that consists of an inner cap, middle ball and outer cap, as well as the conventional solder bumping process have been successfully developed for power chips by using stencil printing. This solder bumping technology is compatible with the existing surface-mount assembly operations and potentially low cost. The fabricated solder joints have been characterized for their structure integrity, mechanical strength and electrical performances. Solder joint reliability has been improved by optimizing solder joint geometry, underfilling flipped power chip and utilizing compliant substrate. Solder joint reliability was evaluated using accelerated temperate cycling and adhesion tests. The interfaces of the triple-stacked solder joints were examined using scanning electron microscopy (SEM) and energy dispersive X-ray analysis (EDX) for the integrity of the joint. Acoustic microscopy imaging (nondestructive evaluation) was utilized to examine the quality of the bonded interfaces and to detect cracks and other defects before and during accelerated fatigue tests. Adhesion strength of both single bump barrel-shaped and stacked hourglass-shaped solder joints to bonding pads was characterized and analyzed. It was found that stacked hourglass-shaped solder joint have higher fracture stress than barrel-shaped solder joint. This verifies that hourglass-shaped solder joint has lower stress singularity at the interface between the solder bump and the silicon die as well as at the interface between the solder bump and substrate than barrel-shaped solder joint, especially around the corners of the interfaces. Furthermore, the adhesion strength of barrel-shaped solder joint decreases much faster than that of high standoff hourglass-shaped solder joint under temperature cycling, which indicates that the latter has high reliability than the former. Our accelerated temperature cycling test clearly shows that solder joint fatigue failure process consists of three phases: crack initiation, crack propagation and catastrophic failure. Solder joint geometry, underfilling and substrate flexibility were proved to affect solder joint reliability. The effects of solder joint shape and standoff height on reliability have been systematically studied experimentally for the first time. Our experimental results indicated that both hourglass shape and great standoff height could improve solder joint fatigue lifetime, with standoff height being the more effective factor. The fatigue lifetime of high standoff hourglass-shaped solder joint is improved mainly by prolonged crack propagation time, with slight improvement in crack initiation time. Experimental data suggested that shape is the dominant factor affecting crack initiation time while standoff height is the major factor influencing crack propagation time. Underfilling and flexible substrate improved the lifetime of both barrel and hourglass-shaped solder joints. The effect of underfill on solder joint reliability is well known in microelectronics packaging field. However, for the first time, it is reported in this study that flex substrate could improve solder joint reliability. It has been found that flex substrate bucks during temperature cycling and thus reduces thermal strain in solder joints, which in turn improves solder joint fatigue lifetime. Chip scale packaging can enable a few very important concepts and advantages in power electronics packaging. It offers high silicon to package footprint ratio, provides a known good die solution to power chips, improves electrical as well as thermal performance and creates an opportunity for power component standardization. Two kinds of chip-scale power packages have been developed in this research. One is called cavity down flip chip on flex; the other is termed Die Dimensional Ball Grid Array (D2BGA). Both utilize solder joint as chip-level interconnection. Electrical tests show that the VCE(sat) of the high speed IGBT chip-scale packages is improved by 20% to 30% by eliminating the device¡¯s wirebonds and other external interconnections, such as leadframe. Double-sided cooling is realized in these CSPs. Temperature cycling test shows that the CSPs are reliable. Integrated power electronics modules (IPEMs) are envisioned as integrated power modules consisting of power semiconductor devices, power integrated circuits, sensors, and protection circuits for a wide range of power electronics applications, such as inverters for motor drives and converters for power processing equipment. We have developed a three-dimensional approach, termed flip chip on flex (FCOF), for packaging high-performance IPEMs. The new concept is based on the use of solder joint (D2BGA chip scale package), not bonding wires, to interconnect power devices. This packaging approach has the potential to produce modules having superior electrical and thermal performance and improved reliability. We have demonstrated the feasibility of this approach by constructing half-bridge converters (consisting of two IGBTs, two power diodes, and a simple gate driver circuitry) which have been successfully tested at power levels over 30 kW. Switching tests have shown that parasitic inductance of the FCOF module has been reduced by 40% to 50% over conventional wire bond power modules. Better thermal management can be achieved in this three-dimensional power module structure. Compared with the state-of-the-art half-bridge power modules, the volume of the half-bridge FCOF power module is reduced by at least 65%. Reliability test shows that this flip chip on flex power module structure is potentially more reliable than wire bond power module. / Ph. D.

Les convertisseurs électroniques de puissance sont voués à fonctionner sous des conditions applicatives de plus en plus sévères tout en respectant les impératifs d’efficacité énergétique et de fiabilité. Or, les besoins industriels tendent vers un plus haut niveau d’intégration fonctionnelle tout en améliorant le rapport qualité-prix. Dès lors, la solution utilisée pour le report des puces semi-conductrices est le siège de densités de courant importantes et d’un flux thermique élevé. La présence de défauts dans cette couche d’interconnexion peut conduire à la dégradation de ses performances et au vieillissement prématuré du composant. L’objectif de nos recherches est d’évaluer la pertinence d’une méthodologie basée sur la confrontation de simulations numériques et de campagnes expérimentales. L’objectif est d’améliorer la compréhension du comportement électrothermique en régime de conduction d’un transistor MOSFET en présence d’un void dans sa brasure. Dans cette manuscrite, nous présenterons la construction d’un modèle intégrant le couplage électrothermique de la partie active qui sera confronté à la réponse de résultats expérimentaux. Puis, une étude numérique basée sur la théorie des plans fractionnaires, qui minimise le nombre de simulations, sera exploitée afin de quantifier l’impact de la taille et de la position du défaut sur la réponse électrothermique du composant et de ses liaisons électriques. Les détails de la mise en place d’une étude expérimentale analogue permettront de mettre en perspective la complémentarité de cette approche. / Power converters nowadays are required to function under harsh conditions in meeting energy efficiency and reliability requirement. Whereas, industrial specifications tend toward a higher level of power integration in respect to the cost constraint. As a result, the die attach is one of the key elements in power module packaging because of high current densities and high heat flow which are transported through. Void formation in the die attach may lead to performance degradation and premature aging of the component. This study introduces a methodology based on the comparison of numerical simulations and experimental campaigns. The obtained results help to improve our understanding on the electro-thermal behaviour of MOSFETs with solder voids. In this thesis, we depict a finite element model in which electro-thermal coupling of a MOSFET active layer is taken in to account. Simulation results will be correlated to the experimental responses. Later on, a parametric numerical study based on the response surface method (RSM) which minimizes the number of simulations and future tests will be exploited to quantify the impact of void position and size on several selective performance criteria. A future serial experimental study in respect to the same RSM design is expected in prospect, in order to fulfil the complementarity for this approach.

abstract: As the microelectronics industry continues to decrease the size of solder joints, each joint will have to carry a greater current density, making atom diffusion due to current flow, electromigration (EM), a problem of ever-increasing severity. The rate of EM damage depends on current density, operating temperature, and the original microstructure of the solder joint, including void volume, grain orientation, and grain size. While numerous studies have investigated the post-mortem effects of EM and have tested a range of current densities and temperatures, none have been able to analyze how the same joint evolves from its initial to final microstructure. This thesis focuses on the study of EM, thermal aging, and thermal cycling in Sn-rich solder joints. Solder joints were either of controlled microstructure and orientation or had trace alloying element additions. Sn grain orientation has been linked to a solder joints’ susceptibility to EM damage, but the precise relationship between orientation and intermetallic (IMC) and void growth has not been deduced. In this research x-ray microtomography was used to nondestructively scan samples and generate 3D reconstructions of both surface and internal features such as interfaces, IMC particles, and voids within a solder joint. Combined with controlled fabrication techniques to create comparable samples and electron backscatter diffraction (EBSD) and energy-dispersive spectroscopy (EDS) analysis for grain orientation and composition analysis, this work shows how grain structure plays a critical role in EM damage and how it differs from damage accrued from thermal effects that occur simultaneously. Unique IMC growth and voiding behaviors are characterized and explained in relation to the solder microstructures that cause their formation and the possible IMC-suppression effects of trace alloying element addition are discussed. / Dissertation/Thesis / Doctoral Dissertation Materials Science and Engineering 2019

No description available.

Two types of solder samples, pins and through-holes were tested by SERA™ (Sequential Electrochemical Reduction Analysis) and Wetting Balance after various length of steamaging treatment. It was shown that after steam-aging, both types of specimen gave a similar electrochemical reduction curve, and solderabilty predictions made from SERA™ test agree with results obtained from Wetting Balance test on a qualitative base. Wetting balance test of pin samples after SERA™ test confirmed that SERA™ is a non-destructive testing method -- it even restored solderability. Comparison of electrochemical reduction behavior of samples under different treatment indicates that steam-aging can not reproduce exactly the effect of naturally atmospheric aging, and may not be the best artificial accelerating environment adopted.

No description available.

No description available.

Electronics, especially, printed circuit boards (PCBs) are a widespread technology. Metal coatings or “surface finishes” are often added to PCB board pads and component leads during manufacturing to improve their performance. Electroplated nickel/gold over copper is a popular surface finish for printed circuit boards and component leads. The presence of gold in solder joints, however, is known to have detrimental effects referred to as gold embrittlement. It is generally understood that tin-lead solder joints with less than 3 weight percent (wt%) of gold will not experience reliability issues. The acceptable level of gold in lead-free solder joints, however, is less well understood, as the technology is younger. The purpose of this study was to investigate the effect of gold content on the microstructural evolution of SnAgCu solder joints. Three integrated circuit packages with various thicknesses of gold coatings were assembled on boards that were made with thin (flash) or thick gold over nickel coatings. The boards were divided into three groups based on the isothermal aging they underwent: 0 days, 30 days, or 56 days of aging at 125 °C. Thirty four of the forty boards then underwent mechanical reliability testing. Components were cross-sectioned and polished. Scanning electron microscopy (SEM) and energy dispersive spectroscopy (EDS/EDX) were used to characterize the morphology and elemental composition of the solder joints and any intermetallic compounds (IMCs) that formed. The growth of bulk and interfacial layer IMCs in each package/board system was studied. In thick gold boards, AuSn4 particles observed in the bulk solder grew larger over time, absorbed Ni, and migrated to the component and board interfaces. (Cu1-p-qAupNiq)6Sn5 and (Au1-xNix)Sn4 IMCs were found at most board and component interfaces after aging. It was observed that most fractures occurred in or along the (Au1-xNix)Sn4 IMCs. Cracks were observed within IMC particles in the bulk solder, along the boardside and component side interfaces, and in the bulk solder traveling toward voids. Components with joint Au contents higher than 10 wt% had unacceptably poor reliability. The conclusion of this work is that gold content of SAC305 solder joints on boards with Au over Ni surface finishes should be kept below 3 wt% to conservatively minimize the risk of creating a microstructure that has poor reliability.

The appropriate selection of failure criterion for solder joint studies is necessary to correctly estimate reliability life. The objective of this study is to compare the effect of different failure criteria on the reliability life estimation. The four failure criteria in this study are a 20% resistance increase defined in the IPC-9701A standard, a resistance beyond 500 Ω, an infinite resistance (hard open), and a failure criterion based on X-bar and R control charts. Accelerated thermal cycling conditions of a low-silver BGA study included 0°C to 100 °C with ten minute dwell times and -40°C to 125°C with ten minute dwell times. The results show that the life estimation based on X-bar and R failure criterion is very similar to the life estimation when a 20% resistance increase defined in the IPC-9701A failure criterion is used. The results also show that the reliability life would be overestimated if the failure criterion of a resistance threshold of 500 Ω or an infinite resistance (hard open) is used.

This thesis examines the packaging of high-temperature SiC power electronic devices. Current-voltage measurements were conducted on as-received and packaged SiC power devices. The planar structure was introduced and developed as a substitution for traditional wire-bonding vertical structure. The planar structure was applied to a high temperature (>250oC) SiC power device. Based on the current-voltage (I-V) measurements, the packaging structures were improved, materials were selected, and processes were tightly controlled. This study applies two types of planar structures, the direct bond and the bump bond, to the high-temperature packaging of high-temperature SiC diode. A drop in the reverse breakdown voltage was discovered in the packaging using a direct bond. The root cause for the drop in the breakdown voltage was identified and corrective solutions were evaluated. A few effective methods were suggested for solving the breakdown issue. The forward I-V curve of the planar packaging using direct bond showed excellent results due to the excellent electrical and thermal properties of sintered nanosilver. The packaging using a bump bond as an improved structure was processed and proved to possess desirable forward and reverse I-V behavior. The cross-sections of both planar structures were inspected. High-temperature packaging materials, including nano-silver paste, high-lead solder ball and paste, adhesive epoxy, and encapsulant, were introduced and evaluated. The processes such as stencil printing, low-temperature sintering, solder reflowing, epoxy curing, sputtering deposition, electroplating, and patterning of direct-bond copper (DBC) were tightly controlled to ensure high-quality packaging with improved performance. Finally, the planar packaging of the high temperature power device was evaluated and summarized, and the future work was recommended. / Master of Science