In this thesis, we successfully fabricated GOLD ( gate-overlapped LDD ) polycrystalline silicon thin-film transistors ( poly-Si TFTs ) with selectively deposited W spacers. Under appropriate deposition conditions, tungsten ( W ) films can be selectively deposited on poly-Si gate electrodes to form spacers without any additional etching process. Compared with the conventional poly-TFTs without LDD structures, our devices effectively lower the leakage current and sustain a comparable on current. The transconductance of our devices is compatible to that of conventional devices, because W-spacer acts as a part of gate electrode to induce channel when the device is operated under ON state. To further study the characteristics of W-spacer TFTs, devices with different channel thickness, spacer thickness and LDD dopant density are fabricated. It is found that thinner channel, thicker spacer and lightly doped LDD implant can effectively suppress the floating body effect and also the kink effect. By comparing device performances after plasma passivation, it is also found that small-dimensional devices have better passivation effect. Finally, the hot-carrier reliability of W-spacer TFTs is also studied. Due to the reduced electric filed on the drain side, W-spacer TFTs have better reliability than the conventional counterparts.

Metal oxides exhibit a wide range of chemical and electronic properties, making them an extremely interesting subject for numerous applications in modern electronics. The primary goal of this research is to develop metal-oxide-based electronic devices, including thin-film transistors (TFTs), resistance random-access memory (RRAM) and planar nano-devices. This research requires different processing techniques, novel device design concepts and optimisation of materials and devices. The first experiments were carried out to optimise the properties of zinc oxide (ZnO) semiconductors, in particular the carrier concentration, which determines the threshold voltage of the TFTs. Thermal annealing is one common method to affect carrier concentration and most work in the literature reports performing this process in a single-gas environment. In this work, however, annealing was carried out in a combination of air and nitrogen, and it was found that the threshold voltage could be tuned over a wide range of pre-determined values.Further experiments were undertaken to enhance the carrier mobility of ZnO TFTs, which is the most important material quality parameter. By optimising deposition conditions and incorporating a high-k gate dielectric layer, the devices showed saturation mobility values over 50 cm2/Vs at a low operating voltage of 4 V. This is, to our knowledge, one of the highest field-effect mobility values achieved in ZnO-based TFTs by room temperature sputtering. As an important type of metal-oxide-based novel memory devices, which have been studied intensively in the last few years, RRAM devices were also explored. New materials, such as tin oxide (SnOx), were tested, exhibiting bipolar-switching operations and a relatively large resistance ratio. As a novel process variation, anodisation was performed, which yielded less impressive results than SnOx, but with a potential for ultra-low-cost manufacturing. Finally, novel planar nano-devices were explored, which have much simpler structures than conventional multi-layered transistors and diodes. Three types of ZnO-based nano-devices (a side-gated transistor, a self-switching diode and a planar inverter) were fabricated using both e-beam lithography and chemical wet etching. After optimisation of the challenging wet etching procedure at nanometre scale, ZnO nano-devices with good reproducibility and reliability have been demonstrated.

Ce travail présente les principaux résultats obtenus avec une large gamme de dispositifs SOI avancés, candidats très prometteurs pour les futurs générations de transistors MOSFETs. Leurs propriétés électriques ont été analysées par des mesures systématiques, agrémentées par des modèles analytiques et/ou des simulations numériques. Nous avons également proposé une utilisation originale de dispositifs FinFETs fabriqués sur ONO enterré en fonctionnalisant le ONO à des fins d'application mémoire non volatile, volatile et unifiées. Après une introduction sur l'état de l'art des dispositifs avancés en technologie SOI, le deuxième chapitre a été consacré à la caractérisation détaillée des propriétés de dispositifs SOI planaires ultra- mince (épaisseur en dessous de 7 nm) et multi-grille. Nous avons montré l’excellent contrôle électrostatique par la grille dans les transistors très courts ainsi que des effets intéressants de transport et de couplage. Une approche similaire a été utilisée pour étudier et comparer des dispositifs FinFETs à double grille et triple grille. Nous avons démontré que la configuration FinFET double grille améliore le couplage avec la grille arrière, phénomène important pour des applications à tension de seuil multiple. Nous avons proposé des modèles originaux expliquant l'effet de couplage 3D et le comportement de la mobilité dans des TFTs nanocristallin ZnO. Nos résultats ont souligné les similitudes et les différences entre les transistors SOI et à base de ZnO. Des mesures à basse température et de nouvelles méthodes d'extraction ont permis d'établir que la mobilité dans le ZnO et la qualité de l'interface ZnO/SiO2 sont remarquables. Cet état de fait ouvre des perspectives intéressantes pour l'utilisation de ce type de matériaux aux applications innovantes de l'électronique flexible. Dans le troisième chapitre, nous nous sommes concentrés sur le comportement de la mobilité dans les dispositifs SOI planaires et FinFET en effectuant des mesures de magnétorésistance à basse température. Nous avons mis en évidence expérimentalement un comportement de mobilité inhabituel (multi-branche) obtenu lorsque deux ou plusieurs canaux coexistent et interagissent. Un autre résultat original concerne l’existence et l’interprétation de la magnétorésistance géométrique dans les FinFETs.L'utilisation de FinFETs fabriqués sur ONO enterré en tant que mémoire non volatile flash a été proposée dans le quatrième chapitre. Deux mécanismes d'injection de charge ont été étudiés systématiquement. En plus de la démonstration de la pertinence de ce type mémoire en termes de performances (rétention, marge de détection), nous avons mis en évidence un comportement inattendu : l’amélioration de la marge de détection pour des dispositifs à canaux courts. Notre concept innovant de FinFlash sur ONO enterré présente plusieurs avantages: (i) opération double-bit et (ii) séparation de la grille de stockage et de l'interface de lecture augmentant la fiabilité et autorisant une miniaturisation plus poussée que des Finflash conventionnels avec grille ONO.Dans le dernier chapitre, nous avons exploré le concept de mémoire unifiée, en combinant les opérations non volatiles et 1T-DRAM par le biais des FinFETs sur ONO enterré. Comme escompté pour les mémoires dites unifiées, le courant transitoire en mode 1T-DRAM dépend des charges non volatiles stockées dans le ONO. D'autre part, nous avons montré que les charges piégées dans le nitrure ne sont pas perturbées par les opérations de programmation et lecture de la 1T-DRAM. Les performances de cette mémoire unifiée multi-bits sont prometteuses et pourront être considérablement améliorées par optimisation technologique de ce dispositif. / The evolution of electronic systems and portable devices requires innovation in both circuit design and transistor architecture. During last fifty years, the main issue in MOS transistor has been the gate length scaling down. The reduction of power consumption together with the co-integration of different functions is a more recent avenue. In bulk-Si planar technology, device shrinking seems to arrive at the end due to the multiplication of parasitic effects. The relay has been taken by novel SOI-like device architectures. In this perspective, this manuscript presents the main achievements of our work obtained with a variety of advanced fully depleted SOI MOSFETs, which are very promising candidates for next generation MOSFETs. Their electrical properties have been analyzed by systematic measurements and clarified by analytical models and/or simulations. Ultimately, appropriate applications have been proposed based on their beneficial features.In the first chapter, we briefly addressed the short-channel effects and the diverse technologies to improve device performance. The second chapter was dedicated to the detailed characterization and interesting properties of SOI devices. We have demonstrated excellent gate control and high performance in ultra-thin FD SOI MOSFET. The SCEs are efficiently suppressed by decreasing the body thickness below 7 nm. We have investigated the transport and electrostatic properties as well as the coupling mechanisms. The strong impact of body thickness and temperature range has been outlined. A similar approach was used to investigate and compare vertical double-gate and triple-gate FinFETs. DG FinFETs show enhanced coupling to back-gate bias which is applicable and suitable for dynamic threshold voltage tuning. We have proposed original models explaining the 3D coupling effect in FinFETs and the mobility behavior in ZnO TFTs. Our results pointed on the similarities and differences in SOI and ZnO transistors. According to our low-temperature measurements and new promoted extraction methods, the mobility in ZnO and the quality of ZnO/SiO2 interface are respectable, enabling innovating applications in flexible, transparent and power electronics. In the third chapter, we focused on the mobility behavior in planar SOI and FinFET devices by performing low-temperature magnetoresistance measurements. Unusual mobility curve with multi-branch aspect were obtained when two or more channels coexist and interplay. Another original result in the existence of the geometrical magnetoresistance in triple-gate and even double-gate FinFETs.The operation of a flash memory in FinFETs with ONO buried layer was explored in the forth chapter. Two charge injection mechanisms were proposed and systematically investigated. We have discussed the role of device geometry and temperature. Our novel ONO FinFlash concept has several distinct advantages: double-bit operation, separation of storage medium and reading interface, reliability and scalability. In the final chapter, we explored the avenue of unified memory, by combining nonvolatile and 1T-DRAM operations in a single transistor. The key result is that the transient current, relevant for 1T-DRAM operation, depends on the nonvolatile charges stored in the nitride buried layer. On the other hand, the trapped charges are not disturbed by the 1T-DRAM operation. Our experimental data offers the proof-of-concept for such advanced memory. The performance of the unified/multi-bit memory is already decent but will greatly improve in the coming years by processing dedicated devices.

In this dissertation, the electrical characteristics of generally used hydrogenated amorphous silicon (a-Si:H) TFTs in LCD and newly risen amorphous indium-gallium-zinc oxide (a-IGZO) TFTs were studied. For modern mobile display and large-size flat panel display application, the traditional thin-film transistor-liquid crystal display (TFT-LCD) technology confronts with a lot of challenges and problems. In general, flexible displays must exhibit some bending ability; however, bending applies mechanical strain to electronic circuits and affects device characteristics. Therefore, the electrical characteristics of a-Si:H TFTs fabricated on stainless steel foil substrates with uniaxial bending were investigated at different temperatures. Experimental results showed that the on-state current and threshold voltage degraded under outward bending. This is because outward bending will induce the increase of band tail states, affecting the transport mechanism at different temperatures. In addition, for practical operation, the electrical characteristics of a-Si:H TFTs under flat and bending situations after AC/DC stress at different temperatures were studied. It was found that high temperature and mechanical bending played important roles under AC stress. The dependence between the accumulated sum of bias rising and falling time and the threshold voltage shifts under AC stress was also observed. Because a-Si:H is a photosensitive material, the high intensity backlight illumination will degrade the performance of a-Si:H TFTs. Thus, the photo-leakage current of a-Si:H TFTs under illumination was investigated at different temperatures. Experimental results showed that a-Si:H TFTs exhibited a pool performance at lower temperatures. The indirect recombination rate and the parasitic resistance (Rp) are responsible for the different photo-leakage-current trends of a-Si:H TFTs under varied temperature operations. To investigate the photo-leakage current, the a-Si:H TFTs were exposed to ultraviolet (UV) light irradiation. It was found that the photo current of a-Si:H TFTs was reduced after UV light irradiation. The detail mechanisms on reducing/increasing photo-leakage current by UV light irradiation were discussed. Recently, the oxide-based semiconductor TFT, especially a-IGZO TFT, is considered as one of promising candidates for active matrix flat-panel display. However, the a-IGZO TFT exists significant electrical instability issue and manufacturing problems. As a consequence, we investigated the effect of hydrogen incorporation on a-IGZO TFTs to reduce interface states between active layer and insulator. Experimental results showed that the electrical characteristics of hydrogen-incorporated a-IGZO TFTs were improved. The threshold voltage shift (£GVth) in hysteresis loop is suppressed from 4 V to 2 V due to the hydrogen-induced passivation of the interface trap states. Finally, we reported the effect of ambient environment on a-IGZO TFT instability. As a-IGZO TFTs were stored in atmosphere environment for 40 days, the transfer characteristics accompanying strange hump were observed during bias-stress. The hump phenomenon is attributed to the absorption of H2O molecule. Additionally, the sufficient electric field is also necessary to cause this anomalous transfer characteristic.

In first part, the supercritical CO2 (SCCO2) fluid technology is employed to improve the device properties of ZnO TFT. The SCCO2 fluid exhibits liquid-like property, which has excellent transport ability. Furthermore, the SCCO2 fluid has gas-like and high-pressure properties to diffuse into the nanoscale structures without damage. Hence, the SCCO2 fluid can carry the H2O molecule effectively into the ZnO films at low temperature and passivate traps by H2O molecule at low temperature. The experimental results show that the on current, sub-threshold slope, and threshold voltage of the device were improved significantly. Next, the electrical degradation behaviors and mechanisms under drain bias stress of a-IGZO TFTs were investigated. A current crowding effect and an obvious capacitance-voltage stretch-out were observed after stress. During the drain-bias stress, the oxygen would be absorbed on the back channel near the drain region of IGZO film. Therefore, the carrier transport is impeded by the additional energy barrier near drain region induced by the adsorbed oxygen, which forms a depletion layer to generate the parasitism resistance. We also investigated the RRAM device based on IGZO film, and proposed the related physical mechanism models. The IGZO RRAM will be very promising for integration with IGZO TFTs for advanced system-on-panel display applications to be a transparent embedded system. In this part, the transparent RRAM device with ITO/IGZO/ITO structure was fabricated. The proposed device presents an excellent bipolar resistive switching characteristic and good reliability. The bipolar switching mechanism of our device is dominated by the formation and rupture of the oxygen vacancies in a conduction path. The influence of electrode material on resistance switching characteristic is investigated through Pt/IGZO/TiN and Ti/IGZO/TiN structure. As the bias applied on the Ti or TiN, the Ti or TiN electrode can play the role of oxygen reservoir to absorb/discharge oxygen ions. Therefore, the device presents a bipolar resistive switching characteristic. However, as the bias applied on the Pt electrode, the device presents a unipolar resistive switching characteristic. Because the Pt electrode can¡¦t store the oxygen ion, the device should use the joule heating mode to rupture the conduction path and present the unipolar resistive switching characteristic. Finally, the resistive switching properties of IGZO film deposited at different oxygen content were investigated, since the resistance switching behaviors are related to the formation and rupture of filaments composed of oxygen vacancies in the IGZO matrix. Experiment results show that the HRS current decreases when the oxygen partial pressure gradually increases. Based on the XPS analysis, these phenomena are related to the non-lattice oxygen concentration. With increasing oxygen ratio, the filaments will rupture completely through the abundant non-lattice oxygen inducing oxidation, which leads to HRS current decrease and an increase in the memory window.

Ce travail présente les principaux résultats obtenus avec une large gamme de dispositifs SOI avancés, candidats très prometteurs pour les futurs générations de transistors MOSFETs. Leurs propriétés électriques ont été analysées par des mesures systématiques, agrémentées par des modèles analytiques et/ou des simulations numériques. Nous avons également proposé une utilisation originale de dispositifs FinFETs fabriqués sur ONO enterré en fonctionnalisant le ONO à des fins d'application mémoire non volatile, volatile et unifiées. Après une introduction sur l'état de l'art des dispositifs avancés en technologie SOI, le deuxième chapitre a été consacré à la caractérisation détaillée des propriétés de dispositifs SOI planaires ultra- mince (épaisseur en dessous de 7 nm) et multi-grille. Nous avons montré l'excellent contrôle électrostatique par la grille dans les transistors très courts ainsi que des effets intéressants de transport et de couplage. Une approche similaire a été utilisée pour étudier et comparer des dispositifs FinFETs à double grille et triple grille. Nous avons démontré que la configuration FinFET double grille améliore le couplage avec la grille arrière, phénomène important pour des applications à tension de seuil multiple. Nous avons proposé des modèles originaux expliquant l'effet de couplage 3D et le comportement de la mobilité dans des TFTs nanocristallin ZnO. Nos résultats ont souligné les similitudes et les différences entre les transistors SOI et à base de ZnO. Des mesures à basse température et de nouvelles méthodes d'extraction ont permis d'établir que la mobilité dans le ZnO et la qualité de l'interface ZnO/SiO2 sont remarquables. Cet état de fait ouvre des perspectives intéressantes pour l'utilisation de ce type de matériaux aux applications innovantes de l'électronique flexible. Dans le troisième chapitre, nous nous sommes concentrés sur le comportement de la mobilité dans les dispositifs SOI planaires et FinFET en effectuant des mesures de magnétorésistance à basse température. Nous avons mis en évidence expérimentalement un comportement de mobilité inhabituel (multi-branche) obtenu lorsque deux ou plusieurs canaux coexistent et interagissent. Un autre résultat original concerne l'existence et l'interprétation de la magnétorésistance géométrique dans les FinFETs.L'utilisation de FinFETs fabriqués sur ONO enterré en tant que mémoire non volatile flash a été proposée dans le quatrième chapitre. Deux mécanismes d'injection de charge ont été étudiés systématiquement. En plus de la démonstration de la pertinence de ce type mémoire en termes de performances (rétention, marge de détection), nous avons mis en évidence un comportement inattendu : l'amélioration de la marge de détection pour des dispositifs à canaux courts. Notre concept innovant de FinFlash sur ONO enterré présente plusieurs avantages: (i) opération double-bit et (ii) séparation de la grille de stockage et de l'interface de lecture augmentant la fiabilité et autorisant une miniaturisation plus poussée que des Finflash conventionnels avec grille ONO.Dans le dernier chapitre, nous avons exploré le concept de mémoire unifiée, en combinant les opérations non volatiles et 1T-DRAM par le biais des FinFETs sur ONO enterré. Comme escompté pour les mémoires dites unifiées, le courant transitoire en mode 1T-DRAM dépend des charges non volatiles stockées dans le ONO. D'autre part, nous avons montré que les charges piégées dans le nitrure ne sont pas perturbées par les opérations de programmation et lecture de la 1T-DRAM. Les performances de cette mémoire unifiée multi-bits sont prometteuses et pourront être considérablement améliorées par optimisation technologique de ce dispositif.

abstract: ABSTRACT This work seeks to develop a practical solution for short range ultrasonic communications and produce an integrated array of acoustic transmitters on a flexible substrate. This is done using flexible thin film transistor (TFT) and micro electromechanical systems (MEMS). The goal is to develop a flexible system capable of communicating in the ultrasonic frequency range at a distance of 10 - 100 meters. This requires a great deal of innovation on the part of the FDC team developing the TFT driving circuitry and the MEMS team adapting the technology for fabrication on a flexible substrate. The technologies required for this research are independently developed. The TFT development is driven primarily by research into flexible displays. The MEMS development is driving by research in biosensors and micro actuators. This project involves the integration of TFT flexible circuit capabilities with MEMS micro actuators in the novel area of flexible acoustic transmitter arrays. This thesis focuses on the design, testing and analysis of the circuit components required for this project. / Dissertation/Thesis / M.S. Electrical Engineering 2012

Le travail de cette thèse porte sur le développement de transistors en couche mince (Thin Film Transistors, TFTs) à base de silicium microcristallin fabriqués sur un substrat flexible à très basse température (T< 180 °C). La première partie de ce travail a consisté à étudier la stabilité électrique de ces TFTs. L'étude de la stabilité électrique des TFTs de type N fabriqués sur verre a montré que ces TFTs sont assez stables, la tension de seuil VTH ne se décale que de 1.2 V au bout de 4 heures de stress sous une tension de grille VGSstress= +50V et à une température T=50 °C. L'instabilité électrique de ces TFTs est principalement causée par le piégeage des porteurs dans l'isolant de grille. La deuxième étape de ce travail s'est concentrée sur l'étude du comportement de ces TFTs sous déformation mécanique. Ces TFTs sont soumis à un stress mécanique en tension et en compression. Le rayon de courbure minimum que les TFTs pouvaient supporter est r=1.5 mm en tension et en compression. La limitation de la déformation mécanique de ces TFTs est principalement due à la contrainte mécanique du nitrure de silicium utilisé comme isolant de grille des TFTs. Autrement dit, ces TFTs sont mécaniquement fiables et présentes une faible variation du courant ION, de l'ordre de 1%, même après 200 cycles de déformation mécanique. Ces résultats obtenus laissent entrevoir la possibilité de concevoir une électronique flexible pouvant être pliée en 2. Enfin, les TFTs sont fabriqués avec différents isolants de grille afin d'augmenter la mobilité d'effet de champ. Malheureusement, aucun isolant de grille utilisé dans ces études n'a permis d'augmenter la mobilité d'effet de champ sans dégrader la stabilité électrique des TFTs. Des études plus détaillées et des optimisations complémentaires sur ces isolants de grille sont nécessaires. / This work deals with the development of microcrystalline silicon thin film transistors (TFTs) fabricated on flexible substrate at low temperature (T=180 °C). The first step of this work consists in studying the electrical stability of TFTs. The N-type TFTs fabricated on glass substrate are electrically stable under gate bias stress VGStress= +50V at T=50 °C. The threshold voltage shift (ΔVTH) was only 1.2 V during 4 hours. This electrical instability of TFTs is mainly due to carrier trapping inside the silicon nitride gate insulator. The second step of this work lies in the study of the mechanical behavior of the TFTs. Both tensile and compressive strains were applied on TFTs. The minimum curvature radius is r=1.5 mm for both tension and compression. The main limitation of TFTs comes from the mechanical strain εlimit of silicon nitride used as gate insulator of TFTs. Also, these TFTs are mechanically reliable: the variation of ION current was only 1% after 200 cycles mechanical bending. These results obtained open the way to the development of flexible electronics that can be folded in half.Finally, TFTs have been fabricated using different gate insulators in order to improve the mobility. Unfortunately, all the gate insulators used couldn’t improve mobility without sacrificing electrical stability of TFT. More detailed studies and complementary optimization of these gate insulators are necessary.

In this dissertation, we investigates the electrical stress induced degradation in low-temperature polycrystalline-silicon thin film transistors (LTPS TFTs) applied for system-on-panel (SOP), including the electrical degradations of device for switch operation in active matrix flat-panel displays, driving circuit and nonvolatile memory. Finally, we also present the reliability of LTPS TFTs applied for flexible displays. In first part, electrical degradation of conventional and pattered metal-shielding LTPS TFTs under darkened and illuminated dynamic AC stresses are investigated. Experimental results reveal that competitive mechanisms are generated in conventional LTPS TFTs during illuminated stress, namely, carrier increase and electric field weakening. This phenomenon is verified by stressing the patterned source/drain open metal-shielding LTPS TFTs, which determines that the electric field weakening dominates; conversely, the carrier increase is dominated the electrical degradation in channel open metal-shielding device under illuminated stress. In addition, an improvement in anomalous on-current and subthreshold swing (S.S.) in n-channel LTPS TFTs after positive gate bias stress are studied. These improved electric properties are due to the hole trapping at SiO2 above the lightly doped drain regions, which causes a strong electric field at the gate corners. The effect of the hole trapping is to reduce the effective channel length and the S.S.. Besides, the stress-related electric field was also simulated by TCAD software to verify the mechanism above. Secondly, a mechanism of anomalous capacitance in p-channel LTPS TFTs was investigated. In general, the effective capacitance of the LTPS TFTs was only dependent with the overlap area between gate and source/drain under the off-state. However, the experimental results reveal that the off-state capacitance was increased with decreasing measurement frequency and/or with increasing measurement temperature. Besides, by fitting the curve of drain current versus electric field under off-state region, it was verified that the TAGIDL is consisted of the Pool-Frenkel emission and Thermal-Field emission. In addition, the charge density calculated from the Cch-Vg measurement also the same dependence with electric field. This result demonstrates that the anomalous capacitance is mainly due to the trap-assisted-gate-induced-drain-leakage (TAGIDL). In order to suppress the anomalous capacitance, a band-to-band hot electron (BTBHE) stress was utilized to reduce the vertical electric field between the gate and the drain. In third part, in order to realize the reliability in p-channel TFTs under illuminated environment operation, the degradation of negative bias temperature instability (NBTI) with illumination effect is investigated. The generations of interface state density (Nit) are identical under various illuminated intensity DC NBTI stresses. Nevertheless, the degradation of the grain boundary trap (Ntrap) under illumination was more significant than for the darkened environment, with degradation increasing as illumination intensity increases. This phenomenon is mainly caused by the extra number of holes generated during the illuminated NBTI stress. The increased Ntrap degradation leads to an increase in the darkened environment leakage current. This indicates that more traps are generated in the drain junction region that from carrier tunneling via the trap, resulting in leakage current. Conversely, an increase of Ntrap degradation results in a decrease in the photoleakage current. This indicates that the number of recombination centers increases in poly-Si bulk, affecting photosensitivity in LTPS TFTs. Besides, the transient effect assisted NBTI degradation in p-channel LTPS TFTs under dynamic stress is also presented, in which the degradation of the Ntrap becomes more significant as rise time decreases to 1 £gs. Because the surface inversion layer cannot form during the short rise time, transient bulk voltage will cause excess holes to diffuse into the poly-Si bulk. Therefore, the significant Ntrap increase is assisted by this transient effect. Fourthly, we study the electric properties of n- and p-channel LTPS TFTs under the mechanical tensile strain. The improved on-current for tensile strained n-channel TFTs is originated form an increase in energy difference between 2- and 4-fold valleys, reducing the inter-valley scattering and further improving the carrier mobility. On the contrary, the hole mobility decreases in p-channel, suggesting the split between the light hole and heavy hole energy bands and an increase in hole population on the heavy hole energy band of poly-Si when the uniaxial tensile strain is parallel to the channel direction. In addition, the Nit and Ntrap degradations induced by NBTI for tensile strained LTPS TFTs are more pronounced than in the unstrained. Extracted density-of-states (DOS) and conduction activation energy (EA) both show increases due to the strained Si-Si bonds, which implies that strained Si-Si bonds are able to react with dissociated H during the NBTI stress. Therefore, the NBTI degradation is more significant after tensile strain than in an unstrained condition. Finally, the SONOS-TFT applied to nonvolatile memory is prepared and studied. In the gate disturb stress, a parasitic capacitance and resistance in off-state region are identified as electrons trapped in the gate-insulator (GI) near the defined gate region. Meanwhile, these trapping electrons induced depletions in source/drain also degraded the I-V characteristic when the gate bias is larger than the threshold voltage. However, these degradations slightly recover when the trapped electrons are removed after negative bias stress. The electric field in the undefined gate region is also verified by TCAD simulation software.

The work carried out in this thesis systematically investigates the correlation between microstructures and electronic properties of organic semiconductors. The major directions that were pursued in this thesis are: (i) studies on structure-property relationship by rational design and synthesis of monodisperse oligomers with varying chain-lengths (ii) role of electronic properties and aggregation (microstructures) in governing singlet fission (SF). In the first part of the thesis, the optical, structural and charge transport properties of Diketopyrrolopyrrole (DPP)-based oligomers, as a function of the chain length, has been discussed. The energy bands became wider with an increase in chain length and a gain in backbone electron affinity was observed, with an offset in microstructural order. With an increase in chain length, the tendency to form intramolecular aggregates increased as compared to intermolecular aggregates due to the onset of backbone conformational defects and chain folding. An insight into the solid-state packing and microstructural order has been obtained by steady-state and transient spectroscopy, grazing incidence small angle x-ray scattering (GISAXS), atomic force microscopy (AFM) and transmission electron microscopy (TEM) studies. The charge-carrier mobilities varied in accordance with the degree of microstructural order as: dimer > trimer > pentamer. A library of DPP-DPP based trimers was also generated by modifying the donor chromophore (phenyl, thiophene and selenophene) in the oligomer backbone. Highest n-channel mobility of ~0.2 cm2V-1s-1 was obtained which validated that: (a) the effect of solid-state packing predominates the effect of backbone electronic structure on charge carrier mobility. Although oligomers possess lesser backbone defects than polymers in general, their charge carrier mobilities were not comparable to that of 2DPP-OD-TEG polymer, which forms highly oriented and isotropic edge-on crystallites/microstructures in the thin film, shows high n-channel mobility of 3 cm2V-1s-1 and band-like transport ;(b) although delocalized electronic states are achieved at greater chain lengths, the degree of solid-state microstructural order drastically reduces which leads to lower charge carrier mobilities; (c) conformational collapse resulted in lower electron mobilities and an increase in ambipolarity. The later part of the thesis debates on the relative contribution of electronic structure and aggregation (microstructures) in governing singlet fission (SF). Motivated by the recent SF model in carotenoid aggregates, a DPP-DPP based oligomer was synthesized by incorporating a vinylene bridge to imbue “polyene” character in the chromophore. Transient Spectroscopy (TA) measurements were carried out to monitor the formation of triplet states in the oligomer and to probe the occurrence of singlet fission. Although the oligomer exhibits “polyene” character like a typical “carotenoid aggregate”, it did not show singlet fission because of the additional stabilization of the singlet (S1) state which reduces the ∆EST. This study rationalized the importance of judicious control of band structures as well as microstructures to observe the SF phenomenon in this category of chromophores. The novel synthetic protocol provides the scope to tailor DPP-DPP based materials with desired effective conjugation lengths and side chains and can foreshow great prospects for future generation of organic electronics.