Transparent oxide semiconductors (TOSs) are materials that exhibit electrical conduction and optical transparency. The traditional applications of these materials are transparent conducting oxides in flat-panel displays, light-emitting diodes, solar cells, and imaging sensors. Recently, significant research has been driven to extend state-of-the-art applications such as thin-film transistors (TFTs). A new and rapidly developing field is emerging, called transparent electronics. This thesis advances transparent electronics through developing a new technique to fabricate TOSs and demonstrating their applications to active semiconductor devices such as diodes and TFTs. Ion beam assisted evaporation (IBAE) is used to deposit two common TOSs: zinc oxide (ZnO) and indium oxide (In2O3). The detailed material study is carried out through various characterization of their electrical properties, chemical composition, optical properties, crystal structure, intrinsic stress, topology, and morphology, as well as an investigation of thin-film property as a function of the deposition parameters: ion flux and energy, and deposition rate. The study proves that IBAE technique provides the capability for fabricating TOSs with controllable properties. By utilizing the newly developed semiconducting ZnO, p-NiO/i-ZnO/n-ITO and n-ITO/i-ZnO/p-NiO heterostructure photodiodes with a low leakage are proposed and assessed. Analysis of their current-voltage characteristics and current transient behaviour reveals that the dominant source of leakage current stems from the deep defect states in the intrinsic zinc oxide layer, where its dynamic response at low signal levels is limited by the charge trapping. The exploration of the photoconduction mechanism and spectral response confirms that such photodiodes are potentially applicable for ultraviolet (UV) sensors. The comparative study of both device structures provides further insights into the leakage current mechanisms, p-i interface properties, and quantum efficiency. Secondly, with the novel semiconducting In2O3, TFTs are fabricated and evaluated. The device performance is optimized by addressing the source/drain contact issue, lowering the intrinsic channel resistance, and improving the dielectric/channel interface. The best n-channel TFT has a high field-effect mobility of ~30 cm^2/Vs, a high current ON/OFF ratio of ~10^8, and a sub-threshold slope of 2.0 V/decade. More important, high-performance indium oxide TFTs here are integrated with the silicon dioxide and silicon nitride gate dielectrics by conventional plasma-enhanced chemical vapour deposition, which makes indium oxide TFT a competitive alternative for next generation TFTs to meet the technical requirements for flat-panel displays, large area imager arrays, and radio frequency identification tags. The stability study shows that indium oxide TFTs are highly stable with a very small threshold voltage shift under both a long-term constant voltage and long-term current stress. The dynamic behaviour indicates factors that affect the operation speed of such TFTs. A descriptive model is proposed to link the material properties and the processing issues with the device performance to facilitate further research and development of TOS TFTs. The research described in this thesis is one of the first investigations of the fabrication of TOSs by the IBAE and their applications to a variety of thin-film devices, particularly UV sensors and TFTs.

Transparent oxide semiconductors (TOSs) are materials that exhibit electrical conduction and optical transparency. The traditional applications of these materials are transparent conducting oxides in flat-panel displays, light-emitting diodes, solar cells, and imaging sensors. Recently, significant research has been driven to extend state-of-the-art applications such as thin-film transistors (TFTs). A new and rapidly developing field is emerging, called transparent electronics. This thesis advances transparent electronics through developing a new technique to fabricate TOSs and demonstrating their applications to active semiconductor devices such as diodes and TFTs. Ion beam assisted evaporation (IBAE) is used to deposit two common TOSs: zinc oxide (ZnO) and indium oxide (In2O3). The detailed material study is carried out through various characterization of their electrical properties, chemical composition, optical properties, crystal structure, intrinsic stress, topology, and morphology, as well as an investigation of thin-film property as a function of the deposition parameters: ion flux and energy, and deposition rate. The study proves that IBAE technique provides the capability for fabricating TOSs with controllable properties. By utilizing the newly developed semiconducting ZnO, p-NiO/i-ZnO/n-ITO and n-ITO/i-ZnO/p-NiO heterostructure photodiodes with a low leakage are proposed and assessed. Analysis of their current-voltage characteristics and current transient behaviour reveals that the dominant source of leakage current stems from the deep defect states in the intrinsic zinc oxide layer, where its dynamic response at low signal levels is limited by the charge trapping. The exploration of the photoconduction mechanism and spectral response confirms that such photodiodes are potentially applicable for ultraviolet (UV) sensors. The comparative study of both device structures provides further insights into the leakage current mechanisms, p-i interface properties, and quantum efficiency. Secondly, with the novel semiconducting In2O3, TFTs are fabricated and evaluated. The device performance is optimized by addressing the source/drain contact issue, lowering the intrinsic channel resistance, and improving the dielectric/channel interface. The best n-channel TFT has a high field-effect mobility of ~30 cm^2/Vs, a high current ON/OFF ratio of ~10^8, and a sub-threshold slope of 2.0 V/decade. More important, high-performance indium oxide TFTs here are integrated with the silicon dioxide and silicon nitride gate dielectrics by conventional plasma-enhanced chemical vapour deposition, which makes indium oxide TFT a competitive alternative for next generation TFTs to meet the technical requirements for flat-panel displays, large area imager arrays, and radio frequency identification tags. The stability study shows that indium oxide TFTs are highly stable with a very small threshold voltage shift under both a long-term constant voltage and long-term current stress. The dynamic behaviour indicates factors that affect the operation speed of such TFTs. A descriptive model is proposed to link the material properties and the processing issues with the device performance to facilitate further research and development of TOS TFTs. The research described in this thesis is one of the first investigations of the fabrication of TOSs by the IBAE and their applications to a variety of thin-film devices, particularly UV sensors and TFTs.

The higher mobility is needed for thin film transistor (TFT) mainly used to be applied in the larger size flat-panel displays (FPDs). The amorphous metal oxide TFT has mobility higher than 10 cm2/V¡Es and can substitute the poor mobility (<1 cm2/V¡Es) of traditional amorphous silicon TFT, which shows a great potential for the next generation. Due to the superior characteristics in amorphous metal oxide TFT, therefore, the amorphous metal oxide TFT has been studied extensively. Usually, the source/drain with island type device has a large overlapped/contact area that we cannot determine the exact electron path. That the sample of inverted stagger £\-IGZO TFTs with via type device has smaller contact area and can be estimated the electron path. In this thesis, the devices with different M1 overlaps etching stop layer (ESL) via distance, M2 £\-IGZO contact size and the fringe field effect are investigated. Although the characteristics of £\-IGZO TFTs have great performance, the electrical stability under illumination and long term bias stress are still a important issue to study before implement them into display. Thus, the devices with different structures that we mentioned previously are investigated the electrical reliability which are the negative bias stress of gate voltage, hot carrier stress effect and negative bias of illumination. The electron path of via type is extracted by contact resistance which is greater than the distance between S/D via. Experiment results show that the increased offset between M1 and ESL via generates the resistance-liked effect in electrical characteristics. The hot carrier stress effect is independent of M2 £\-IGZO contact size in short channel length devices and there are close depletion lengths in drain side. The negative bias stress of illumination is proceeded in the fringe field effect devices, which results a negative shift of threshold voltage due to the hole trapping.

Abstract With the critical development trend of industry of the world, TFT-LCD industry, following the footstep of semi-conductive industry, has become an important leading industry of Taiwan to the economic policy of the Government. The ¡§Two Trillion Double Star¡¨plan pro- -moted by Industrial Development Bureau fo Taiwan intends to push up the production values of the two industries, semi-conductive and flat panel photonic displayer, to exceed NT$ 1 trillion respectively in 2006. This plan also promotes digital contents and biotechnical industry to be two star industries with high potentials of development. Therefore, TFT- LCD industry is undoubtedly the core industry of the next wave of econo- mic growth in Taiwan. According to the distinguishing characteristics of capital and technology density, short-lived productive cycle, and variable productive technique in TFT-LCD industry, cash flow out of investment activities became the key point to promote the competitiveness with the continuously overcharge in the next generation panel field.In addition, the investors would find that the TFT-LCD panel factories have no ability to support the cash flow out which invested in equipment if they do not ask for finance. In this paper, we attempt to investigate the relationship between variation of cash flow in operation, investment, and finance activities and potential risk of operation in enterprise by financial statement in TFT-LCD industry. In addition, this dissertation commence with ROE and development from Du-Pont Formula. Our research decomposes ROE to fundamental elements in enterprise step by step, such as the construction of cost and expense and the risk of business. Furthermore, we afford a referable approach to estimate performance of companies by Du-Pont Formula. Key Words¡G Thin Film Transistor (TFT), Liquid Crystal Display (LCD),Cash Flow, Risk, Risk Management, Du Pont Equation, Du Pont Ratio.

The instability under bias voltage stress and low mobility of hydrogenated amorphous silicon (a-Si:H) thin film transistor (TFT), produced by plasma enhanced chemical vapor deposition (PECVD) technique, are the main problems impeding the implementation of active matrix arrays for light emitting diode display panels and their peripheral circuitry. Replacing a-Si:H by hydrogenated nanocrystalline silicon film (nc-Si:H) seems a solution due to its higher mobility and better stability. Therefore nc-Si:H TFT was produced and investigated in this thesis. All TFT layers (doped nc-Si:H, intrinsic nc-Si:H and insulator films) were produced separately, characterized by optical (UV-visible and FTIR spectroscopies, XRD) and electrical (current-voltage, I-V) methods, and optimized for TFT application. Afterwards the non self-aligned bottom-gate TFT structure was fabricated by the photolithographic method using 2-mask set. The n+ nc-Si:H films, used for TFT drain/source ohmic contacts, were produced at high H2 dilution and at several RF power densities (PRF). The change of their lateral resistivity (rho) was measured by reducing the film thickness via reactive ion etching. The rho values rise below a critical film thickness, indicating the presence of the disordered and less conductive incubation layer. The optimum PRF for the lowest incubation layer was determined. Among the deposition parameters only increased NH3/SiH4 flow rate ratio improved the insulating properties of the amorphous silicon nitride (a-SiNx:H) films, chosen as the TFT gate dielectric. The electrical characteristics of two TFTs with a-SiNx:H having low leakage current, fabricated at different NH3/SiH4 ratios (~19 and ~28) were compared and discussed. The properties (such as crystallinity, large area uniformity, etc.) of the nc-Si:H film as TFT channel layer, were found to depend on PRF. For the films deposited at the center of the PECVD electrode the change from an amorphous dominant structure to a nanocrystalline phase took place with increasing PRF, whereas those at the edge had always nanocrystalline nature, independent of PRF. The two different TFTs produced at the center of the electrode with a-Si:H and nc-Si:H grown at low and high PRF, respectively, were compared through their I-V characteristics and electrical stability under the gate bias voltage stress. Finally, nc-Si:H TFT structure, produced and optimized in this work, was analyzed through gate-insulator-drain/source capacitor by capacitance-voltage (C-V) measurements within 106-10-2 Hz frequency (F) range. The inversion regime was detected at low F without any external charge injection. Besides, ac hopping conductivity in the nc-Si:H bulk was extracted from the fitting results of the C-F curves.

In this dissertation, a carbon nanotube thin-film transistor is fabricated on a flexible substrate. Combined printing and stamping techniques are used for the fabrication. An ink-jet printing technique is used to form the gate, source, and drain electrodes as well as the dielectric layer. A self aligned carbon nanotube (CNT) thin film is formed by using a new modified dip coat technique before being transferred to the device substrate. This novel modified dip-coat technique utilizes the capillary effect of a liquid solution rising between gaps to coat CNT solution on a large area of the substrate while consuming minimal CNT solution. Several key solutions are addressed to solve the fabrication problems. (1) The source/drain contact with the CNT channel is developed by using droplets of silver ink printed on the source/drain areas prior to applying CNT thin. The wet silver ink droplets allow the silver to "wet" the CNT thin-film area and enable good contact with the source and drain contact after annealing. (2) A passivation layer to protect the device channel is developed by bonding a thin Kapton film on top of the device channel. This thin Kapton film is also used as the media for transferring the aligned CNT thin-film on the device substrate. Using this technique, printing the passivation layer can be avoided, and it prevents the inter-diffusion of the liquid dielectric into the CNT porous thin-film. (3) A simple and cost effective technique to form multilayer metal interconnections on flexible substrate is developed and demonstrated. Contact vias are formed on the second substrate prior bonding on the first substrate. Ink-jet printing is used to fill the silver ink into the via structure. The printed silver ink penetrates through the vias to contact with the contact pads on the on the bottom layer, followed by an anneal process. High drain current of 0.476mA was obtained when V[subscript G]= -3V and source-drain voltage (V[subscript DS]) was -1.5V. A bending test was performed on the CNT TFT showing less than a 10% variation in performance. A bending test was also performed on via structures, which yielded less than a 5% change in resistance. The developed CNT TFT is used to form a switch in a phase shifter for a flexible phased-array antenna (PAA). Four element 1-dimensional and 2-dimensional phased-array antennae are fabricated and characterized. Multilayer metal interconnects were used to make a complete PAA system. For a 2-bit 1x4 PAA system, by controlling the ON/OFF states of the transistors, beam steering of a 5.3GHz signal from 0° to -27° has been demonstrated. The antenna system also shows good stability and tolerance under different bending radii of curvature. A 2-bit 2x2 PAA system was also fabricated and demonstrated. Two dimensional beam steering of a 5.2GHz signal at an angle of [theta]=20.7° and [phi]=45° has been demonstrated. The total efficiency of the 1-dimensional and 2-dimensional PAA systems are 42% and 46%, respectively. / text

The prospect of producing nanometer channel-length thin film transistors (TFTs) for active matrix addressed pixelated arrays opens up new high-performance applications in which the most amenable device topology is the vertical thin film transistor (VTFT) in view of its small area. The previous attempts at fabricating VTFTs have yielded devices with a high drain leakage current, a low ON/OFF current ratio, and no saturation behaviour in the output current at high drain voltages, all induced by short channel effects. To overcome these adversities, particularly dominant as the channel length approaches the nano-scale regime, the reduction of the gate dielectric thickness is essential. However, the problems with scaling the gate dielectric thickness are the high gate leakage current and early dielectric breakdown of the insulator, deteriorating the device performance and reliability. A novel ultra-thin SiNx film suitable for the application as the gate dielectric of short channel TFTs and VTFTs is developed. The deposition is performed in a standard 13.56MHz PECVD system with silane and ammonia precursor gasses diluted in nitrogen. The deposited 50nm SiNx films demonstrate excellent electrical characteristics in terms of a leakage current of 0.1 nA/cm?? and a breakdown electric field of 5.6MV/cm. Subsequently, the state of the art performances of 0.5??m channel length VTFTs with 50 and 30nm thick SiNx gate dielectrics are presented in this thesis. The transistors exhibit ON/OFF current ratios over 10^9, the subthreshold slopes as sharp as 0.23 V/dec, and leakage currents in the fA range. More significantly, a high associated yield is obtained for the fabrication of these devices on 3-inch rigid substrates. Finally, to illustrate the tremendous potential of the VTFT for the large area electronics, a 2.2-inch QVGA AMOLD display with in-pixel VTFT-based driver circuits is designed and fabricated. An outstanding value of 56% compared to the 30% produced by conventional technology is achieved as the aperture ratio of the display. Moreover, the initial measurement results reveal an excellent uniformity of the circuit elements.

The development of functional flexible electronics is essential to enable applications such as conformal medical imagers, wearable health monitoring systems, and flexible light-weight displays. Intensive research on thin-film transistors (TFTs) is being conducted with the goal of producing high-performance devices for improved backplane electronics. However, there are many challenges regarding the performance of devices fabricated at low temperatures that are compatible with flexible plastic substrates. Prior work has reported on the change in TFT characteristics due to mechanical strain, with especially extensive data on the effect of strain on field-effect mobility. This thesis investigates the effect of gate-bias stress and elastic strain on the long-term stability of flexible low-temperature hydrogenated amorphous silicon (a-Si:H) TFTs, as the topic has yet to be explored systematically. An emphasis was placed on bias-stress measurements over time in order to obtain information on the physical mechanisms of instability. Drain current was measured over various intervals of time to track the degradation of devices due to metastability, and results were then compared across devices of various sizes under tensile, compressive, and zero strain. Transfer characteristics of the TFTs were also measured under the different conditions, to allow for extraction of parameters that would provide insight into the instability mechanisms. In addition to parameter extraction, the degradation and recovery of TFT output current was quantitatively compared for various bias-stress times across the different levels of strain. Finally, the instability mechanisms are modelled with a Markov system to further examine the effect of strain on long-term TFT operation. From the analysis of results, it was found that shallow charge trapping in the dielectric is the main mechanism of instability for short bias stress times, and did not seem to be greatly affected by strain. For longer bias stress times of over 10000 seconds, defect creation in the a-Si:H becomes a more significant contributor to instability. Both tension and compression increased defect creation compared to TFTs with zero applied strain. Compression appeared to cause the greatest increase in the rate of defect formation, likely by weakening Si-Si bonds in the a-Si:H. Tension appeared to cause a less significant increase, possibly due to a strengthening of some proportion of the Si-Si bonds caused by the slight elongation of bond length or because the applied tension relieves intrinsic compressive stress in a-Si:H film. A longer conduction path and greater dielectric area appears to increase the bias-stress and strain-related effects. Therefore reducing device size should increase the reliability of flexible TFTs.

Nanolaminate dielectrics combine two or more insulating materials in a many-layered film. These structures can be made to significantly outperform films composed of a single one of their constituent materials by adjusting the composition ratio, arrangement, and size of the component layers. In this work, atomic layer deposition (ALD) is used to fabricate pure-oxide and nanolaminate dielectrics based upon Al₂O₃ and ZrO₂. The relative performance of these dielectrics is investigated with respect to application as gate dielectrics for ZnSnO (ZTO) and InGaZnO (IGZO) amorphous-oxide-semiconductor (AOS) thin-film transistors (TFTs). AOS TFTs are promising candidates for commercial use in applications such as active-matrix displays and e-paper. It was found that the layer thickness, relative composition, and interfacial material all had an effect on TFT performance. Several variants of the Al₂O₃/ZrO₂ nanolaminate were found to exhibit superior properties to either Al₂O₃ or ZrO₂ alone. / Graduation date: 2011

Neste trabalho, são discutidas as características de transistores de filmes finos (TFTs) nos quais nanopartículas de óxido de zinco (ZnO) são empregadas como material ativo na camada semicondutora. O crescimento contínuo do interesse por este componente está associado à busca pelo desenvolvimento da tecnologia de dispositivos eletrônicos flexíveis, transparentes e de baixo custo. TFTs integrados com nanopartículas de ZnO são apresentados, e uma extensa rotina de caracterização elétrica transiente é realizada para avaliar como estes dispositivos se comportam e degradam ao longo do tempo. Foram medidas, ao total, 80 amostras de transistores integrados em duas configurações distintas: inverted staggered e inverted coplanar. A partir das medidas analisadas foram identificados dois grupos de comportamentos elétricos dominantes, os quais foram classificados em: efeitos abruptos e efeitos de memória. A partir dos dados coletados, foram formuladas hipóteses para modelar o comportamento típico observado. Para tanto, utiliza-se dos mecanismos de atividade de traps, de interação da camada semicondutora com o meio ambiente, de polarização de dipolos e difusão de cargas móveis no dielétrico, de formação de caminhos percolados paralelos pelas nanopartículas e de difusão de vacâncias de oxigênio e íons metálicos que podem estar associados ao comportamento elétrico observado. / In this work, the characteristics of thin-film transistors (TFTs) employing nanoparticulated zinc oxide (ZnO) as the active semiconductor channel layer are discussed. The growing interest in this component is associated to the development of low-cost, flexible and transparent electronic devices. The TFTs integrated with ZnO nanoparticles are presented and an extensive transient electrical characterization campaign was performed in order to evaluate how these devices behave and degrade over time. The measurement was performed for 80 samples of two different integration setups: inverted staggered and inverted coplanar. In the performed tests two main disturbances were identified, which were classified as abrupt and memory effects. From the collected data, hypothesis to model the observed typical behavior are formulated. Trapping activity, ambient interaction, dielectric dipoles, mobile charges, formed parallel-paths, oxygen vacancies and metallic ions diffusion are mechanisms that may be associated to the observed behavior.