This work extends the technology of amorphous silicon (a-Si) thin film transistors (TFTs) from traditional switching applications to on-pixel signal amplification for large area digital imaging and in particular, is aimed towards enabling emerging low noise, high resolution and high frame rate medical diagnostic imaging modalities such as digital tomosynthesis. A two transistor (2T) pixel amplifier circuit based on a novel charge-gate thin film transistor (TFT) device architecture is introduced to shrink the TFT based pixel readout circuit size and complexity and thus, improve the imaging array resolution and reliability of the TFT fabrication process. The high resolution pixel amplifier results in improved electrical performance such as on-pixel amplification gain, input referred noise and faster readouts. In this research, a charge-gated TFT that operates as both a switched amplifier and driver is used to replace two transistors (the addressing switch and the amplifier transistor) of previously reported three transistor (3T) APS pixel circuits.. In addition to enabling smaller pixels, the proposed 2T pixel amplifier results in better signal-to-noise (SNR) by removing the large flicker noise source associated with the switched TFT and increased pixel transconductance gain since the large ON-state resistance of the switched TFT is removed from the source of the amplifier TFT. Alternate configurations of 2T APS architectures based on source or drain switched TFTs are also investigated, compared, and contrasted to the gate switched architecture using charge-gated TFT. A new driving scheme based on multiple row resetting is introduced which combined with the on-pixel gain of the APS, offers considerable improvements in imaging frame rates beyond those feasible for PPS based pixels. The novel developed 2T APS architectures is implemented in single pixel test structures and in 88 pixel test arrays with a pixel pitch of 100 µm. The devices were fabricated using an in-house developed top-gate TFT fabrication process. Measured characteristics of the test devices confirm the performance expectations of the 2T architecture design. Based on parameters extracted from fabricated TFTs, the input referred noise is calculated, and the instability in pixel transconductance gain over prolonged operation tine is projected for different imaging frame rates. 2T APS test arrays were packaged and integrated with an amorphous selenium (a-Se) direct x-ray detector, and the x-ray response of the a-Se detector integrated with the novel readout circuit was evaluated. The special features of the APS such as non-destructive readout and voltage programmable on-pixel gain control are verified. The research presented in this thesis extends amorphous silicon pixel amplifier technology into the area of high density pixel arrays such as large area medical X-ray imagers for digital mammography tomosynthesis. It underscores novel device and circuit design as an effective method of overcoming the inherent shortcomings of the a-Si material . Although the developed device and circuit ideas were implemented and tested using a-Si TFTs, the scope of the device and circuit designs is not limited to amorphous silicon technology and has the potential to be applied to more mainstream technologies, for example, in CMOS active pixel sensor (APS) based digital cameras.

This thesis examines strategies to exploit existing materials and techniques to advance organic thin film transistor (OTFT) technology in device performance, device manufacture, and device integration. To enhance device performance, optimization of plasma enhanced chemical vapor deposited (PECVD) gate dielectric thin film and investigation of interface engineering methodologies are explored. To advance device manufacture, OTFT fabrication strategies are developed to enable organic circuit integration. Progress in device integration is achieved through demonstration of OTFT integration into functional circuits for applications such as active-matrix displays and radio frequency identification (RFID) tags. OTFT integration schemes featuring a tailored OTFT-compatible photolithography process and a hybrid photolithography-inkjet printing process are developed. They enable the fabrication of fully-patterned and fully-encapsulated OTFTs and circuits. Research on improving device performance of bottom-gate bottom-contact poly(3,3'''-dialkyl-quarter-thiophene) (PQT-12) OTFTs on PECVD silicon nitride (SiNx) gate dielectric leads to the following key conclusions: (a) increasing silicon content in SiNx gate dielectric leads to enhancement in field-effect mobility and on/off current ratio; (b) surface treatment of SiNx gate dielectric with a combination of O2 plasma and octyltrichlorosilane (OTS) self-assembled monolayer (SAM) delivers the best OTFT performance; (c) an optimal O2 plasma treatment duration exists for attaining highest field-effect mobility and is linked to a “turn-around” effect; and (d) surface treatment of the gold (Au) source/drain contacts by 1-octanethiol SAM limits mobility and should be omitted. There is a strong correlation between the electrical characteristics and the interfacial characteristics of OTFTs. In particular, the device mobility is influenced by the interplay of various interfacial mechanisms, including surface energy, surface roughness, and chemical composition. Finally, the collective knowledge from these investigations facilitates the integration of OTFTs into organic circuits, which is expected to contribute to the development of new generation of all-organic displays for communication devices and other pertinent applications. A major outcome of this work is that it provides an economical means for organic transistor and circuit integration, by enabling use of the well-established PECVD infrastructure, yet not compromising the performance of electronics.

A Voltage Controlled Oscillator (VCO) based pixel and array architecture is reported using amorphous silicon (a-Si) technology for large area digital imaging applications. The objectives of this research are to (a) demonstrate photon quantum noise limited pixel operation of less than 30 input referred noise electrons, (b) theoretically explore the use of the proposed VCO pixel architecture for photon quantum noise limited large area imaging applications, more specifically protein crystallography using a-Si, (c) to implement and demonstrate experimentally a quantum noise limited (VCO) pixel, a small prototype of quantum noise limited (VCO) pixelated array and a quantum noise limited (VCO) pixel integrated with direct detection selenium for energies compatible with a protein crystallography application. Electronic noise (phase noise) and metastability performance of VCO pixels in low cost, widely available a-Si technology will be theoretically calculated and measured for the first time in this research. The application of a VCO pixel architecture in thin film technologies to large area imaging modalities will be examined and a small prototype a-Si array integrated with an overlying selenium X-ray converter will be demonstrated for the first time. A-Si and poly-Si transistor technologies are traditionally considered inferior in performance to crystalline silicon, the dominant semiconductor technology today. This work v aims to extend the reach of low cost, thin film transistor a-Si technology to high performance analog applications (i.e. very low input referred noise) previously considered only the domain of crystalline silicon type semiconductor. The proposed VCO pixel architecture can enable large area arrays with quantum noise limited pixels using low cost thin film transistor technologies.

A Voltage Controlled Oscillator (VCO) based pixel and array architecture is reported using amorphous silicon (a-Si) technology for large area digital imaging applications. The objectives of this research are to (a) demonstrate photon quantum noise limited pixel operation of less than 30 input referred noise electrons, (b) theoretically explore the use of the proposed VCO pixel architecture for photon quantum noise limited large area imaging applications, more specifically protein crystallography using a-Si, (c) to implement and demonstrate experimentally a quantum noise limited (VCO) pixel, a small prototype of quantum noise limited (VCO) pixelated array and a quantum noise limited (VCO) pixel integrated with direct detection selenium for energies compatible with a protein crystallography application. Electronic noise (phase noise) and metastability performance of VCO pixels in low cost, widely available a-Si technology will be theoretically calculated and measured for the first time in this research. The application of a VCO pixel architecture in thin film technologies to large area imaging modalities will be examined and a small prototype a-Si array integrated with an overlying selenium X-ray converter will be demonstrated for the first time. A-Si and poly-Si transistor technologies are traditionally considered inferior in performance to crystalline silicon, the dominant semiconductor technology today. This work v aims to extend the reach of low cost, thin film transistor a-Si technology to high performance analog applications (i.e. very low input referred noise) previously considered only the domain of crystalline silicon type semiconductor. The proposed VCO pixel architecture can enable large area arrays with quantum noise limited pixels using low cost thin film transistor technologies.

Le travail entre dans le cadre de la nouvelle tendance à la recherche d’une électronique mécaniquement flexible basée sur des transistors en couche mince constitués uniquement de matériaux organiques (OTFT). OTFT de type n et de type p ont été fabriqués par la technique de dépôt par impression (inkjet) et étudiés. Les paramètres d’impression (jetabilité, mouillabilité, imprimabilité et possibilité d’obtention de différentes formes), de chaque encre permettant le dépôt de couches conductrices, isolantes et semiconductrices, ont été systématiquement étudiés. Les OTFT de type n basés sur du C60 se sont montrés non fiables, principalement du fait de la faible solubilité du C60 dans les solvants organiques. Les OTFT de type basés sur du Tips-pentacene ont montré par contre une grande fiabilité. Le travail global constitue une large revue des problèmes et difficultés rencontrés dans la fabrication de transistors fabriqués entièrement par impression jet d’encre. Des solutions ont été trouvées et de nouvelles idées sont proposées. / Present work deals with the new trend to get highly flexible electronics by using fully Organic Thin-Film Transistor (OTFT) as the basic element of this electronics. Fully organic n-type as well as p-type OTFT processed by inkjet printing are studied. Printing parameters of each ink, jettability, wetting, printability, and patterns optimization, leading to the deposition of conductive contacts, gate insulator and semiconducting active layer are studied. Process of n-type OTFT based on C60 is shown as unreliable, mainly due to the poor solubility of C60 in organic solvent. In the contrary, p-type OTFTs based on Tips-pentacene are much more reliable. The work is a large overview of the issues and the difficulties that have been to jump and to solve in the way to fabricate fully printed organic transistors. Some solutions have been given and new ideas have been proposed.

Pour réaliser des fonctions électroniques sur support souple, le transistor en couches minces (TFT) est indispensable. Cette thèse a pour objectif d’approfondir les connaissances sur ces dispositifs.L’état de l’art est synthétisé dans le chapitre 1. Cette partie présente tout d’abord les TFT et justifie l’utilisation de l’oxyde d’indium gallium zinc (IGZO). Ensuite les propriétés de cet oxyde semi-conducteur amorphe sont traitées ; et enfin le chapitre fait état des résultats obtenus avec des TFT en IGZO.Le chapitre 2 établie un lien entre les propriétés de l’IGZO et le dépôt par pulvérisation cathodique. L’étude des films a été réalisée par ellipsométrie spectroscopique. Celle-ci a mis en évidence des variations dans les propriétés optiques dues au temps de dépôt, à la concentration en oxygène et à la position sur le substrat. Ces résultats ont été comparés à des mesures de résistivité, pour comprendre plus précisément la cause de ces variations.Le chapitre 3 élabore un procédé complet permettant de réaliser des TFT sur support souple. Le choix des différents matériaux est discuté, et les différents outils de procédés sont adaptés afin de réaliser ces dispositifs. Les TFT obtenus sont caractérisés en fonction du temps de recuit et sous flexion. Ils ont atteint des mobilités 10 cm².V-1.s-1.Le chapitre 4 étudie le dépôt d’IGZO par impression jet d’encre. Une encre a été formulée et les différents paramètres d’impression ajustés. Afin de comparer les différentes techniques de dépôt, des TFT avec canal en IGZO imprimé ont été réalisé et les films imprimés ont été caractérisé par ellipsométrie spectroscopique. Ces dispositifs ont atteint des mobilités de 0,4 cm2.V-1.s-1. / In order to carry out electronics functions on flexible substrate, thin film transistor is essential. The aim of this thesis is to increase knowledge on this device.State of art of IGZO TFT is summarized in chapter 1. This part presents thin film transistor and justify the choice of IGZO as the semiconductor material. Then, properties of this amorphous oxide semiconductor are discussed. Finally, this chapter presents the results obtained in the literature for IGZO based thin film transistor.Chapter 2 establishes a link between IGZO properties and sputtering deposition. Films are studied by spectroscopic ellipsometry. Experiments show variations in optical properties due to deposition time, oxygen content and position on the wafer. Resistivity measurements are carried out to understand more deeply the causes of these variations.Chapter 3 develops a complete process to achieve TFT on flexible substrate. The choice of different materials and processes is discussed. The performances of the TFT are investigated versus the annealing time and characterized under mechanical stress. Mobility up to 10 cm2.V-1.s-1 can be achieved after an annealing at 300°C during 1h30. Mechanical stresses show a degradation of the transistor induced by cracks in the oxide layer.Chapter 4 focuses on IGZO's deposition by inkjet printing. An ink is formulated using metallic salts and a solvents mixture. The parameters of the printing system are also optimized. To compare the different techniques of deposition, printed IGZO TFTs are characterized and compared with the one fabricated with the standard PVD deposition technique. Mobility is relatively lower and equals 0.4 cm2.V-1.s-1.

Ce travail a pour objectifs d'apporter des connaissances au niveau des propriétés électriques de transistors en couches minces (TFTs) à base de silicium polymorphe (pm-Si :H), ainsi qu'au niveau de la structure du matériau polymorphe. Nous nous sommes également intéressé à une nouvelle méthode de cristallisation d'une couche de silicium amorphe par interférométrie laser qui présente un fort potentiel pour le développement de matrice active en silicium polycristallin de grandes dimensions. Nous avons d'abord mis en évidence un courant OFF plus faible dans les TFTs en pm-Si :H que dans les TFTs en silicium microcristallin (µc-Si :H). Nos études ont également montré que les TFTs en pm-Si :H ne sont pas, ou très peu, sujet à la contamination par l'oxygène lors du procédé de fabrication, problème rencontré dans la fabrication des TFTs en µc-Si :H. Nous avons ensuite étudié la dérive de la tension de seuil lorsque les TFTs sont stressés électriquement. Nous avons mis en évidence des résultats similaires à ceux observer dans les TFTs en silicium amorphe (a-Si :H), à savoir que la création de défauts dans la couche active est le mécanisme responsable de la dérive de VT pour des tensions de grille faibles et des temps de stress courts, alors que le piégeage de charges dans le nitrure de grille est responsable de la dérive de VT lorsque les tensions de grille sont élevées et les temps de stress longs. Il s'est avéré que les TFTs en pm-Si :H sont plus stables que les TFTs en a-Si :H. Dans un second temps, les analyses structurales de films minces de pm-Si :H ont montré la présence de cristallites de quelques nanomètres dans la couche. De même, nous avons isolé le signal de diffraction de rayons X d'une telle couche et mis en évidence une organisation structurale à plus grande distance que pour le silicium amorphe, ce qui est cohérent avec les résultats des stress électriques. Pour finir, nous avons étudié une méthode de cristallisation du a-Si par interférences laser 4 faisceaux. Nous avons observé une structuration périodique de la couche dans un système cubique face centrée. Les observations TEM ont montré que la couche était bien cristallisée. Les observations MEB suite à la révélation des joints de grains ont montré ce qu'il semble être un réseau de germes de µc-SiH avec un pas de 652 nm et la présence continue de grains et de joints de grains entre ces germes. / This work aims to provide knowledge on electrical properties of thin-film transistors(TFTs) based on polymorphous silicon (pm-Si: H), and on polymorphous material structure.We also focused on a new method of crystallization of amorphous silicon layer by laserinterferometry, which has great potential for the development of active matrix flat paneldisplays based on polysilicon.We first identified a lower OFF current in TFTs based on pm-Si: H than inmicrocrystalline silicon (μc-Si: H) TFTs. Our studies have also shown that pm-Si: H TFTs donot present oxygen contamination during the fabrication process, which is a problemencountered in the fabrication of μc-Si:H TFTs. We then studied the threshold voltage shift ofpm-Si:H TFTs under electrical stress. We have found results similar to those observed inamorphous silicon TFTs (a-Si:H), namely, defects creation in the active layer which isresponsible for the threshold voltage shift (ΔVT) for low gate voltage and short times stress,and charge trapping in the gate silicon nitride is responsible for ΔVT for high gate voltage andlong time stress. We also shown that pm-Si:H TFTs are more stable under electrical stressthan a-Si:H TFT.In a second step, the structural analysis of thin films of pm-Si: H revealed the presence ofcrystallites about few nanometers in the polymorphous layer. Similarly, we isolated the X-raydiffraction signal of polymorphous layer and revealed a structural organization at larger rangethan in amorphous silicon layer, which is consistent with the results of electrical stress.Finally, we studied a method of crystallization of a-Si by 4-beams laser interferences. Weobserved a periodic structure of the layer in a face-centered cubic system. TEM observationsshowed that the layer was well crystallized. SEM observations after revelation of grainboundaries showed what appears to be a network of μc-Si seed with a pitch of 652 nm and thepresence of a continued layer of grains and grain boundaries between these seeds.

Organic thin film transistors (OTFT) are a key active devices of future organic electronic circuits. The biggest advantages of organic electronics are the potential for cheep production and the enabling of new applications for light, bendable or transparent devices. These benefits are offered by a wide spectrum of various molecules and polymers that are optimized for different purpose. In this work, several interesting organic semiconductors are compared as well as transistor geometries and processing steps. In a cooperation with an industrial partner, test series of transistors are produced that are intensively characterized and used as a basis for later device simulation. Therefore, among others 4-point-probe measurements are used for a potential mapping of the transistor channel and via transfer line method the contact resistance is measured in a temperature range between 173 and 353 K. From later comparison with the simulation models, it appears that the geometrical resistance is actually more important for the transistor performance than the resistance of charge-carrier injection at the electrodes. The charge-carrier mobility is detailed evaluated and discussed. Within the observed temperature range a Arrhenius-like thermal activation of the charge- carrier transport is determined with an activation energy of 170 meV. Furthermore, a dependence of the electric field-strength of a Poole-Frenkel type is found with a Poole-Frenkel factor of about 4.9 × 10E−4 (V/m) −0.5 that is especially important for transistors with small channel length. With these two considerations, already a good agreement between device simulation and measurement data is reached. In a detailed discussion of the dependence on the charge-carrier density and from comparison with established the charge-carrier mobility models, an exponential density of states could be estimated for the organic semiconductor. However, reliability of OTFTs remains one of the most challenging hurdles to be understood and resolved for broad commercial applications. In particular, bias-stress is identified as the key instability under operation for numerous OTFT devices and interfaces. In this work, a novel approach is presented that allows controlling and significantly alleviating the bias-stress effect by using molecular doping at low concentrations. For pentacene as semiconductor and SiO2 as gate oxide, we are able to reduce the time constant of degradation by three orders of magnitude. The effect of molecular doping on the bias-stress is explained in terms of the shift of Fermi level and, thus, exponentially reduced proton generation at the pentacene/oxide interface. For transistors prepared in cooperation with the industrial partner, a second effect is observed that can be explained by a model considering a ferroelectric process in the dielectric and counteracts the bias-stress behavior.:1. Introduction and Motivation 10 2. Organic Semiconductors and Thin-Film Transistors 12 2.1. Fundamentals of Organic Semiconductors 12 2.1.1. Structural and Electronic Properties 12 2.1.2. Polarons and Trap States 15 2.1.3. Doping of Organic Semiconductors 16 2.2. Charge-Carrier Transport in Organic Semiconductors 18 2.2.1. Field-Effect Mobility 18 2.2.2. Gaussian Disorder Model 21 2.2.3. Variable-Range Hopping Models 24 2.2.4. Fishchuk Model 26 2.3. Organic Field-Effect Transistors 27 2.3.1. Transistor Geometry 27 2.3.2. Transistor Equations 29 2.3.3. Evaluation of Mobility 32 2.3.4. Threshold Voltage 34 2.3.5. Contact Resistance 35 2.3.6. Au-SAMs 38 2.3.7. Dielectric 39 2.3.8. Scaling and Short Channel Effects 41 2.3.9. Stability and Bias-Stress 43 2.4. Device Simulation 44 3. Materials and Methods 46 3.1. Materials 46 3.2. Sample Preparation 50 3.2.1. Sample Preparation in cooperation with the industrial partner 51 3.2.2. Sample Preparation at IAPP 52 3.2.3. Staggered Transistors at IAPP 56 3.3. Sample Characterization 57 3.3.1. Electrical Measurement Setup 57 3.3.2. Parameter Extraction 60 3.3.3. Contact Resistance 61 3.3.4. Kelvin-Probe Atomic Force Microscopy 64 3.3.5. UPS Measurement 65 4. Organic Field-Effect Transistors - Experiment and Simulation 67 4.1. Bottom-Gate Transistors 67 4.1.1. Semiconductors 67 4.1.2. Bipolar Transport 72 4.1.3. Electrode Treatments 74 4.1.4. Channel Treatments 77 4.1.5. Polymer Transistors 79 4.2. Polymer Transistors at Room Temperature 85 4.2.1. Parameter Extraction 85 4.2.2. Four-Point-Probe Measurements 90 4.2.3. Transferline Methode 96 4.2.4. UPS Measurements 100 4.3. Cryostat Measurements 102 4.3.1. Transistor Characteristics 102 4.3.2. Contact Resistance 105 4.3.3. Density of States 107 4.4. Transistor Simulation 110 4.4.1. Introduction of Device Simulation with Genius 110 4.4.2. Mesh and Geometry 111 4.4.3. Contact Resistance of Charge-Carrier Injection 112 4.4.4. Temperature Dependent Simulations 114 4.4.5. Implementation of Donor Traps 116 4.4.6. Poole-Frenkel Discussion 118 4.4.7. Contact Resistance of Geometry 122 4.4.8. Simulation with Advanced Mobility Models 123 4.5. Bias-Stress Reliability 128 4.5.1. Bias-Stress Phenomena 128 4.5.2. Doped Transistors 136 4.5.3. Polymer Transistors 145 5. Conclusion and Outlook 150 A. Appendix 154 A.1. Charge-Carrier Mobility measurements for solar cell materials 154 A.2. Simulation pictures 154 B. Bibliography 160

<p>As  thefundamentallimits  of  two-dimensional(2D)geometric  scaling  of  commercial transistors  are  being reached,  there  is  tremendous  demand  for  new  materials  and  process innovations  that  can  keep  delivering  performance  improvements  for  future  generations  of computing chips. One major avenue being explored istheincorporation ofan increasing degree of three-dimensionality   by   vertically   stacking   logic   and   memory   layerswith   high-density interconnections.In  this  dissertation,  high-performanceultra-thin  amorphousindium  oxide transistors  are  demonstrated as  an  excellent  candidate  for these  back-end-of-line  (BEOL)  and monolithic 3D (M3D) integration applications.</p> <p>A  major  pain-point  in the  development  of  BEOL  and  M3D  systems is  the  strict  thermal budget imposed –once the bottom layer of devices is fabricated, they can generally withstand no more  than  400 °C.  It  is  exceedingly  difficult  to  directly  deposit  single-crystal  material  at  these temperatures, and polycrystalline materials will have grain boundary instability issues. Amorphous materials  generally  have  low  carrier  mobilities,  which  would  seemingly  remove  them  from contention as well. Indium oxideand itsclass of related metal oxides are exceptions. Indium oxideis  a  wide  bandgap  semiconductor  with  high  electron  mobility  up  to  about  100  cm²/V∙s  in amorphous form. Ithas a strong preference for native degenerate n-type doping which has hindered prior  devices  fabricated  with it.  In  this  dissertation,  extremely  thin  layers  on  the  order  of  1  nm thick are used for which quantum confinement effects widen the bandgap further, reliably enabling gate-controllable  carrier  densitiesand  demonstration  of  excellent  transistor  performance  with  a low thermal budget of just 225 °C.</p> <p>Detailed characterization is performed down to 40 nm channel lengths revealing excellent transistor characteristics  includingenhancement-mode operation withon currents greater than 2 A/μm, low  subthreshold  swing,and  high  on/off  ratios  due  to  the  wide  bandgap.  Subsequent chaptersdemonstrate the fundamental lower limits of off current around 6 ×10^-20A/μmby a novel measurement  technique,  good  gate  bias  stress  stability  behaviorwith  small  parameter  drift  at silicon  complementary  metal  oxide  semiconductor  (CMOS)  logic  voltages,  and  high-frequency operationin the GHz regime enabling easy operation at CMOS clock frequencies.</p>

Amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) constitute the central theme of this thesis. Within this theme, three primary areas of focus are pursued. The first focus is the realization of a transparent three-stage ring oscillator with buffered output and an output frequency in the megahertz range. This leads to the possibility of transparent radio frequency applications, such as transparent RFID tags. At the time of its fabrication, this ring oscillator was the fastest oxide electronics ring oscillator reported, with an output frequency of 2.16 MHz, and a time delay per stage of 77 ns. The second focus is to ascertain whether a three-terminal device (i.e., a TFT) is an appropriate structure for conducting space-charge-limited-current (SCLC) measurements. It is found that it is not appropriate to use a diode-tied or gate-biased TFT configuration for conducting a SCLC assessment since square-law theory shows that transistor action alone gives rise to I proportional to V² characteristics, which can easily be mistakenly attributed to a SCLC mechanism. Instead, a floating gate TFT configuration is recommended for accomplishing SCLC assessment of AOS channel layers. The final focus of this work is to describe an assessment procedure appropriate for determining if a dielectric is suitable for use as a TFT gate insulator. This is accomplished by examining the shape of a MIM capacitor's log(J)-ξ curve, where J is the measured current density and ξ is the applied electric field. An appropriate dielectric for use as a TFT gate insulator will have a log(J)-ξ curve that expresses a clear breakover knee, indicating a high-field conduction mechanism dominated by Fowler-Nordheim tunneling. Such a dielectric produces a TFT with a minimal gate leakage which does not track with the drain current in a log(I[subscript D])-V[subscript GS] transfer curve. An inappropriate dielectric for use as a TFT gate insulator will have a log(J)-ξ curve that does not express a clear breakover knee, indicating that the dominate conduction mechanism is defect driven (i.e., pin-hole like shunt paths) and, therefore, the dielectric is leaky. It is shown that experimental log(J)-ξ leakage curves can be accurately simulated using Ohmic, space-charge-limited current (SCLC), and Fowler-Nordheim tunneling conduction mechanisms. / Graduation date: 2010