The hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) are widely used as switching elements in LCD displays and large area matrix addressed senor arrays. In recent years, a-Si:H TFTs have been used as analog active components in OLED displays. However, a-Si:H TFTs exhibit a bias induced metastability. This problem causes both threshold voltage and subthreshold slope to shift with time when a gate bias is applied. These instabilities jeopardize the long-term performance of a-Si:H TFT circuits. Nevertheless a-Si:H TFTs show an exponential transfer characteristic in the subthreshold region. Moreover, the typical power consumptions for TFTs in the subthreshold region are in the order of nano-watts, thus making them suitable for low power design. For these reasons, a-Si:H TFT I-V characteristics in the forward subthreshold operation are investigated. First, we have derived the static and dynamic models of a-Si:H TFT in the forward subthreshold region. Second, we have verified our theoretical models with experimental results. Third, we have proven that a-Si:H TFT experiences no subthreshold slope degradation or threshold voltage shift in the forward subthreshold operation. Finally, we have studied a-Si:H TFT current mirror circuit applications. Measurements regarding the fidelity of current matching in the forward subthreshold region have been performed, and results are shown.

Proteins are commonly found molecules in biological systems: our fingernails, hair, skin, blood, muscle, and eyes are all made of protein. Many diseases simply arise because a protein is not folded properly. Therefore, knowledge of protein structure is considered a prerequisite to understanding protein function and, by extension, a cornerstone for drug design and for the development of therapeutic agents. Protein crystallography is a tool that allows structural biologists to discern protein structures to the highest degree of detail possible in three dimensions. The recording of x-ray diffraction data from the protein crystal is a central part of protein crystallography. As such, an important challenge in protein crystallography research is to design x-ray detectors to accurately determine the structures of proteins. This research presents the design and evaluation of a solid-state large area at panel detector for protein crystallography based on an amorphous selenium (a-Se) x-ray sensitive photoconductor operating in avalanche mode integrated with an amorphous silicon (a-Si:H) charge storage and readout pixel. The advantages of the proposed detector over the existing imaging plate (IP) and charge coupled device (CCD) detectors are large area, high dynamic range coupled to single x-ray detection capability, fast readout, high spatial resolution, and inexpensive manufacturing process. The requirement of high dynamic range is crucial for protein crystallography since both weak and strong diffraction spots need to be imaged. The main disadvantage of a-Si:H thin film transistor (TFT) array is its high electronic noise which prohibits quantum noise limited operation for the weak diffraction spots. To overcome the problem, the x-ray to charge conversion gain of a-Se is increased by using its internal avalanche multiplication gain. Since the detector can be made approximately the same size as the diffraction pattern, it eliminates the need for image demagnification. The readout time of the detector is usually within the ms range, so it is appropriate for crystallographic application. The optimal detector parameters (such as, detector size, pixel size, thickness of a-Se layer), and operating parameters (such as, electric field across the a-Se layer) are determined based on the requirements for protein crystallography. A complete model of detective quantum efficiency (DQE) of the detector is developed to predict and optimize the performance of the detector. The performance of the detector is evaluated in terms of readout time (< 1 s), dynamic range (~10^5), and sensitivity (~ 1 x-ray photon), thus validating the detector's efficacy for protein crystallography. The design of an in-house a-Si:H TFT pixel array for integration with an avalanche a-Se layer is detailed. Results obtained using single pixel are promising and highlight the feasibility of a-Si:H pixels coupled with avalanche a-Se layer for protein crystallography application.

Novel electrophoresis devices for protein and DNA separation and identification have been presented and studied. The new device utilizes a contact resistance change detection method to identify protein and DNA in situ. The devices were prepared with a microelectronic micromechanical system (MEMS) fabrication method. Three model proteins and six DNA fragments were separated by polyacrylamide gel microchannel electrophoresis and surface electrophoresis. The detection of the proteins or DNA fragments was accomplished using the contact resistance increase of the detection electrode due to adsorption of the separated biomolecules. Key factors for the success of these devices were the optimization of fabrication process and the enhancement of detection efficiency of the devices. Parameters, such as microchannel configuration, size of electrode, and affinity of protein or polyacrylamide gel to the microchannel sidewall and bottom surface were explored in detail. For DNA analysis, the affinity to the bottom surface of the channel was critical. The surface modification method was used to enhance the efficiency of the microchannel surface electrophoresis device. The adsorption of channel separated protein and DNA on the detection electrode was confirmed with the electron spectroscopy for chemical analysis (ESCA) method. The electrical current (I) from the protein microchannel electrophoresis was usually noisy and fluctuated at the early stage of the electrophoresis process. In order to remove the current perturbation, an amorphous silicon (a-Si:H) thin film transistor (TFT) was connected to the microchannel device. The self-aligned a-Si:H TFT was fabricated with a two-photomask process. The result shows that the attachment of the TFT successfully suppressed the current fluctuation of the microchannel electrophoresis process. In summary, protein and DNA samples were effectively separated and detected with the novel TFT-driven or surface microchannel electrophoresis device.

abstract: Due to diminishing availability of 3He, which is the critical component of neutron detecting proportional counters, large area flexible arrays are being considered as a potential replacement for neutron detection. A large area flexible array, utilizing semiconductors for both charged particle detection and pixel readout, ensures a large detection surface area in a light weight rugged form. Such a neutron detector could be suitable for deployment at ports of entry. The specific approach used in this research, uses a neutron converter layer which captures incident thermal neutrons, and then emits ionizing charged particles. These ionizing particles cause electron-hole pair generation within a single pixel's integrated sensing diode. The resulting charge is then amplified via a low-noise amplifier. This document begins by discussing the current state of the art in neutron detection and the associated challenges. Then, for the purpose of resolving some of these issues, recent design and modeling efforts towards developing an improved neutron detection system are described. Also presented is a low-noise active pixel sensor (APS) design capable of being implemented in low temperature indium gallium zinc oxide (InGaZnO) or amorphous silicon (a-Si:H) thin film transistor process compatible with plastic substrates. The low gain and limited scalability of this design are improved upon by implementing a new multi-stage self-resetting APS. For each APS design, successful radiation measurements are also presented using PiN diodes for charged particle detection. Next, detection array readout methodologies are modeled and analyzed, and use of a matched filter readout circuit is described as well. Finally, this document discusses detection diode integration with the designed TFT-based APSs. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2014

In today’s electronics, transistors are the main building blocks of the vast majority of electronic devices and integrated circuits. Types of transistors vary depending on the device structure and operation principle. Metal-oxide-based thin film transistors (MO TFTs), in particular, are an emerging technology that has a promising future in many applications, such as large-area display and wearable electronics. It exhibits unique features that make it superior to the existing Si-based technology, such as optical transparency and mechanical flexibility. However, some technical challenges in MO TFTs limit their emplyoment in today’s applications, such as low carrier mobility and high processing temperature. Solution-processed MO TFT based on spray pyrolysis combined with a carefully engineered TFT structure offers a dramatically enhance carrier mobility at low processing temperature. In this work, we are utilizing spray pyrolysis to grow In2O3 and ZnO based TFTs at low processing temperature. The structural effects of the channel layer on the electrical performance is investigated in two parts. The first part highlights the impact of thickness of the channel layer on the device performance of both In2O3 and ZnO, while the second part explores In2O3/ZnO heterojunction-based active layer. The results showed that increasing the channel thickness of both In2O3 and ZnO based TFTs enhanced the carrier mobility due to a reduced surface-roughness scattering effect. In addition, evidence showed that the electron transport mechanism in In2O3/ZnO heterojunction transitioned from trap-limited conduction (TLC) to percolation conduction (PC) process. Thanks to the existence of a 2D-confined electron sheet at the atomically sharp In2O3/ZnO heterointerface, the electron mobility was dramatically enhanced.

This dissertation presents a unique concept for a device architecture named the nanotube (NT) architecture, which is capable of higher drive current compared to the Gate-All-Around Nanowire architecture when applied to heterostructure Tunnel Field Effect Transistors. Through the use of inner/outer core-shell gates, heterostructure NT TFET leverages physically larger tunneling area thus achieving higher driver current (ION) and saving real estates by eliminating arraying requirement. We discuss the physics of p-type (Silicon/Indium Arsenide) and n-type (Silicon/Germanium hetero-structure) based TFETs. Numerical TCAD simulations have shown that NT TFETs have 5x and 1.6 x higher normalized ION when compared to GAA NW TFET for p and n-type TFETs, respectively. This is due to the availability of larger tunneling junction cross sectional area, and lower Shockley-Reed-Hall recombination, while achieving sub 60 mV/dec performance for more than 5 orders of magnitude of drain current, thus enabling scaling down of Vdd to 0.5 V. This dissertation also introduces a novel thin-film-transistors architecture that is named the Wavy Channel (WC) architecture, which allows for extending device width by integrating vertical fin-like substrate corrugations giving rise to up to 50% larger device width, without occupying extra chip area. The novel architecture shows 2x higher output drive current per unit chip area when compared to conventional planar architecture. The current increase is attributed to both the extra device width and 50% enhancement in field effect mobility due to electrostatic gating effects. Digital circuits are fabricated to demonstrate the potential of integrating WC TFT based circuits. WC inverters have shown 2× the peak-to-peak output voltage for the same input, and ~2× the operation frequency of the planar inverters for the same peak-to-peak output voltage. WC NAND circuits have shown 2× higher peak-to-peak output voltage, and 3× lower high-to-low propagation delay times when compared to their planar counterparts. WC NOR circuits have shown 70% higher peak-to-peak output voltage, over their planar counterparts. Finally, a WC based pass transistor logic multiplexer circuit is demonstrated, which has shown more than 5× faster high-to-low propagation delay compared to its planar counterpart at a similar peak-to-peak output voltage.

京都大学 / 新制・課程博士 / 博士(情報学) / 甲第24746号 / 情博第834号 / 新制||情||140(附属図書館) / 京都大学大学院情報学研究科通信情報システム専攻 / (主査)教授 佐藤 高史, 教授 橋本 昌宜, 教授 新津 葵一 / 学位規則第4条第1項該当 / Doctor of Informatics / Kyoto University / DFAM

Neste trabalho, são discutidas as características de transistores de filmes finos (TFTs) nos quais nanopartículas de óxido de zinco (ZnO) são empregadas como material ativo na camada semicondutora. O crescimento contínuo do interesse por este componente está associado à busca pelo desenvolvimento da tecnologia de dispositivos eletrônicos flexíveis, transparentes e de baixo custo. TFTs integrados com nanopartículas de ZnO são apresentados, e uma extensa rotina de caracterização elétrica transiente é realizada para avaliar como estes dispositivos se comportam e degradam ao longo do tempo. Foram medidas, ao total, 80 amostras de transistores integrados em duas configurações distintas: inverted staggered e inverted coplanar. A partir das medidas analisadas foram identificados dois grupos de comportamentos elétricos dominantes, os quais foram classificados em: efeitos abruptos e efeitos de memória. A partir dos dados coletados, foram formuladas hipóteses para modelar o comportamento típico observado. Para tanto, utiliza-se dos mecanismos de atividade de traps, de interação da camada semicondutora com o meio ambiente, de polarização de dipolos e difusão de cargas móveis no dielétrico, de formação de caminhos percolados paralelos pelas nanopartículas e de difusão de vacâncias de oxigênio e íons metálicos que podem estar associados ao comportamento elétrico observado. / In this work, the characteristics of thin-film transistors (TFTs) employing nanoparticulated zinc oxide (ZnO) as the active semiconductor channel layer are discussed. The growing interest in this component is associated to the development of low-cost, flexible and transparent electronic devices. The TFTs integrated with ZnO nanoparticles are presented and an extensive transient electrical characterization campaign was performed in order to evaluate how these devices behave and degrade over time. The measurement was performed for 80 samples of two different integration setups: inverted staggered and inverted coplanar. In the performed tests two main disturbances were identified, which were classified as abrupt and memory effects. From the collected data, hypothesis to model the observed typical behavior are formulated. Trapping activity, ambient interaction, dielectric dipoles, mobile charges, formed parallel-paths, oxygen vacancies and metallic ions diffusion are mechanisms that may be associated to the observed behavior.

Fabrication techniques and process integration considerations for amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) constitute the central theme of this dissertation. Within this theme three primary areas of focus are pursued. The first focus involves formulating a general framework for assessing passivation. Avoiding formation of an undesirable backside accumulation layer in an AOS bottom-gate TFT is accomplished by (i) choosing a passivation layer in which the charge neutrality level is aligned with (ideal case) or higher in energy than that of the semiconductor channel layer charge neutrality level, and (ii) depositing the passivation layer in such a manner that a negligible density of oxygen vacancies are present at the channel-passivation layer interface. Two AOS TFT passivation schemes are explored. Sputter-deposited zinc tin silicon oxide (ZTSO) appears promising for suppressing the effects of negative bias illumination stress (NBIS) with respect to ZTO and IGZO TFTs. Solution-deposited silicon dioxide is used as a barrier layer to subsequent PECVD silicon dioxide deposition, yielding ZTO TFT transfer curves showing that the dual-layer passivation process does not significantly alter ZTO TFT electrical characteristics. The second focus involves creating an adaptable back-end process compatible with flexible substrates. A detailed list of possible via formation techniques is presented with particular focus on non-traditional and adaptable techniques. Two of the discussed methods, "hydrophobic surface treatment" and "printed local insulator," are demonstrated and proven effective. The third focus is printing AOS TFT channel layers in order to create an adaptable and additive front-end integrated circuit fabrication scheme. Printed zinc indium aluminum oxide (ZIAO) and indium gallium zinc oxide (IGZO) channel layers are demonstrated using a SonoPlot piezoelectric printing system. Finally, challenges associated with printing electronic materials are discussed. Organic-based solutions are easier to print due to their ability to "stick" to the substrate and form well-defined patterns, but have poor electrical characteristics due to the weakness of organic bonds. Inorganic aqueous-based solutions demonstrate good electrical performance when deposited by spin coating, but are difficult to print because precise control of a substrate's hydrophillic/hydrophobic nature is required. However, precise control is difficult to achieve, since aqueous-based solutions either spread out or ball up on the substrate surface. Thickness control of any printed solution is always problematic due to surface wetting and the elliptical thickness profile of a dispensed solution. / Graduation date: 2013

The development of functional flexible electronics is essential to enable applications such as conformal medical imagers, wearable health monitoring systems, and flexible light-weight displays. Intensive research on thin-film transistors (TFTs) is being conducted with the goal of producing high-performance devices for improved backplane electronics. However, there are many challenges regarding the performance of devices fabricated at low temperatures that are compatible with flexible plastic substrates. Prior work has reported on the change in TFT characteristics due to mechanical strain, with especially extensive data on the effect of strain on field-effect mobility. This thesis investigates the effect of gate-bias stress and elastic strain on the long-term stability of flexible low-temperature hydrogenated amorphous silicon (a-Si:H) TFTs, as the topic has yet to be explored systematically. An emphasis was placed on bias-stress measurements over time in order to obtain information on the physical mechanisms of instability. Drain current was measured over various intervals of time to track the degradation of devices due to metastability, and results were then compared across devices of various sizes under tensile, compressive, and zero strain. Transfer characteristics of the TFTs were also measured under the different conditions, to allow for extraction of parameters that would provide insight into the instability mechanisms. In addition to parameter extraction, the degradation and recovery of TFT output current was quantitatively compared for various bias-stress times across the different levels of strain. Finally, the instability mechanisms are modelled with a Markov system to further examine the effect of strain on long-term TFT operation. From the analysis of results, it was found that shallow charge trapping in the dielectric is the main mechanism of instability for short bias stress times, and did not seem to be greatly affected by strain. For longer bias stress times of over 10000 seconds, defect creation in the a-Si:H becomes a more significant contributor to instability. Both tension and compression increased defect creation compared to TFTs with zero applied strain. Compression appeared to cause the greatest increase in the rate of defect formation, likely by weakening Si-Si bonds in the a-Si:H. Tension appeared to cause a less significant increase, possibly due to a strengthening of some proportion of the Si-Si bonds caused by the slight elongation of bond length or because the applied tension relieves intrinsic compressive stress in a-Si:H film. A longer conduction path and greater dielectric area appears to increase the bias-stress and strain-related effects. Therefore reducing device size should increase the reliability of flexible TFTs.