The potential failure in through-silicon vias (TSVs) still poses a challenge in trying to extend the useful life of a 3D integrated circuit (IC). A model is proposed to mitigate the communication problem in 3D integrated circuits caused by the breaks at the TSVs. We provide the details of a low-complexity network that takes advantages of redundant TSVs to make it possible to re-route around breaks and maintain effective communication between layers. Different configurations for the micronetwork are analyzed and discussed. We also present an evaluation of the micronetwork's performance, which turns out to be quite promising, based on several Monte Carlo simulations. Finally, we provide some directions for future research on the subject.

A key challenge for three dimensional (3D) integrated circuits (ICs) is thermal management. There are two main thermal challenges in typical 3D ICs. First, in the homogeneous integration with multiple high-power tiers, an effective cooling solution that scales with the number of dice in the stack is needed. Second, in the heterogeneous integration, an effective thermal isolation solution is needed to ‘protect’ the low-power tier from the high-power tier. This research focuses to address these two thermal challenges through hybrid microfluidic cooling and thermal isolation technologies. Within-tier microfluidic cooling is proposed and demonstrated to cool a stack with multiple high-power tiers. Electrical thermal co-analysis is performed to understand the trade-offs between through silicon via (TSV) parasitics and heat sink performance. A TSV-compatible micropin-fin heat sink is designed, fabricated and thermally characterized in a single tier, and benchmarked with a conventional air-cooled heat sink. The designed heat sink has a thermal resistance of 0.269 K·cm2/W at a flow rate of 70 mL/min. High aspect ratios TSVs (18:1) are integrated in the micropin-fins. Within-tier microfluidic cooling is then implemented in 3D stacks to emulate different heating scenarios, such as memory-on-processor and processor-on-processor. Air gap and mechanically flexible interconnects (MFIs) are proposed for the first time to decrease the vertical thermal coupling between high-power (e.g. processor) and low-power tiers (e.g. memory or nanophotonics). A two-tier testbed with the proposed thermal isolation technology is designed, fabricated and tested. Compared with conventional 3D integration approach, thermal isolation technology helps reduce the temperature at a fixed location in the low-tier by 12.9 °C. The resistance of a single MFI is measured to be 46.49 mΩ.

Physical scaling limits of microelectronic devices and the need to improve electrical performance have driven significant research and development into 3D architecture. The development of die stacks in first level packaging is one of the more viable short-term options for improved performance. Placement of memory die above or below processors in a traditional flip chip C4 package with through-silicon vias (TSVs) has significant benefits in reducing data and power transmission paths. However, with the electrical performance benefits come great thermal and mechanical challenges. There are two key objectives for this work. The first is understanding of the die-die interface resistance, R[subscript dd], composed of the back end of line (BEOL) layers and micro-C4 interconnects. The interfacial resistance between BEOL material layers, the impact of TSVs and the impact of strain on R[subscript dd] are subtopics. The second key objective is the understanding of package thermal and mechanical behavior under operating conditions, such as local thermal disturbances. To date, these topics have not been adequately addressed in the literature. It is found that R[subscript dd] can be affected by TSVs, and that the interfacial contributions predicted by theoretical sub-continuum models can be significantly different than measurements. Using validated finite element models, the significance of the power distribution and R[subscript dd] on the temporal responses of 2D vs. 3D packages is highlighted. The results suggest local thermal hotspots can greatly exacerbate the thermal penalty due to the R[subscript dd] and that no peaks in stress arise in the transient period from power on to power off. / text

With the advancement of silicon electronics under threat from physical limits to dimensional scaling, the International Technology Roadmap for Semiconductors (ITRS) released a white paper in 2008, detailing the ways in which the semiconductor industry can keep itself continually growing in the twenty-first century. Two distinct paths were proposed: More-Moore and More-than-Moore. While More-Moore approach focuses on the continued use of state-of-the-art, complementary metal oxide semiconductor (CMOS) technology for next generation electronics, More-than-Moore approach calls for a disruptive change in the system architecture and integration strategies. In this doctoral thesis, we investigate both the approaches to obtain performance improvement in the state-of-the-art, CMOS electronics. We present a novel channel material, SiSn, for fabrication of CMOS circuits. This investigation is in line with the More-Moore approach because we are relying on the established CMOS industry infrastructure to obtain an incremental change in the integrated circuit (IC) performance by replacing silicon channel with SiSn. We report a simple, low-cost and CMOS compatible process for obtaining single crystal SiSn wafers. Tin (Sn) is deposited on silicon wafers in the form of a metallic thin film and annealed to facilitate diffusion into the silicon lattice. This diffusion provides for sufficient SiSn layer at the top surface for fabrication of CMOS devices. We report a lowering of band gap and enhanced mobility for SiSn channel MOSFETs compared to silicon control devices. We also present a process for fabrication of vertically integrated flexible silicon to form 3D integrated circuits. This disruptive change in the state-of-the-art, in line with the More-than-Moore approach, promises to increase the performance per area of a silicon chip. We report a process for stacking and bonding these pieces with polymeric bonding and interconnecting them using copper through silicon vias (TSVs). We report a process for fabricating through polymer vias (TPVs) facilitating the fabrication of sensor arrays and control electronics on the opposite sides of the same flexible polymer. Finally, we present a process to fabricate stretchable metallic thin films with up to 800% stretchability, and report two distinct applications for these devices which cannot be done using current techniques.

Through Silicon Vias (TSVs) are vertical interconnections providing the shortest possible signal paths between vertically stacked chips in 3D packaging. In this thesis, TSVs are fabricated and two novel approaches for the metal filling of TSVs are investigated. A wire bonder is utilized to apply TSV core material in the form of gold stud bumps. The metal filling approaches are carried out by 1) squeezing stud bumps down the TSV holes by utilizing a wafer bonder and 2) stacking stud bumps on the outer periphery of the TSV holes and thereby forcing the material further down. Both approaches have successfully filled TSV holes of varying depths and no voids have been observed. The squeezing approach reaches measured depths of up to 52.9 μm and the stacking approach reaches depths of up to 100 μm.

Afin d’améliorer les performances électriques dans les circuits intégrés en 3D, une large modélisation électromagnétique et une caractérisation haute fréquence sont requises. Cela a pour but de quantifier et prédire les phénomènes de couplage par le substrat qui peuvent survenir dans ces circuits intégrés. Ces couplages sont principalement dus aux nombreuses interconnexions verticales par unité de volume qui traversent le silicium et que l’on nomme « Through Silicon Vias » (TSV).L’objectif de cette thèse est de proposer des règles d’optimisation des performances, à savoir la minimisation des effets de couplage par les substrats en RF. Pour cela, différentes configurations de structures de test utilisées pour analyser le couplage sont caractérisées.Les caractérisations sont effectuées sur un très large spectre de fréquence. Les paramètres d’analyse sont les épaisseurs du substrat, les architectures des vias traversant (diamètres, densités, types de barrières), ainsi que la nature des matériaux utilisés. Des modèles électriques permettant de prédire les phénomènes de couplage sont extraits. Différents outils pour l’analyse de ces effets, sont développés dans notre laboratoire. Parallèlement un important travail de modélisation 3D est mené de façon à confronter mesure et simulation et valider nos résultats. Des stratégies d’optimisation pour réduire ces phénomènes dans les circuits 3D ont été proposées, ce qui a permis de fournir de riches informations aux designers. / In order to improve the electrical performance in 3D integrated circuits, a large electromagnetic modeling and a high frequency characterization are required. This has for goal to quantifiy and predicts the substrate coupling phenomena that can occur in these integrated circuits. These couplings are mainly due to the numerous vertical interconnections existing in a small volume and passing through the silicon, and so called “Through Silicon Vias” (TSV). The objective of this thesis is to propose rules for electrical performance optimization, in order to minimize the coupling effects in RF substrates. For this reason, different test structures configurations used to analyze the coupling are characterized.The characterizations are performed on a very wide frequency spectrum. The analysis parameters are the thicknesses of the substrate, the TSV architectures (diameters, densities, types of barriers), and the nature of the used materials. Electrical models for predicting the coupling phenomena are extracted. Different tools for the analysis of these effects are developed in our laboratory. At the same time, a considerable amount of 3D modeling is conducted to compare measurements with simulations and validate our results. Optimization strategies to reduce coupling phenomena in 3D circuits have been proposed; this has provided a wealth of information to designers.

The main objective of this thesis is to design reliable clock-distribution networks and power-delivery networks for three-dimensional integrated circuits (3D ICs) using through-silicon vias (TSVs). This dissertation supports this goal by addressing six research topics. The first four works focus on 3D clock tree synthesis for low power, pre-bond testability, TSV-induced obstacle avoidance, and TSV utilization. The last two works develop modeling approaches for reliability analysis on 3D power-delivery networks. In the first work, a clock synthesis algorithm is developed for low-power and low-slew 3D clock network design. The impact of various design parameters on clock performance, including the wirelength, clock power, clock slew, and skew, is investigated. These parameters cover the TSV count, TSV parasitics, the maximum loading capacitance of the clock buffers, and the supply voltage. In the second work, a clock synthesis algorithm is developed to construct 3D clock networks for both pre-bond testability and post-bond operability. Pre-bond testing of 3D stacked ICs involves testing each individual die before bonding, which can improve the overall yield of 3D ICs by avoiding stacking defective dies with good ones. Two key techniques including TSV-buffer insertion and redundant tree generation are implemented to minimize clock skew and ensure pre-bond testing. The impact of TSV utilization and TSV parasitics on clock power is also investigated. In the third work, an obstacle-aware clock tree synthesis method is presented for through-silicon-via (TSV)-based 3D ICs. A unique aspect of this problem lies in the fact that various types of TSVs become obstacles during 3D clock routing including signal, power/ground, and clock TSVs. These TSVs may occupy silicon area or routing layers. The generated clock tree does not sacrifice wirelength or clock power too much and avoids TSV-induced obstacles. In the fourth work, a decision-tree-based clock synthesis (DTCS) method is developed for low-power 3D clock network design, where TSVs form a regular 2D array. This TSV array style is shown to be more manufacturable and practical than layouts with TSVs located at irregular spots. The DTCS method explores the entire solution space for the best TSV array utilization in terms of low power. Close-to-optimal solutions can be found for power efficiency with skew minimization in short runtime. In the fifth work, current crowding and its impact on 3D power grid integrity is investigated. Due to the geometry of TSVs and connections to the global power grid, significant current crowding can occur. The current density distribution within a TSV and its connections to the global power grid is explored. A simple TSV model is implemented to obtain current density distributions within a TSV and its local environment. This model is checked for accuracy by comparing with identical models simulated using finite element modeling methods. The simple TSV models are integrated with the global power wires for detailed chip-scale power analysis. In the sixth work, a comprehensive multi-physics modeling approach is developed to analyze electromigration (EM) in TSV-based 3D connections. Since a TSV has regions of high current density, grain boundaries play a significant role in EM dominating atomic transport. The transient analysis is performed on atomic transport including grain and grain boundary structures. The evolution of atomic depletion and accumulation is simulated due to current crowding. And the TSV resistance change is modeled.

Abstract des Vortrages: The reliability-limiting effects in 3D IC structures using TSVs including mechanical stress distributions and the resulting effects on material integrity (e.g. failure modes like interface delamination, cohesive cracking, metallurgical degradation at joints, and chip-package interaction) and finally on device performance degradation are challenges in advanced 3D integration technologies and product development. Managing internal mechanical stress is a key task to ensure high reliability of products manufactured in advanced CMOS technology nodes, and it is a highly ranked concern for 3D TSV technologies. It requires the determination of materials properties, including Young’s modulus, Poisson ratio and coefficient of thermal expansion (CTE), for each material used. For polycrystalline materials, their microstructure has to be considered. In this talk, one reliability-limiting effect, interface delamination and so-called “pop-up” of copper TSV structures will be addressed. Shear stress along the Cu/Si interface and adhesion of the interfaces in a complex stack (Si/liner/barrier/seed/Cu) are parameters that have to be considered. Metal barrier and seed films and the respective surfaces will be discussed in the context of interface strength. Nano X-ray tomography is currently the only analytical technique to study the so-called “pop-up” effect quantitatively, without modifying the region of interest.

Abstract des Vortrages: The reliability-limiting effects in 3D IC structures using TSVs including mechanical stress distributions and the resulting effects on material integrity (e.g. failure modes like interface delamination, cohesive cracking, metallurgical degradation at joints, and chip-package interaction) and finally on device performance degradation are challenges in advanced 3D integration technologies and product development. Managing internal mechanical stress is a key task to ensure high reliability of products manufactured in advanced CMOS technology nodes, and it is a highly ranked concern for 3D TSV technologies. It requires the determination of materials properties, including Young’s modulus, Poisson ratio and coefficient of thermal expansion (CTE), for each material used. For polycrystalline materials, their microstructure has to be considered. In this talk, one reliability-limiting effect, interface delamination and so-called “pop-up” of copper TSV structures will be addressed. Shear stress along the Cu/Si interface and adhesion of the interfaces in a complex stack (Si/liner/barrier/seed/Cu) are parameters that have to be considered. Metal barrier and seed films and the respective surfaces will be discussed in the context of interface strength. Nano X-ray tomography is currently the only analytical technique to study the so-called “pop-up” effect quantitatively, without modifying the region of interest.

Optical connectivity has the potential to outperform copper-based TSVs in terms of bandwidth at the cost of more complexity due to the required electro-optical and opto-electrical conversion. The continuously increasing demand for higher bandwidth pushes the breakeven point for a profitable operation to shorter distances. To integrate an optical communication network in a 3D-chip-stack optical through-silicon vertical VIAs (TSV) are required. While the necessary effort for the electrical/optical and vice versa conversion makes it hard to envision an on-chip optical interconnect, a chip-to-chip optical link appears practicable. In general, the interposer offers the potential advantage to realize electro-optical transceivers on affordable expense by specific, but not necessarily CMOS technology. We investigated the realization and characterization of optical interconnects as a polymer based waveguide in high aspect ratio (HAR) TSVs proved on waferlevel. To guide the optical field inside a TSV as optical-waveguide or fiber, its core has to have a higher refractive index than the surrounding material. Comparing different material / technology options it turned out that thermal grown silicon dioxide (SiO2) is a perfect candidate for the cladding (nSiO2 = 1.4525 at 850 nm). In combination with SiO2 as the adjacent polymer layer, the negative resist SU-8 is very well suited as waveguide material (nSU-8 = 1.56) for the core. Here, we present the fabrication of an optical polymer based multimode waveguide in TSVs proved on waferlevel using SU-8 as core and SiO2 as cladding. The process resulted in a defect-free filling of waveguide TSVs with SU-8 core and SiO2 cladding up to aspect ratio (AR) 20:1 and losses less than 3 dB.