abstract: Time-interleaved analog to digital converters (ADCs) have become critical components in high-speed communication systems. Consumers demands for smaller size, more bandwidth and more features from their communication systems have driven the market to use modern complementary metal-oxide-semiconductor (CMOS) technologies with shorter channel-length transistors and hence a more compact design. Downscaling the supply voltage which is required in submicron technologies benefits digital circuits in terms of power and area. Designing accurate analog circuits, however becomes more challenging due to the less headroom. One way to overcome this problem is to use calibration to compensate for the loss of accuracy in analog circuits. Time-interleaving increases the effective data conversion rate in ADCs while keeping the circuit requirements the same. However, this technique needs special considerations as other design issues associated with using parallel identical channels emerge. The first and the most important is the practical issue of timing mismatch between channels, also called sample-time error, which can directly affect the performance of the ADC. Many techniques have been developed to tackle this issue both in analog and digital domains. Most of these techniques have high complexities especially when the number of channels exceeds 2 and some of them are only valid when input signal is a single tone sinusoidal which limits the application. This dissertation proposes a sample-time error calibration technique which bests the previous techniques in terms of simplicity, and also could be used with arbitrary input signals. A 12-bit 650 MSPS pipeline ADC with 1.5 GHz analog bandwidth for digital beam forming systems is designed in IBM 8HP BiCMOS 130 nm technology. A front-end sample-and-hold amplifier (SHA) was also designed to compare with an SHA-less design in terms of performance, power and area. Simulation results show that the proposed technique is able to improve the SNDR by 20 dB for a mismatch of 50% of the sampling period and up to 29 dB at 37% of the Nyquist frequency. The designed ADC consumes 122 mW in each channel and the clock generation circuit consumes 142 mW. The ADC achieves 68.4 dB SNDR for an input of 61 MHz. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2017

Time Interleaved Analog-to-Digital Converters (TI-ADCs) utilize an architecture which enables conversion rates well beyond the capabilities of a single converter while preserving most or all of the other performance characteristics of the converters on which said architecture is based. Most of the approaches discussed here are independent of architecture; some solutions take advantage of specific architectures. Chapter 1 provides the problem formulation and reviews the errors found in ADCs as well as a brief literature review of available TI-ADC error correction solutions. Chapter 2 presents the methods and materials used in implementation as well as extend the state of the art for post conversion correction. Chapter 3 presents the simulation results of this work and Chapter 4 concludes the work. The contribution of this research is three fold: A new behavioral model was developed in SimulinkTM and MATLABTM to model and test linear and nonlinear mismatch errors emulating the performance data of actual converters. The details of this model are presented as well as the results of cumulant statistical calculations of the mismatch errors which is followed by the detailed explanation and performance evaluation of the extension developed in this research effort. Leading post conversion correction methods are presented and an extension with derivations is presented. It is shown that the data converter subsystem architecture developed is capable of realizing better performance of those currently reported in the literature while having a more efficient implementation.

Analog-to-Digital Converters (ADCs) can be classified into two categories namely Nyquist-rate ADCs and OversampledADCs. Nyquist-rate ADCs can process very high bandwidths while Oversampling ADCs provide high resolution using coarse quantizers and support lower input signal bandwidths. This work describes a Reconfigurable ADC (R-ADC) architecture which models 14 different ADCs utilizing four four-bit flash ADCs and four Reconfigurable Blocks (RBs). Both Nyquist-rate and Oversampled ADCs are included in the reconfiguration scheme. The R-ADC supports first- and second-order Sigma-Delta (ΣΔ) ADCs. Cascaded ΣΔ ADCs which provide high resolution while avoiding the stability issues related to higher order ΣΔ loops are also included. Among the Nyquist-rate ADCs, pipelined and time interleaved ADCs are modeled. A four-bit flash ADC with calibration is used as the basic building block for all ADC configurations. The R-ADC needs to support very high sampling rates (1 GHz to 2 GHz). Hence switched-capacitor (SC) based circuits are used for realizing the loop filters in the ΣΔ ADCs. The pipelined ADCs also utilize an SC based block called Multiplying Digital-to-Analog Converter (MDAC). By analyzing the similarities in structure and function of the loop filter and MDAC, a RB has been designed which can accomplish the function of either block based on the selected configuration. Utilizing the same block for various configurations reduces power and area requirements for the R-ADC. In SC based circuits, the minimum sampling capacitance is limited by the thermal noise that can be tolerated in order to achieve a specific ENOB. The thermal noise in a ΣΔ ADC is subjected to noise shaping. This results in reduced thermal noise levels at the inputs of successive loop filters in cascaded or multi-order ΣΔ ADCs. This property can be used to reduce the sampling capacitance of successive stages in cascaded and multi-order ΣΔ ADCs. In pipelined ADCs, the thermal noise in successive stages are reduced due to the inter-stage gain of the MDAC in each stage. Hence scaling of sampling capacitors can be applied along the pipeline stages. The RB utilizes the scaling of capacitor values afforded by the noise shaping property of ΣΔ loops and the inter-stage gain of stages in pipelined ADCs to reduce the total capacitance requirement for the specified Effective Number Of Bits (ENOB). The critical component of the RB is the operational amplifier (opamp). The speed of operation and ENOB for different configurations are determined by the 3 dB frequency and DC gain of the opamp. In order to find the specifications of the opamp, the errors introduced in ΣΔ and pipelined ADCs by the finite gain and bandwidth of the opamp were modeled in Matlab.The gain and bandwidth requirements for the opamp were derived from the simulation results. Unlike Nyquist-rate ADCs, the ΣΔ ADCs suffer from stability issues when the input exceeds a certain level. The maximum usable input level is determined by the resolution of the quantizer and the order of the loop filter in the ΣΔADC. Using Matlab models, the maximum value of input for different oversampling ADC configurations in the R-ADC were found. The results obtained from simulation are comparable to the theoretical values. The cascaded ADCs require digital filter functions which enable the cancellation of quantization noise from certain stages. These functions were implemented in Matlab. For the R-ADC, these filter functions need to run at very high sampling rates. The ΣΔ loop filter transfer functions were chosen such that their coefficients are powers of two, which would allow them to be implemented as shift and add operations instead of multiplications. The R-ADC configurations were simulated in Matlab. A schematic for the R-ADC was developed in Cadence using ideal switches and a finite gain, single-pole operational transconductance amplifier model. The ADC configuration was selected by four external bits. Performance parameters such as SNR, SNDR and SFDR obtained from simulations in Cadence agree with those from Matlab for all ADC configurations.

<p>Nonuniform sampling occurs in many practical applications either intentionally or unintentionally. This thesis deals with the reconstruction of two-periodic nonuniform signals which is of great importance in two-channel time-interleaved analog-to-digital converters. In a two-channel time-interleaved ADC, aperture delay mismatch between the channels gives rise to a two-periodic nonuniform sampling pattern, resulting in distortion and severely affecting the linearity of the converter. The problem is solved by digitally recovering a uniformly sampled sequence from a two-periodic nonuniformly sampled set. For this purpose, a time-varying FIR filter is employed. If the sampling pattern is known and fixed, this filter can be designed in an optimal way using least-squares or minimax design. When the sampling pattern changes now and then as during the normal operation of time-interleaved ADC, these filters have to be redesigned. This has implications on the implementation cost as general on-line design is cumbersome. To overcome this problem, a novel time-varying FIR filter with polynomial impulse response is developed and characterized in this thesis. The main advantage with these filters is that on-line design is no longer needed. It now suffices to perform only one design before implementation and in the implementation it is enough to adjust only one variable parameter when the sampling pattern changes. Thus the high implementation cost is decreased substantially.</p><p>Filter design and the associated performance metrics have been validated using MATLAB. The design space has been explored to limits imposed by machine precision on matrix inversions. Studies related to finite wordlength effects in practical filter realisations have also been carried out. These formulations can also be extended to the general M - periodic nonuniform sampling case.</p>

Nonuniform sampling occurs in many practical applications either intentionally or unintentionally. This thesis deals with the reconstruction of two-periodic nonuniform signals which is of great importance in two-channel time-interleaved analog-to-digital converters. In a two-channel time-interleaved ADC, aperture delay mismatch between the channels gives rise to a two-periodic nonuniform sampling pattern, resulting in distortion and severely affecting the linearity of the converter. The problem is solved by digitally recovering a uniformly sampled sequence from a two-periodic nonuniformly sampled set. For this purpose, a time-varying FIR filter is employed. If the sampling pattern is known and fixed, this filter can be designed in an optimal way using least-squares or minimax design. When the sampling pattern changes now and then as during the normal operation of time-interleaved ADC, these filters have to be redesigned. This has implications on the implementation cost as general on-line design is cumbersome. To overcome this problem, a novel time-varying FIR filter with polynomial impulse response is developed and characterized in this thesis. The main advantage with these filters is that on-line design is no longer needed. It now suffices to perform only one design before implementation and in the implementation it is enough to adjust only one variable parameter when the sampling pattern changes. Thus the high implementation cost is decreased substantially. Filter design and the associated performance metrics have been validated using MATLAB. The design space has been explored to limits imposed by machine precision on matrix inversions. Studies related to finite wordlength effects in practical filter realisations have also been carried out. These formulations can also be extended to the general M - periodic nonuniform sampling case.

Demand for data communication capacity is rapidly increasing with more and more number of users and higher bandwidth services. As a result, a critical research issue is the implementation of wideband and flexible signal processing in communication and sensing applications. Although software defined radio (SDR) is a possible solution, it may not be practical due to the excessive requirements for analog-to-digital converter (ADCs) and digital filters for wideband signals. In this environment, discrete-time (DT) domain circuits are gaining attention in various architectures such as N-path filters, sampling mixers, and analog FIR/IIR/FFT filters. DT analog signal processing (DT-ASP) ahead of an ADC considerably relaxes the ADC requirements by flexible filtering, offers the potential for higher dynamic range performance, and provides robustness in the presence of digital CMOS scaling. The primary work presented in this dissertation is the design of wideband analog finite impulse response (AFIR) filters. Analog FIR filters have been used as low pass filters for out-of-band rejection in narrow-band applications. However, this work seeks to develop AFIR filters suitable for wideband applications, extending its possible applications. To achieve these performance goals, capacitive digital to analog converters (CDACs) have been introduced for the first time as wideband analog coefficient multipliers, which has led to high linearity analog multiplication with coefficient selection at the DAC resolution. A prototype 4th order DT FIR filter has been implemented in 32nm SOI CMOS technology and has achieved low-pass, band-pass, and high-pass filter (LPF, BPF and HPF) transfer functions corresponding to the programmed coefficient sets with IIP3>11dBm linearity and less than 2 mW/tap of power consumption. The AFIR filter is also utilized to demonstrate a proof-of-concept FIR-based beamforming. The beamforming network consisting of 4 antenna element inputs followed by AFIR filters was implemented with PCB modules with the previously fabricated AFIR filter chip. Behavioral simulations are used to verify the beamforming function with given coefficient sets. Based on the developed AFIR filter modules, FIR-based beamforming was demonstrated with measurement results matching well with the simulations. Further work presented is the design and optimization of multi-section CDAC (MS-CDAC) structures. The proposed MS-CDAC approach provides wide range of options to optimize the tradeoff between kT/C noise, linearity versus switching energy, speed and area. When the optimization approach is applied to a proof-of-concept 10-bit CDAC design, the selected MS-CDAC structure reduces total capacitance and switching energy by 97% and 98%, respectively for given linearity and noise limitations. The proposed MS-CDAC structures are applicable in both DT-ASP coefficient multiplier and SAR-ADC applications. / PHD / In communication systems, filter design is a fundamental task required to recover the signal of interest in the presence of interference. As upcoming communication systems, such as 5th generation (5G) mobile communications and future IEEE 802.11 standards (Wi-Fi), require higher speed and flexibility in signal processing due to the rapidly increasing number of users and data rates, it becomes more challenging to design such filters. In general, analog filters are useful for high-speed, digital filters features flexibility. To take advantage of both aspects, discrete-time (DT) domain filters have become a promising alternative, which can be used to implement digital signal processing functions in the analog domain. This dissertation presents the development of DT analog finite-impulse-response (AFIR) filter design for mixed-signal processing applications. The core idea in this work is to adopt the capacitive DAC (CDAC) as a coefficient multiplier, which enables digital code coefficient multiplication as well as high-speed and high-linearity performance while consuming low power. A prototype 4th order DT FIR filter implemented in 32nm SOI CMOS process is demonstrated with measurements. Based on the developed AFIR filters, proof-of-concept FIR-based beamforming is investigated as well. For this purpose, AFIR filter modules are built on printed-circuit-boards (PCBs) and coefficients are calculated by a simplified method. In addition, this dissertation also includes analysis and optimization of multi-section CDAC (MS-CDAC) structures. Traditional CDAC approaches have a fundamental trade-off between noise and linearity versus size, switching energy and speed. This work explores the characteristics of CDACs depending on the section segmentations and the optimal structure is selected based on the trade-off. Through comprehensive simulations and calculations, the selected structure for 10-bit MS-CDAC achieved 97% and 98% reduced total capacitance and switching energy, respectively.

Les besoins en débit d’information à transmettre ne cessent de croitre. Aussi la généralisation des émetteurs-récepteurs large-bande implique l’intégration de solutions sur une technologie silicium CMOS afin que leur cout soit compatible avec une application grand public. Si l’intégration massive des traitements numériques est facilitée par les dernières technologies CMOS, la fonction de conversion analogique-numérique est quant à elle plus difficile. En effet, afin d’optimiser l’étage frontal analogique, le convertisseur analogique-numérique (CAN) doit répondre à des contraintes très fortes en termes de largeur de bande (de l’ordre du GHz) et de résolution (de 10 à 14bits). Les convertisseurs analogique-numérique basés sur l’entrelacement temporel (CAN-ET) connaissent un essor remarquable car ce sont aujourd’hui les seuls à pouvoir répondre aux deux contraintes énoncées ci-dessus. Cependant, cette structure de CAN reste sensible aux défauts d’appariement entre ses différentes voies de conversion et voit ses performances limitées par la présence de raies parasites liées à des erreurs statiques (offset et gain) et dynamiques (skew et bande passante). Pour réduire l’impact des erreurs dynamiques, nous avons implémenté une calibration mixte en technologie FD-SOI 28nm. Dans une première partie, un état de l’art portant sur les différentes techniques de minimisation et de compensations analogiques des erreurs de skew et bande passante est réalisé. A partir de cette étude, nous proposons différentes techniques analogiques pour compenser les d´esappariements de bande passante et de skew. Pour compenser le skew, nous profitons des avantages de la technologie FD-SOI en modulant fortement la tension de la face arrière d’un ou plusieurs transistor(s) d’ échantillonnage. Concernant l’erreur de bande passante, nous proposons d’ajuster la résistance équivalente du T/H en adaptant la résistance à l’état passant des transistors d’échantillonnage de cinq manières différentes. Pour définir parmi toutes les compensations proposées celle qui est la plus adaptée à nos besoins, nous comparons différents critères de performance. Après avoir identifié la meilleure compensation de skew et de bande passante, nous avons, dans une dernière partie, implémenté une calibration mixte des erreurs statiques et dynamiques o`u l’estimation numérique est basée sur la méthode des Moindres Carrés. / Data transmission requirements are ever more stringent, with respect to more throughput, less power consumption and reduced cost. The cable TV market is where broadband transceivers must continuously innovate to meet these requirements. In these transceivers, the analog front-end part must be adapted to meet the increasingly tighter specifications of the newest standards. A key bottleneck is the Analogto- Digital Converter (ADC), which must reach a sampling rate of several Gigasamples per second at effective conversion resolutions in the range of 10 to 14 bits. Among the possible choices, converters based on Time-Interleaving (TI-ADC) are experiencing remarkable growth, and today they appear to be the best candidates to rmeet the two constraints set out above. However, TI-ADCs are hampered by mismatches between its different conversion channels, which result in degraded performance due to the appearance of mismatch spurs in the frequency domain, arising both from static errors (gain and offset mismatch) and dynamic (skew and bandwidth) errors. To reduce these errors, we have investigated a mixeddomain calibration strategy for TI-ADCS in 28nm FDSOI technology. We strongly focused the analog compensation of dynamic errors. This report begins with a review of the state-of-theart w.r.t. the mismatch reduction and analog compensation techniques for both dynamic errors. Based on these results, we then introduce a variety of analog techniques aimed at compensating the bandwidth and skew mismatches. In order to compensate for the skew, we make the most of the FD-SOI technology by tightly regulating the voltage of the back gate of one or several sampling transistors. For the bandwidth error, we recommend that the T/H equivalent resistor be adjusted, adapting the on-resistor of the sampling transistors using up to five different techniques. Once the most appropriate skew and bandwidth compensations were identified, we ultimately implemented a mixed calibration of static and dynamic errors along with a digital calculation based upon the "Least- Squares" method.

Impulse Ultra Wideband (UWB) communications is an emerging technology that promises a number of benefits over traditional narrowband or broadband signals: extremely high data rates, extremely robust operation in dense multipath environments, low probability of intercept/detection, and the ability to operate concurrently with existing users. Unfortunately, most currently available UWB systems are based on dedicated hardware, preventing researchers from investigating algorithms or architectures that take advantage of some of the unique properties of UWB signals. This dissertation outlines the development of a general purpose software radio transceiver testbed for UWB signals. The testbed is an enabling technology that provides a development platform for investigating ultra wideband communication algorithms (e.g., acquisition, synchronization, modulation, multiple access), ranging or radar (e.g., precision position location, intrusion detection, heart and respiration rate monitoring), and could potentially be used in the area of ultra wideband based medical imaging or vital signs monitoring. As research into impulse ultra wideband expands, the need is greater now than ever for a platform that will allow researchers to collect real-world performance data to corroborate theoretical and simulation results. Additionally, this dissertation outlines the development of the Time-Interleaved Analog to Digital Converter array which served as the core of the testbed, along with a comprehensive theoretical and simulation-based analysis on the effects of Analog to Digital Converter mismatches in a Time-Interleaved Sampling array when the input signal is an ultra wideband Gaussian Monocycle. Included in the discussion is a thorough overview of the implementation of both a scaled-down prototype as well as the final version of the testbed. This dissertation concludes by evaluating the of the transceiver testbed in terms of the narrowband dynamic range, the accuracy with which it can sample and reconstruct a UWB pulse, and the bit error rate performance of the overall system. / Ph. D.

L’ évolution des systèmes radar et de guerre électronique tend à concevoir desrécepteurs numériques possédant des bandes instantanées de plus en plus larges. Cette contraintese reporte sur les Convertisseurs Analogique-Numérique (CAN) qui doivent fournir une fréquenced’échantillonnage de plus en plus élevée tout en conservant une puissance dissipée réduite. Unesolution pour répondre à cette demande est le CAN à Temps Entrelacés (ET-CAN) qui paralléliseM CANs pour augmenter la fréquence d’échantillonnage d’un facteur M tout en restant dansun rapport proportionné avec la puissance dissipée. Cependant, les performances dynamiquesdes ET-CANs sont réduites par des défauts d’entrelacements liés à des différences de processusde fabrication, de leur tension d’alimentation et des variations de température. Ces défautspeuvent être modélisés comme issus des disparités d’offsets, de gains ou décalages temporels etglobalement comme issus des disparités de réponses fréquentielles. Ce sont sur ces dernièresdisparités, moins traitées dans la littérature, que portent nos travaux. L’objectif est d’étudierces disparités pour en déduire un modèle et une méthode d’estimation puis, de proposer desméthodes de compensation numérique qui peuvent être implémentées sur une cible FPGA.Pour cela, nous proposons un modèle général des disparités de réponses fréquentielles desET-CANs pour un nombre de voies M quelconques. Celui-ci mélange une description continuedes disparités et une description discrète de l’entrelacement, résultant sur une expression desdéfauts des ET-CANs comme un filtrage à temps variant périodique (LPTV) du signal analogiqueéchantillonné uniformément. Puis, nous proposons une méthode d’estimation des disparitésdes ET-CANs basée sur les propriétés de corrélation du signal en sortie du modèle, pour Mvoies quelconques. Ensuite, nous définissions une architecture de compensation des disparitésde réponses fréquentielles des ET-CANs et nous étudions ses performances en fonction de sesconfigurations et du signal en entrée. Nous décrivons une implémentation de cette architecturepour M=4 voies entrelacées sur cible FPGA et nous étudions les ressources consommées afin deproposer des pistes d’optimisation. Enfin, nous proposons une seconde méthode de compensationspécifique au cas M=2 voies entrelacées, dérivée de la première mais travaillant sur le signalanalytique en sortie d’un ET-CAN et nous la comparons à une méthode similaire de l’état del’art. / The evolution of radar and electronic warfare systems tends to develop digitalreceivers with wider bandwidths. This constraint reaches the Analog to Digital Converters(ADC) which must provide a sample rate higher and higher while maintaining a reducedpower dissipation. A solution to meet this demand is the Time-Interleaved ADC (TIADC)which parallelizes M ADCs, increasing the sampling frequency of an M factor while still ina proportionate relation to the power loss. However, the dynamic performance of TIADCsare reduced by errors related to the mismatches between the sampling channels, due to themanufacturing processes, the supply voltage and the temperature variations. These errors canbe modeled as the result of offset, gain and clock-skew mismatches and globally as from thefrequency response mismatches. It is these last mismatches, unless addressed in the literaturethat carry our work. The objective is to study these errors to derive a model and an estimationmethod then, to propose digital compensation methods that can be implemented on a FPGAtarget.First, we propose a general TIADC model using frequency response mismatches for any Mchannel number. Our model merge a continuous-time description of mismatches and a discretetimeone of the interleaving process, resulting in an expression of the TIADC errors as a linearperiodic time-varying (LPTV) system applied to the uniformly sampled analog signal. Then,we propose a method to estimate TIADC errors based on the correlation properties of theoutput signal for any M channel. Next, we define a frequency response mismatch compensationarchitecture for TIADC errors and we study its performance related to its configuration and theinput signal. We describe an FPGA implementation of this architecture for M=4 interleavedchannels and we study the resources consumption to propose optimisations. Finally, we proposea second compensation method, specific to M=2 interleaved channels and derived from the firstone, but working on the analytical signal from the TIADC output and we compare it to a similarstate-of-the-art method.