Low voltage, low power amplifiers are proposed. One of the operational amplifiers is an Operational Transconductance Amplifier (OTA) with wide input and output swing and constant gm. The second and third amplifiers are high-performance Current Operational amplifiers (COAs). All amplifiers have power supply as low as one threshold voltage plus two overdrive voltage. In this thesis, the supply voltage is 1V. Simulation results show that the OTA has the maximum linear range over 0.7V. The transconductance can be 147£gA/V, the power consumption is 0.133mW. There are two designs of the COA. Simulation results show COA(1) with a current gain of 143. The input impedance is 110£[, the output impedance is 240K£[ and the power consumption is 0.15mW. In the simulation results of the COA(2), the current gain is 110. The DC power dissipation is 0.07mW. The input and output impedance are 95£[ and 500K£[, respectively. All the proposed amplifiers are implemented on a TSMC 0.35£gm 2p4m CMOS process technology and analyzed using HSPICE.

Les transistors à haute mobilité électronique à base de GaN (HEMTs) constituent une filière prometteuse pour l’amplification de puissance dans la gamme des fréquences micro-ondes et des applications dans le domaine millimétrique. Les propriétés physiques exceptionnelles du GaN, sont à l’origine de performances attrayantes obtenues avec les dispositifs à base de GaN, comparées aux autres technologies III-V, en termes de densité de puissance jusqu’à 94GHz pour des applications en télécommunications ou militaires.Cette thèse traite de la fabrication et de la caractérisation des transistors HEMTs AlGaN/GaN sur substrat de silicium (111) avec une fine épaisseur de barrière d’AlGaN et des longueurs de grilles très courtes. Des transistors à grilles décentrées ont été ainsi fabriqués et optimisés en réduisant l’espacement grille-source. Par conséquent, une amélioration significative de la transconductance et des fréquences de coupure FT et FMAX a été obtenue. De plus, un maximum de transconductance de 435 mS/mm avec une bonne qualité de pincement pour une longueur de grille de 110 nm a été démontré. D’autre part, des transistors HEMTs à grille double chapeaux ont été fabriqués. De bons résultats en termes de fréquence de coupure FMAX=206GHz et FT=100GHz ont été obtenus sur des HEMTs ayant une longueur de grille de 90nm et une distance source-grille de 0.25µm. Le maximum de transconductance associé est de 440mS/mm. Ces résultats attrayants obtenus montrent clairement que la technologie des transistors HEMTs GaN sur substrat silicium est une voie viable et prometteuse pour la réalisation de dispositifs à bas coût dans le domaine millimétrique. / GaN-based High-Electron Mobility Transistors (HEMTs) have emerged as one of the best candidates for solid-state power amplification in the microwave and millimeter-wave ranges. Compared with other III-V semiconductors, the outstanding physical properties of Gallium Nitride, make GaN-based devices suitable in terms of microwave power density up to 94GHz for telecommunication or military applications. This work reports on the fabrication and the characterization of AlGaN/GaN HEMTs on silicon (111) substrate with a thin barrier layer and a short gate length. Devices with non-centered gate were fabricated and optimized by reducing gate-source spacing. Consequently, significant improvement of the transconductance and cut-off frequencies FT and FMAX were achieved. Furthermore, a maximum extrinsic transconductance of 435mS/mm was obtained associated with a good channel pinch-off for 110 nm gate length HEMT devices. Moreover, devices with a record maximum oscillation cutoff frequency were fabricated. These transistors are based on a double-T-shaped gate associated with an optimized technology to enable high efficiency 2DEG control while mitigating the parasitic resistances. Good results of FMAX = 206GHz and FT =100GHz are obtained for 90nm gate-length HEMTs with 0.25µm source-to-gate spacing. The associated maximum transconductance value is as high as 440mS/mm. These high performances obtained on AlGaN/GaN HEMTs on silicon substrate are clearly showing that high-resistive silicon substrate associated with a thin AlGaN barrier layer provide an attractive alternative for the fabrication of low-cost millimeter-wave devices.

Cette thèse, effectuée au LPA par Julien Chaste, présente l'analyse dynamique d'un transistor à effet de champ en nanotube de carbone (NT-FET) dans la perspective de mesurer sa résolution de charge δqrms.<br />La quantification des électrons dans le nanotube joue un rôle sur la limitation de la conductance, de la transconductance gm, de la capacité de grille Cg et en particulier sur la limitation de la fréquence de coupure ωt=gm/Cg par l'inductance cinétique du canal.<br />Les deux montages expérimentaux, l'un à 300K et l'autre à 4K, ainsi que la fabrication des NT-FET ont intégré des solutions efficaces au problème de désadaptation d'impédance et ont permis de mesurer la transmission entre 0,1 et 1,6GHz ainsi que gm,Cg et ωt. Des fréquences ωt =50GHz ont même été mesurées.<br />De plus, la coloration du bruit (0,2-0,8GHz) du transistor à 4K a été déterminée. Le bruit mesuré en mode ouvert est d'origine poissonienne (F=1) et montre des effets de saturation dues aux phonons optiques.<br />L'ensemble de ce travail a prouvé que la résolution de charge δqrms du NT-FET est suffisante pour détecter des charges uniques en une nanoseconde

<p>The geometry of CMOS processes has decreased in a steady pace over the years at the same time as the complexity has increased. Even if there are more requirements on the designer today, the main goal is still the same: to minimize the occupied area and power dissipation. This thesis investigates if a prediction of the costs in future CMOS processes can be made. By implementing several processes on a test circuit we can see a pattern in area and power dissipation when we change to smaller processes.</p><p>This is done by optimizing a two-stage operational transconductance amplifier on basis of a given specification. A circuit optimization tool evaluates the performance measures and costs. The optimization results from the area and power dissipation is used to present a diagram that shows the decreasing costs with smaller processes and also a prediction of how small the costs will be for future processes. This thesis also presents different optimization tools and a design hexagon that can be used when we struggle with optimization trade-offs.</p>

Integrated high-Q continuous-time filters require adaptive tuning circuits that will correct the filter parameters such as center frequency and quality factor (Q). Three different automatic tuning techniques are introduced. In all of the proposed methods, frequencyand quality factor tuning loops are controlled digitally, providing stable tuning by activating only one loop at a given time. In addition, a direct relationship between passband gain and quality factor is not required, so the techniques can be applied to active LC filters as well as Gm-C filters. The digital-tuning method based on phase comparison was verified with 1% tuning accuracy at 5.5 MHz for Q of 20. It uses phase information for both Q and center-frequency tuning. The filter output phase is tuned to the known references, which are generated by a frequency synthesizer. The core tuning circuit consists of D flip-flops (DFF) and simple logic gates. DFFs are utilized to perform binary phase comparisons. The second method, high-order digital tuning based on phase comparison, is an extension of the previous technique to high-order analog filters without depending on the master-slave approach. Direct tuning of the overall filter response is achieved without separating individual biquad sections, eliminating switches and their parasitics. The tuning system was verified with a prototype 6th order bandpass filter at 19 MHz with 0.6 MHz bandwidth, which was fabricated in a conventional 0.5 [mu]m CMOS technology. Analysis of different practical limitations is also provided. Finally, the digital-tuning method based on magnitude comparison is proposed for second-order filters for higher frequency operations. It incorporates a frequency synthesizer to generate reference signals, an envelope detector and a switched comparator to compare output magnitudes at three reference frequencies. The theoretical analysis of the technique and the simulation results are provided.

High linearity transmitters and receivers should be used to efficiently utilize the available channel bandwidth. Power consumption is also a critical factor that determines the battery life of portable devices and wireless sensors. Three base-band and RF building blocks are designed with the focus of high linearity and low power consumption. An architectural attenuation-predistortion linearization scheme for a wide range of operational transconductance amplifiers (OTAs) is proposed and demonstrated with a transconductance-capacitor (Gm-C) filter. The linearization technique utilizes two matched OTAs to cancel output harmonics, creating a robust architecture. Compensation for process variations and frequency-dependent distortion based on Volterra series analysis is achieved by employing a delay equalization scheme with on-chip programmable resistors. The distortion-cancellation technique enables an IM3 improvement of up to 22dB compared to a commensurate OTA without linearization. A proof-of-concept lowpass filter with the linearized OTAs has a measured IM3 < -70dB and 54.5dB dynamic range over its 195MHz bandwidth. Design methodology for high efficiency class D power amplifier is presented. The high efficiency is achieved by using higher current harmonic to achieve zero voltage switching (ZVS) in class D power amplifier. The matching network is used as a part of the output filter to remove the high order harmonics. Optimum values for passive circuit elements and transistor sizes have been derived in order to achieve the highest possible efficiency. The proposed power amplifier achieves efficiency close to 60 percent at 400 MHz for -2dBm of output power. High efficiency class A power amplifier using dynamic biasing technique is presented. The power consumption of the power amplifier changes dynamically according to the output signal level. Effect of dynamic bias on class A power amplifier linearity is analyzed and the results were verified using simulations. The linearity of the dynamically biased amplifier is improved by adjusting the preamplifier gain to guarantee constant overall gain for different input signal levels.

Integrated high-Q continuous-time filters require adaptive tuning circuits that will correct the filter parameters such as center frequency and quality factor (Q). Three different automatic tuning techniques are introduced. In all of the proposed methods, frequencyand quality factor tuning loops are controlled digitally, providing stable tuning by activating only one loop at a given time. In addition, a direct relationship between passband gain and quality factor is not required, so the techniques can be applied to active LC filters as well as Gm-C filters. The digital-tuning method based on phase comparison was verified with 1% tuning accuracy at 5.5 MHz for Q of 20. It uses phase information for both Q and center-frequency tuning. The filter output phase is tuned to the known references, which are generated by a frequency synthesizer. The core tuning circuit consists of D flip-flops (DFF) and simple logic gates. DFFs are utilized to perform binary phase comparisons. The second method, high-order digital tuning based on phase comparison, is an extension of the previous technique to high-order analog filters without depending on the master-slave approach. Direct tuning of the overall filter response is achieved without separating individual biquad sections, eliminating switches and their parasitics. The tuning system was verified with a prototype 6th order bandpass filter at 19 MHz with 0.6 MHz bandwidth, which was fabricated in a conventional 0.5 [mu]m CMOS technology. Analysis of different practical limitations is also provided. Finally, the digital-tuning method based on magnitude comparison is proposed for second-order filters for higher frequency operations. It incorporates a frequency synthesizer to generate reference signals, an envelope detector and a switched comparator to compare output magnitudes at three reference frequencies. The theoretical analysis of the technique and the simulation results are provided.

In this thesis, we use the no-capacitor feed-forward (NCFF) compensation scheme which employs a feed-forward path to obtain high gain, high frequency. We use CMFB circuit to adjust the common-mode output voltages and the bias circuit. The CMFB circuit makes the output accurately to the reference voltage. The circuit was designed and fabricated TSMC 0.35 £gm CMOS process. The dc gain is around 90dB and the cut-off frequency is 1GHz. The supply voltage is ¡Ó1.25V. The output voltage is smaller than 10mV.

Thesis (M.S.)--Auburn University, 2008. / Abstract. Vita. Includes bibliographical references (p. 45-46).

This work deals with methods used in design of low voltage operational amplifiers. It describes some of the most commonly used methods. Properties of these methods are verified by computer simulation of operational transconductance amplifiers that are utilizing them.