Translinear circuits are circuits in which the exponential relationship between the output current and input voltage of a circuit element is exploited to realize various algebraic or differential equations. This thesis is concerned with a subclass of translinear circuits, in which the basic translinear element, called a multiple-input translinear element (MITE), has an output current that is exponentially related to a weighted sum of its input voltages. MITE networks can be used for the implementation of the same class of functions as traditional translinear circuits. The implementation of algebraic or (algebraic) differential equations using MITEs can be reduced to the implementation of the product-of-power-law (POPL) relationships, in which an output is given by the product of inputs raised to different powers. Hence, the synthesis of POPL relationships, and their optimization with respect to the relevant cost functions, is very important in the theory of MITE networks. In this thesis, different constraints on the topology of POPL networks that result in desirable system behavior are explored and different methods of synthesis, subject to these constraints, are developed. The constraints are usually conditions on certain matrices of the network, which characterize the weights in the relevant MITEs. Some of these constraints are related to the uniqueness of the operating point of the network and the stability of the network. Conditions that satisfy these constraints are developed in this work. The cost functions to be minimized are the number of MITEs and the number of input gates in each MITE. A complete solution to POPL network synthesis is presented here that minimizes the number of MITEs first and then minimizes the number of input gates to each MITE. A procedure for synthesizing POPL relationships optimally when the number of gates is minimal, i.e., 2, has also been developed here for the single--output case. A MITE structure that produces the maximum number of functions with minimal reconfigurability is developed for use in MITE field--programmable analog arrays. The extension of these constraints to the synthesis of linear filters is also explored, the constraint here being that the filter network should have a unique operating point in the presence of nonidealities. Synthesis examples presented here include nonlinear functions like the arctangent and the gaussian function which find application in analog implementations of particle filters. Synthesis of dynamical systems is presented here using the examples of a Lorenz system and a sinusoidal oscillator. The procedures developed here provide a structured way to automate the synthesis of nonlinear algebraic functions and differential equations using MITEs.

In this thesis, a first order low pass square root domain filter (SRD filter) based on the novel operational transconductor amplifiers (OTAs) is presented. The SRD filter consists of a translinear filter and two OTAs. Because the conventional OTA has small input voltage swings, which violates the large signal operation of a SRD filter. We propose the novel OTA which is based on the large signal behaviors of MOSFETs, and the OTA also has large signal operation. We improve Cruz¡¦s SRD filter [22], reduce the number of the transconductors from 3 to 2, and replace Class-AB linear transconductors with the proposed OTAs. The MOSFET count of whole circuit can be reduced. Therefore, the OTAs have many advantages: wider input voltage swing, low supply voltage, low power consumption, and small chip area. The circuit has been fabricated with 0.35£gm CMOS technology. It operates with a supply voltage 1.5V and the bias current varies from 0.3£gA to 15£gA. Measurement results show that the cutoff frequency can be tuned from 1.1kHz to 35.2kHz when the external capacitance C is 1nF and the cutoff frequency can be tuned from 8.7kHz to 310.4kHz when the external capacitance C is 100pF. The total harmonic distortions are 0.93% and 0.91% when the external capacitances C are 1nF and 100pF, and the power consumption is 152.29£gW.

With the introduction of the floating-gate transistor into reconfigurable architectures, great advances have been made in the field. Recently, Hall et. al. have proposed the first truly large-scale field programmable analog array (FPAA). As an outgrowth of this work, a new class of FPAAs based on translinear elements has begun to be developed. The use of translinear elements, multiple input translinear elements (MITEs) specifically, allows for extreme versatility in the functions implemented by the system while keeping the computational elements of the FPAA regular. In addition, synthesis procedures have been developed for translinear elements. This facilitates the implementation of large-scale systems on the FPAA because the circuit design can be extracted using the synthesis procedures based on equations entered by the user. Two architectures are proposed for the new FPAA. The first architecture uses fine grain reconfigurability, every gate capacitor and the drain of each MITE can be connected arbitrarily, in order to create reconfigurable MITE networks. Circuits including a squaring circuit, a square root circuit, a translinear loop, a vector magnitude circuit, and a 1st-order log-domain filter were implemented using this architecture and results are presented. In addition, examples are shown to illustrate the compilation of the circuits onto the FPAA. The second proposed architecture uses a mix of fine and medium granularity in order to simplify the implementation of larger systems. Examples are given and again the compilation of the circuits onto the FPAA is shown.

No description available.

While the development of reconfigurable analog platforms is a blossoming field, the tradeoff between usability and flexibility continues to be a major barrier. Field Programmable Analog Arrays (FPAAs) built with translinear elements offer a promising solution to this problem. These FPAAs can be built to use previously developed synthesis procedures for translinear circuits. Furthermore, large-scale translinear FPAAs can be built using floating-gate transistors as both the computational elements and the reconfigurable interconnect network. Two FPAAs, built using Multiple Input Translinear Elements (MITEs), have been designed, fabricated, and tested. These devices have been programmed to implement various circuits including multipliers, squaring circuits, current splitters, and filters. In addition, synthesis, place-and-route, and programming tools have been created in order to implement a reconfigurable system where the circuits implemented are described only by equations. Supporting circuitry for interfacing with current-mode, translinear FPAAs has also been developed. This circuitry included a voltage-to-current converter, a current-to-voltage converter, and a pipelined analog-to-digital converter. The continued development of translinear FPAAs will lead to a reconfigurable analog system that allows for a large portion of the design to be abstracted away from the user.

Η ενσωμάτωση των κωδίκων Turbo σε ένα ευρύ φάσμα εφαρμογών λόγω της εκπληκτικής αποδόσεώς τους που προσεγγίζει το θεμελιώδες όριο του Shannon, απαιτεί αποδοτικές αρχιτεκτονικές και υλοποιήσεις υψηλού ρυθμού διεκπεραίωσης και χαμηλής κατανάλωσης ενέργειας όσον αφορά την εξαιρετικά πολύπλοκη και χρονοβόρα επαναληπτική αποκωδικοποίησή τους. Η παρούσα διδακτορική διατριβή μελετά την χρήση της τεχνολογίας Πυριτίου-Γερμανίου (SiGe) BiCMOS σε αναλογικές αρχιτεκτονικές για την υλοποίηση αποκωδικοποιητών Turbo υψηλού ρυθμού διεκπεραίωσης και όσο το δυνατόν χαμηλής κατανάλωσης ισχύος. Η σχεδίαση βάσει των διπολικών τρανζίστορ ετεροεπαφής προσδίδει ιδιαίτερα υψηλή ταχύτητα στην απόκριση του αναλογικού συστήματος σε αντίθεση με τα συμβατικά διπολικά τρανζίστορ ή με τα τρανζίστορ πεδίου MOS, τα οποία λειτουργούν στην περιοχή υποκατωφλίου για τη διατήρηση της διαγραμμικής αρχής. Στα πλαίσια της διατριβής αυτής παρουσιάζεται μια γενική μεθοδολογία χρησιμοποιώντας τους γράφους παραγόντων για την προδιαγραφή συστημάτων ελέγχου λαθών. Έπειτα, πραγματοποιείται η σύζευξη της επιτευχθείσας προδιαγραφής με την κυκλωματική συμπεριφορά των τοπολογιών λαμβάνοντας υπ’ όψιν φυσικά τα χαρακτηριστικά της τεχνολογίας SiGe BiCMOS και καταλήγουμε στην αποδοτική σχεδίαση και ολοκλήρωση αποκωδικοποιητών διόρθωσης λαθών υψηλής ταχύτητας. Χρήσιμα συμπεράσματα, για την υιοθέτηση της προτεινόμενης μεθοδολογίας και τη χρήση της τεχνολογίας Πυριτίου-Γερμανίου, αναφέρονται με την παρουσίαση της πρώτης επιτυχούς υλοποίησης σε τεχνολογία 0.35μm AMS SiGe BiCMOS ενός αναλογικού Trellis αποκωδικοποιητή και των εξομοιωτικών αποτελεσμάτων του αντίστοιχου αποκωδικοποιητή Turbo, ο οποίος ενσωματώνει τον παραπάνω Trellis αποκωδικοποιητή. / The incorporation of Turbo codes into a wide range of applications due to their amazing performance close to the fundamental Shannon limit, demands efficient architectures and implementations of high-throughput and low energy consumption in the case of the extremely complex and time consuming procedure of iterative decoding. The present dissertation studies the use of SiGe BiCMOS technology in analog architectures for the implementation of high-throughput and moderate power consumption Turbo decoders. The design is based on Heterojunction Bipolar Transistors and leads to a significant increment of the analog system’s speed in contrast to the designs based on conventional bipolar transistors or MOS transistor, which operate in the subthreshold region in order to conform to the translinear principle. A generic methodology, using factor-graphs for the specification procedure of error control systems, is also presented. Furthermore, we map the derived specification onto the appropriate acircuit topology taking into account the characteristics of the SiGe BiCMOS technology. Finally, the methodology leads to an efficient design and consistent integration of high-speed analog decoders. We report useful conclusions for the adoption of the proposed methodology, and the use of Silicon-Germanium technology by presenting the first successful implementation of an analog Trellis decoder, and the simulation results of the relevant Turbo decoder in a 0.35μm AMS SiGe BiCMOS technology.