With the advancement of biomedical instrumentation technologies sensor based remote healthcare monitoring system is gaining more attention day by day. In this system wearable and implantable sensors are placed outside or inside of the human body. Certain sensors are needed to be placed inside the human body to acquire the information on the vital physiological phenomena such as glucose, lactate, pH, oxygen, etc. These implantable sensors have associated circuits for sensor signal processing and data transmission. Powering the circuit is always a crucial design issue. Batteries cannot be used in implantable sensors which can come in contact with the blood resulting in serious health risks. An alternate approach is to supply power wirelessly for tether-less and battery- less operation of the circuits.Inductive power transfer is the most common method of wireless power transfer to the implantable sensors. For good inductive coupling, the inductors should have high inductance and high quality factor. But the physical dimensions of the implanted inductors cannot be large due to a number of biomedical constraints. Therefore, there is a need for small sized and high inductance, high quality factor inductors for implantable sensor applications. In this work, design of a multi-spiral solenoidal printed circuit board (PCB) inductor for biomedical application is presented. The targeted frequency for power transfer is 13.56 MHz which is within the license-free industrial, scientific and medical (ISM) band. A figure of merit based optimization technique has been utilized to optimize the PCB inductors. Similar principal is applied to design on-chip inductor which could be a potential solution for further miniaturization of the implantable system. For layered human tissue the optimum frequency of power transfer is 1 GHz for smaller coil size. For this reason, design and optimization of multi-spiral solenoidal integrated inductors for 1 GHz frequency is proposed. Finally, it is demonstrated that the proposed inductors exhibit a better overall performance in comparison with the conventional inductors for biomedical applications.

The 2006 International Technology Roadmap for Semiconductors projects that for 2020, interconnects will be as narrow as 14 nm and will operate at frequencies as high as 50GHz. For a wire that operates at ultra-high frequencies, such that skin depth and the mean free path of the electrons are in the same order, skin effect and surface scattering should be considered simultaneously. This is known as the anomalous skin effect (ASE). The objective of this work is to identify the challenges and opportunities for using GSI interconnects in the nanometer and GHz regime. The increase in the resistivity of a thin wire caused by the ASE is studied. The delay of a digital transmission line resulting from this effect is modeled. Compact models are presented for the bit-rate limit of transmission lines using a general form of resistance that for the first time simultaneously considers dc resistance, skin effect, and surface scattering. A conventional low-loss approximation that is only valid for fast rising signals is also relaxed. The impact of size effects on the design of multi-level interconnect networks is studied. For high-performance chips at the 18 nm technology node, it is shown that despite a more than four times increase in the resistivity of copper for minimum-size interconnects, the increase in the number of metal levels is negligible (less than 7%), and interconnects that will be affected most are so short that their impact on chip performance is inconsequential. It is shown that for low-cost applications where very few wiring pitches are normally used, the number of metal levels needed to compensate for the impact of size effects on the average rc delay of a copper interconnect is drastically high. An optimization methodology has been presented for power distribution interconnects at the local level. For a given IR drop budget, compact models are presented for the optimal widths of power and ground lines in the first two metal levels for which the total metal area used for power distribution is minimized.

Zugl.: Dortmund, Techn. Univ., Diss., 2008

Αντικείμενο της παρούσας διπλωματικής εργασίας είναι η παρουσίαση και η μελέτη ενος εναλλακτικού σχεδιασμού του deblocking φίλτρου του προτύπου κωδικοποίησης βίντεο Η.264. Αρχικά επεξηγείται αναλυτικά ο τρόπος λειτουργίας του φίλτρου και στη συνέχεια προτείνεται ένας πρωτοποριακός σχεδιασμός με χρήση pipeline πέντε σταδίων. Ο σχεδιασμός παρουσιάζει σημαντικά πλεονεκτήματα στον τομέα της ταχύτητας (ενδεικτικά εμφανίζεται βελτιωμένη απόδοση στην συχνότητα λειτουργίας και στο throughput). Αυτό πιστοποιήθηκε από μετρήσεις που έγιναν σε συγκεκριμένα fpga και επαλήθευσαν τα θεωρητικά συμπεράσματα που είχαν εξαχθεί. / The standard H.264 (or else MPEG-4 part 10) is nowadays the most widely used standard in the area of video coding as it is supported by the largest enterprises in the internet (including Google, Apple and Youtube). Its most important advantage over the previous standards is that it achieves better bitrate without falling in terms of quality. A crucial part of the standard is the deblocking filter which is applied in each macroblock of a frame so that it reduces the blocking distortion. The filter accounts for about one third of the computational requirements of the standard, something which makes it a really important part of the filtering process. The current diploma thesis presents an alternative design of the filter which achieves better performance than the existing ones. The design is based in the use of two filters (instead of one used in current technology) and moreover, in the application of a pipelined design in each filter. By using a double filter, exploitation of the independence which exists in many parts of the macroblock is achieved. That is to say, it is feasible that different parts of it can be filtered at the same time without facing any problems. Furthermore, the use of the pipeline technique importantly increases the throughput. Needless to say, in order for the desired result to be achieved, the design has to be made really carefully so that the restrictions imposed by the standard will not be failed. The use of this alternative filter design will result in an important raise in the performance. Amongst all, the operating frequency, the throughput and the quality of the produced video will all appear to be considerably risen. It also needs to be mentioned that the inevitable increase of the area used (because of the fact that two filters are used instead of one) is not really important in terms of cost. The structure of the thesis is described in this paragraph. In chapter 1 there is a rather synoptic description of the H.264 standard and the exact position of the deblocking filter in the whole design is clarified. After that, the algorithmic description of the filter follows (Chapter 2). In this chapter, all the parameters participating in the filter are presented in full detail as well as the equations used during the process. In the next chapter (chapter 3), the architecture chosen for the design is presented. That is to say, the block diagram is presented and explained, as well as the table of timings which explains completely how the filter works. The pipelining technique applied in the filter is also analyzed and justified in this chapter. In the next chapter (chapter 4), every structural unit used in the current architecture is analyzed completely and its role in the whole structure is presented. Finally, in chapter 5, the results of the measurements made in typical fpgas of Altera and Xilinx are presented. The results are shown in table format whereas for specific parameters diagrams were used so that the improved performance of the current design compared to the older ones that are widely used, becomes evident.

Submitted by Johnny Rodrigues (johnnyrodrigues@ufcg.edu.br) on 2018-08-13T20:41:07Z No. of bitstreams: 1 LUIZ BRUNELLI - TESE PPGEE 2005..pdf: 3761170 bytes, checksum: e05b83824a2a7e6d3aca6ea19daf1396 (MD5) / Made available in DSpace on 2018-08-13T20:41:07Z (GMT). No. of bitstreams: 1 LUIZ BRUNELLI - TESE PPGEE 2005..pdf: 3761170 bytes, checksum: e05b83824a2a7e6d3aca6ea19daf1396 (MD5) Previous issue date: 2005-02 / CNPq / Nesta tese descreve-se uma nova solução para o tratamento da complexidade das interconexões entre os elementos de processamento das redes neuronais artificiais (RNAs). Ela possibilita implementar RNAs em hardware, de tecnologia digital, com um número maior de neurônios do que se faz atualmente. As RNAs têm sido usadas como solução em vários problemas complexos. Em alguns destes problemas faz-se necesário a sua implementação em hardware. Vários s˜ao os compromissos que devem ser satisfeitos durante o projeto e implementa¸c˜ao das RNAs, dentre eles o das interconexões entre os neurônios. Atualmente encontram-se implementações neuronais utilizando circuitos integrados especificamente desenvolvidos para uma dada arquitetura de rede neuronal e também o uso de circuitos integrados configurados pelo usuário. Dentre estes circuitos existem os FPGAs reconfigur´aveis dinamicamente (DR-FPGAs) que podem ter suas características alteradas durante a sua opera¸c˜ao, sem sofrer interrupções em seu funcionamento normal. Estes dispositivos têm sido utilizados na implementação de RNAs. Propõe-se uma solução para o problema das interconexões entre os neurônios artificiais utilizando os DR-FPGAs e uma nova forma de computação: as Figuras de Execução (F.E.). As F.E. permitem teoricamente reduzir o impacto das interconexões através da eliminação do transporte de dados via barramento, além de outras vantagens e desvantagens durante o processamento da computação. As F.E. não parecem estar restritas apenas as aplicações de RNAs. Elas podem ser utilizadas pela computação reconfigurável em problemas massivamente paralelos e/ou que necessitem trocar informações entre os vários elementos de processamento do sistema. / In this thesis a new solution for the treatment of the complexity in the interconnections among the processing elements of the artificial neural networks (ANNs) is described. It enables realize ANNs digital hardware implementation with a larger number of neurons than does nowadays. The ANNs have been used as a solution in various complex problems. Some of these problems require hardware implementation. A lot of constraints must be satisfied during the project flow of the implementations of ANNs, such as the neural interconnections. Nowadays, neural implementations are done using integrated circuits, specifically developed for a given neural network architecture or integrated circuits configured by the user. Among these circuits exist the dynamically reconfigured FPGAs (DR-FPGAs) which can have their characteristics changed during operation without suffering interruptions in their execution. These devices have been usedforANNimplementations. Itpresentsaproposaltosolvethe interconnection problem for artificial neurons using DR-FPGAs in a new computational way: the Execution Patterns1 (EPs). The EPs allow, theoretically, to reduce the influence of interconnections through the removal of data transport via busses, besides other advantages and disadvantages. TheEPsdoesnotseemtoberestrictedonlytoANNapplications. They can be used by reconfigurable computation in massive parallel problems and/or problems that demand information exchange among the various elements in a processing system.

Bancos de dados biológicos utilizados para comparação e alinhamento local de sequências tem crescido de forma exponencial. Isso popularizou programas que realizam buscas nesses bancos. As implementações dos algoritmos de alinhamento de sequências Smith- Waterman e distância Levenshtein demonstraram ser computacionalmente intensivas e, portanto, propícias para aceleração em hardware. Este trabalho descreve arquiteturas em hardware dedicado prototipadas para FPGA e ASIC para acelerar os algoritmos Smith- Waterman e distância Levenshtein mantendo os mesmos resultados obtidos por softwares. Descrevemos uma nova e eficiente unidade de processamento para o cálculo do Smith- Waterman utilizando affine gap. Também projetamos uma arquitetura que permite particionar as sequências de entrada para a distância Levenshtein em um array sistólico de tamanho fixo. Nossa implementação em FPGA para o Smith-Waterman acelera de 275 a 494 vezes o algoritmo em relação a um computador com processador de propósito geral. Ainda é 52 a 113% mais rápida em relação, segundo nosso conhecimento, as mais rápidas arquiteturas recentemente publicadas. / Bioinformatics databases used for sequence comparison and local sequence alignment are growing exponentially. This has popularized programs that carry out database searches. Current implementations of sequence alignment methods based on Smith- Waterman and Levenshtein distance have proven to be computationally intensive and, hence, amenable for hardware acceleration. This Msc. Thesis describes an FPGA and ASIC based hardware implementation designed to accelerate the Smith-Waterman and Levenshtein distance maintaining the same results yielded by general softwares. We describe an new efficient Smith-Waterman affine gap process element and a new architecture to partitioning and maping the Levenshtein distance into fixed size systolic arrays. Our FPGA Smith-Waterman implementation delivers 275 to 494-fold speed-up over a standard desktop computer and is also about 52 to 113% faster, to the best of our knowledge, than the fastest implementation in a most recent family of accelerators.

La prédiction de l'organisation topologique du plan de masse d'un circuit VLSI complexe est très importante pour sa conception. Cette thèse présente une étude sur les proprietés statistiques des dessins des masques des principaux blocs constituant un circuit intégré. Un outil prototype d'évaluation topologique est également présenté. Cet outil donne une évaluation de la forme et de la taille de ces blocs, à partir de leurs spécifications fonetionelles. Il est composé par un ensemble de sousprogrammes d'évaluation spécialisés pour les différents types de blocs fonetionnels qui peuvent constituer un circuit VLSI. / The prediction of the floor plan topological organization in the design process of a complex VLSI circuit is very important. This thesis presents a study about statistical properties of the main blocks that compose an integrated circuit. A prototype tool for topological evaluation is also presented. This tool provides an evaluation of the shape and size of these blocks from their functional specifications. It is composed of a set of evaluation rotines specialized for the different functional blocks which may constitute a VLSI circuit.

La prédiction de l'organisation topologique du plan de masse d'un circuit VLSI complexe est très importante pour sa conception. Cette thèse présente une étude sur les proprietés statistiques des dessins des masques des principaux blocs constituant un circuit intégré. Un outil prototype d'évaluation topologique est également présenté. Cet outil donne une évaluation de la forme et de la taille de ces blocs, à partir de leurs spécifications fonetionelles. Il est composé par un ensemble de sousprogrammes d'évaluation spécialisés pour les différents types de blocs fonetionnels qui peuvent constituer un circuit VLSI. / The prediction of the floor plan topological organization in the design process of a complex VLSI circuit is very important. This thesis presents a study about statistical properties of the main blocks that compose an integrated circuit. A prototype tool for topological evaluation is also presented. This tool provides an evaluation of the shape and size of these blocks from their functional specifications. It is composed of a set of evaluation rotines specialized for the different functional blocks which may constitute a VLSI circuit.

Bancos de dados biológicos utilizados para comparação e alinhamento local de sequências tem crescido de forma exponencial. Isso popularizou programas que realizam buscas nesses bancos. As implementações dos algoritmos de alinhamento de sequências Smith- Waterman e distância Levenshtein demonstraram ser computacionalmente intensivas e, portanto, propícias para aceleração em hardware. Este trabalho descreve arquiteturas em hardware dedicado prototipadas para FPGA e ASIC para acelerar os algoritmos Smith- Waterman e distância Levenshtein mantendo os mesmos resultados obtidos por softwares. Descrevemos uma nova e eficiente unidade de processamento para o cálculo do Smith- Waterman utilizando affine gap. Também projetamos uma arquitetura que permite particionar as sequências de entrada para a distância Levenshtein em um array sistólico de tamanho fixo. Nossa implementação em FPGA para o Smith-Waterman acelera de 275 a 494 vezes o algoritmo em relação a um computador com processador de propósito geral. Ainda é 52 a 113% mais rápida em relação, segundo nosso conhecimento, as mais rápidas arquiteturas recentemente publicadas. / Bioinformatics databases used for sequence comparison and local sequence alignment are growing exponentially. This has popularized programs that carry out database searches. Current implementations of sequence alignment methods based on Smith- Waterman and Levenshtein distance have proven to be computationally intensive and, hence, amenable for hardware acceleration. This Msc. Thesis describes an FPGA and ASIC based hardware implementation designed to accelerate the Smith-Waterman and Levenshtein distance maintaining the same results yielded by general softwares. We describe an new efficient Smith-Waterman affine gap process element and a new architecture to partitioning and maping the Levenshtein distance into fixed size systolic arrays. Our FPGA Smith-Waterman implementation delivers 275 to 494-fold speed-up over a standard desktop computer and is also about 52 to 113% faster, to the best of our knowledge, than the fastest implementation in a most recent family of accelerators.

Bancos de dados biológicos utilizados para comparação e alinhamento local de sequências tem crescido de forma exponencial. Isso popularizou programas que realizam buscas nesses bancos. As implementações dos algoritmos de alinhamento de sequências Smith- Waterman e distância Levenshtein demonstraram ser computacionalmente intensivas e, portanto, propícias para aceleração em hardware. Este trabalho descreve arquiteturas em hardware dedicado prototipadas para FPGA e ASIC para acelerar os algoritmos Smith- Waterman e distância Levenshtein mantendo os mesmos resultados obtidos por softwares. Descrevemos uma nova e eficiente unidade de processamento para o cálculo do Smith- Waterman utilizando affine gap. Também projetamos uma arquitetura que permite particionar as sequências de entrada para a distância Levenshtein em um array sistólico de tamanho fixo. Nossa implementação em FPGA para o Smith-Waterman acelera de 275 a 494 vezes o algoritmo em relação a um computador com processador de propósito geral. Ainda é 52 a 113% mais rápida em relação, segundo nosso conhecimento, as mais rápidas arquiteturas recentemente publicadas. / Bioinformatics databases used for sequence comparison and local sequence alignment are growing exponentially. This has popularized programs that carry out database searches. Current implementations of sequence alignment methods based on Smith- Waterman and Levenshtein distance have proven to be computationally intensive and, hence, amenable for hardware acceleration. This Msc. Thesis describes an FPGA and ASIC based hardware implementation designed to accelerate the Smith-Waterman and Levenshtein distance maintaining the same results yielded by general softwares. We describe an new efficient Smith-Waterman affine gap process element and a new architecture to partitioning and maping the Levenshtein distance into fixed size systolic arrays. Our FPGA Smith-Waterman implementation delivers 275 to 494-fold speed-up over a standard desktop computer and is also about 52 to 113% faster, to the best of our knowledge, than the fastest implementation in a most recent family of accelerators.