La prédiction de l'organisation topologique du plan de masse d'un circuit VLSI complexe est très importante pour sa conception. Cette thèse présente une étude sur les proprietés statistiques des dessins des masques des principaux blocs constituant un circuit intégré. Un outil prototype d'évaluation topologique est également présenté. Cet outil donne une évaluation de la forme et de la taille de ces blocs, à partir de leurs spécifications fonetionelles. Il est composé par un ensemble de sousprogrammes d'évaluation spécialisés pour les différents types de blocs fonetionnels qui peuvent constituer un circuit VLSI. / The prediction of the floor plan topological organization in the design process of a complex VLSI circuit is very important. This thesis presents a study about statistical properties of the main blocks that compose an integrated circuit. A prototype tool for topological evaluation is also presented. This tool provides an evaluation of the shape and size of these blocks from their functional specifications. It is composed of a set of evaluation rotines specialized for the different functional blocks which may constitute a VLSI circuit.

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The objective of the research presented in this thesis is to investigate alternative ways of information processing employing asynchronous, data driven, and analogue computation in massively parallel cellular processor arrays, with applications in machine vision and artificial intelligence. The use of cellular processor architectures, with only local neighbourhood connectivity, is considered in VLSI realisations of the trigger-wave propagation in binary image processing, and in Bayesian inference. Design issues, critical in terms of the computational precision and system performance, are extensively analysed, accounting for the non-ideal operation of MOS devices caused by the second order effects, noise and parameter mismatch. In particular, CMOS hardware solutions for two specific tasks: binary image skeletonization and sum-product algorithm for belief propagation in factor graphs, are considered, targeting efficient design in terms of the processing speed, power, area, and computational precision. The major contributions of this research are in the area of continuous-time and discrete-time CMOS circuit design, with applications in moderate precision analogue and asynchronous computation, accounting for parameter variability. Various analogue and digital circuit realisations, operating in the continuous-time and discrete-time domains, are analysed in theory and verified using combined Matlab-Hspice simulations, providing a versatile framework suitable for custom specific analyses, verification and optimisation of the designed systems. Novel solutions, exhibiting reduced impact of parameter variability on the circuit operation, are presented and applied in the designs of the arithmetic circuits for matrix-vector operations and in the data driven asynchronous processor arrays for binary image processing. Several mismatch optimisation techniques are demonstrated, based on the use of switched-current approach in the design of current-mode Gilbert multiplier circuit, novel biasing scheme in the design of tunable delay gates, and averaging technique applied to the analogue continuous-time circuits realisations of Bayesian networks. The most promising circuit solutions were implemented on the PPATC test chip, fabricated in a standard 90 nm CMOS process, and verified in experiments.

The power side-channel attack, which allows an attacker to derive secret information from power traces, continues to be a major vulnerability in many critical systems. Numerous countermeasures have been proposed since its discovery as a serious vulnerability, including both hardware and software implementations. Each countermeasure has its own drawback, with some of the highly effective countermeasures incurring large overhead in area and power. In addition, many countermeasures are quite invasive to the design process, requiring modification of the design and therefore additional validation and testing to ensure its accuracy. Less invasive countermeasures that do not require directly modifying the system do exist but often offer less protection. This thesis analyzes two non-invasive countermeasures and examines ways to maximize the protection offered by them while incurring the least amount of overhead. These two countermeasures are called clock phase noise (CPN) and voltage noise (VN), and are placed on the same FPGA as an AES encryption module that we are trying to protect. We test these designs against a highly effective algorithm called correlation power analysis (CPA) and a preprocessing technique called the sliding window attack (SW). We found that the combined effects of the two countermeasures was greater than the impact of either countermeasure when used independently, and published a paper in the 2019 IEEE 30th International Conference on Application-specific Systems, Architectures and Processors (ASAP) on our findings. We found that our best combined countermeasure protected about 76% of the maximum amount of traces that a well-known but invasive competitor, wave dynamic differential logic (WDDL), could with only about 41% of the area and 78% of the power. However, the sliding window attack significantly reduced the amount of protection our combined countermeasure could offer to only 11% of that offered by WDDL. Since then, we updated our methodology and made some adjustments to VN and CPN. Our CPN countermeasure greatly improved, and therefore so did our combined countermeasure, which on average protected up to about 90% of the maximum amount of traces that WDDL could with only about 43% of the area and about 60% of the power. This is remarkable because these results are after the sliding window attack, meaning that our post-proposal countermeasures protect almost as well as WDDL while requiring only about half of the resources.

A stability checker is a clocked storage element, much like a flip-flop, which detects unstable and late signals in the pipeline of a digital system. The On-line stability checker operates concurrently with its associated circuit-under-test (CUT). This thesis describes the full custom very-large-scale integration (VLSI) design and testing process of On-Line Stability Checkers. The goals of this thesis are to construct and test Stability Checker designs, and to create a design template for future class projects in the EE 431 Computer-Aided Design (CAD) of VLSI Devices course at Cal Poly. A method for concurrent fault testing called On-line Stability Checking was introduced by Franco and McCluskey [10] to detect reliability failures. Reliability failures initially manifest themselves as delay faults and transient glitching, which become progressively larger over time due to the wearout of conducting metal lines, eventually leading to functional faults. Stability checkers periodically detect reliability failures by monitoring CUT output signals for unstable and late input signals over a time period after the sampling clock edge. The checkers are tested by applying variable delayed input test patterns to emulate reliability failures. Consequently, configurable delay chains were incorporated into the system to provide variable delays on the input signal lines. The system also includes external test signal ports. Circuit and layout designs were implemented in the Electric VLSI Design tool [12] and simulated with LTSPICE [13]. Electric provides Design Rule Checking (DRC) and Layout-versus-Schematic (LVS) utilities for verification. Each module was designed in a bottom-up, hierarchical cell-based approach. Functional simulation, DRC and LVS checks were performed at every subsequent higher cell layer in the design hierarchy. The final chip layout was taped out for fabrication on November 29, 2010 and finished parts were received on July 7, 2011 after two manufacturing delays. Finished packaged parts were successfully verified for functionality based on SPICE simulations. The stability checkers were tested for flip-flop operation, glitch detection and late signal arrival detection. Configurable delay chains were tested to determine delay resolution and uniformity. Actual delay resolution and range measurements show a 3 to 4 times difference compared to simulated values. The Electric design template created from this project includes basic CMOS logic gates with uniform standard cell heights. The template contains a 40-pin pad ring cell along with the individual pad ring components. EE 431 students would be able to create custom chips that are compatible for fabrication via the MOSIS MEP service. In future work, the template design library can be expanded to include more logic gate variants of various inputs and drive strengths as well as more complex functional modules.

This Master's thesis deals with functional safety of electronic systems. Specifically, it focuses on self-testing of the microprocessor and its peripherals at the software level. The main aim of the thesis is to design and implement a set of functions written in programming language C or assembly language, which automatically test the selected areas of the microcontroller. Resources and methods used in the implemented solution also aim to meet the requirements according to the safety standard IEC 60730-1, Annex H, Software Class B. The microcontroller NXP LPC55S69 was chosen as a hardware platform. It consists of two ARM Cortex-M33 cores. As a result, the example application is provided, which uses implemented test functions at the run-time. Example application also contains a graphical user interface with fault injection ability.

Parametric acoustic arrays are ultrasonic-based loudspeakers that produce highly directive audio. The audio must first be preprocessed and modulated into an ultrasonic carrier before being emitted into the air, where it will self-demodulate in the far field. The resulting audio wave is proportional to the double time-derivative of the square of the modulation envelope. This thesis presents a fully analog processor which encodes the audio into two Pulse Width Modulated (PWM) signals in quadrature phase and sums them together to produce a Single Sideband (SSB) spectrum around the fundamental frequency of the PWM signals. The two signals are modulated between 8% and 24% duty cycle to maintain a quasi-linear relationship between the duty cycle and the output signal level. This also allows the signals to sum without overlapping each other, maintaining a two-level output. The system drives a network of narrowband transducers with a center frequency equal to the PWM fundamental. Because the transducers are voltage driven, they have a bandpass frequency response which behaves as a first-order integrator on the SSB signal, eliminating the need for two integrators in the processor. Results show that the “SSB-PWM” output wave has a consistent 20-30dB difference in magnitude between the upper sideband and lower sideband. In simulation, a single tone test shows higher total harmonic distortion for lower frequencies and higher modulation depth. A two-tone test creates a 2nd order intermodulation term that increases with the frequencies of the input signals.

It was previously shown that the BRESENHAM algorithm is well-suited for digital fractional clock generation. Specifically, it proved to be the optimal approximation of a desired clock in terms of the switching edges provided by an available reference clock. Moreover, some synthesis results for hardwired dividers on Altera FPGAs showed that this technique for clock division achieves a high performance often at or close to the maximum frequency supported by the devices for moderate bit widths of up to 16 bits. This paper extends the investigations on the clock division by the BRESENHAM algorithm. It draws out the limits encountered by the existing implementation for both FPGA and VLSI realizations. A rather unconventional adoption of the carry-save representation combined with a soft-threshold comparison is proposed to circumvent these limitations. The resulting design is described and evaluated. Mathematically appealing results on the quality of the approximation achieved by this approach are presented. The underlying proofs and technical details are provided in the appendix.

With the scaling of technology nodes, modern CMOS integrated circuits face severe fundamental challenges that stem from device scaling limitations, interconnection bottlenecks and increasing manufacturing complexities. These challenges drive researchers to look for revolutionary technologies beyond the end of CMOS roadmap. Towards this end, a new nanoscale 3-D computing fabric for future integrated circuits, Skybridge, has been proposed [1]. In this new fabric, core aspects from device to circuit style, connectivity, thermal management and manufacturing pathway are co-architected in a 3-D fabric-centric manner. However, the Skybridge fabric uses only n-type transistors in a dynamic circuit style for logic and memory implementations. Therefore, it requires complicated clocking schemes to overcome signal monotonicity associated with cascading dynamic logic gates. For Skybridge’s large-scale circuits, the dynamic circuit style requires cascaded stages to be micro-pipelined, which results in large number of buffers used for storing minterms causing significant overhead in terms of area and power. Moreover, implementation of logic is limited to NAND or AND-of-NAND based logic expressions, which does not always result in compact circuits. In this work, we propose an extension of original Skybridge fabric, called NP-Dynamic-Skybridge, to solve these challenges by using both n-and p-type transistors in an innovative circuit style. Here, every stage in a given circuit is implemented by either n-type or p-type dynamic logic. Cascading n- and p-type dynamic logic effectively avoids signal monotonicity problem, and allows combinational-like circuit implementation. This helps to simplify the clocking scheme for cascaded logics requiring only one set of global precharge and evaluate clock signals. And also it expands the degree of expressing logic enabling expressions such as NOR, OR-of-NORs, in addition to those previously mentioned. Furthermore, the number of pipeline stages is significantly reduced for a given logic function, and buffer requirements are less compared with Skybridge 3D fabric thus improving on area and power metrics. Initial evaluation for NP-Dynamic-Skybridge’s 4-bit carry look-ahead adder shows up to 2x density benefits over Skybridge 3-D fabric and at least 17% power/throughput benefit.

Hardware implementations of artificial neural networks (ANNs) have become feasible due to the advent of persistent 2-terminal devices such as memristor, phase change memory, MTJs, etc. Hybrid memristor crossbar/CMOS systems have been studied extensively and demonstrated experimentally. In these circuits, memristors located at each cross point in a crossbar are, however, stacked on top of CMOS circuits using back end of line processing (BOEL), limiting scaling. Each neuron’s functionality is spread across layers of CMOS and memristor crossbar and thus cannot support the required connectivity to implement large-scale multi-layered ANNs. This work proposes a new fine-grained 3D integrated circuit technology for ANNs that is one of the first IC technologies for this purpose. Synaptic weights implemented with devices are incorporated in a uniform vertical nanowire template co-locating the memory and computation requirements of ANNs within each neuron. Novel 3D routing features are used for interconnections in all three dimensions between the devices enabling high connectivity without the need for special pins or metal vias. To demonstrate the proof of concept of this fabric, classification of binary images using a perceptron-based feed forward neural network is shown. Bottom-up evaluations for the proposed fabric considering 3D implementation of fabric components reveal up to 19x density, 1.2x power benefits when compared to 16nm hybrid memristor/CMOS technology.