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Les principaux résultats de recherche présentés dans cette thèse de Doctorat concernent la proposition de nouvelles méthodologies de spécifications et de dimensionnement ainsi que des techniques de mise en œuvre de structures de filtrage et de conception d'architectures matérielles reconfigurables pour la sélection numérique des canaux radio dans un contexte de réception multistandard. Les résultats obtenus à l'issue de cette thèse constituent une contribution à un nouvel axe de recherche qui vise à développer de nouvelles technologies pour des équipements radio flexibles, multi-service, multi-standards, multi-bandes, re-configurables mais tout en limitant la complexité de traitement et d'implantation matérielle en vue de réduire d'avantage l'encombrement des équipements portables ainsi que leur consommation d'énergie. Notre première étape d'étude a concerné la définition de structure et de méthode de dimensionnement d'un récepteur radio à conversion directe doté de fonctionnalités large bande et multi-bande. Une méthode a aussi été établie pour déterminer les spécifications des étages de sélection des canaux en tenant compte de la structure de filtrage en cascade, des profils des signaux et interférents radio ainsi que des effets de repliement de spectre. Les résultats de synthèse sur FPGA ont permis de mettre en évidence les performances en terme de qualité de filtrage et d'optimisation des ressources d'implantation matérielle.

Any system in the world constitutes particles like electrons. To analyze the behaviors of these systems the behavior of these particles must be predicted. The ground state energy of a molecule is the most important information about a molecule and can calculate by solving the Schrodinger equation. But as the number of atoms increase, the number of variable (coordinates of the atom) that the equation represent increases by three times. Due to the large state space and the nonlinear nature of the Schrodinger equation, it is very difficult to solver this equation. Quantum Monte Carlo (QMC) is a very efficient method to solve the Schrodinger equation for accurate results. This methods uses random numbers to sample the complex equation and get very accurate results. Due to the large data involved in this method, it exhibits rich amount of data parallelism. Variational path integral (VPI) simulations are a class of QMC methods that permit direct computation of expectation values of coordinate-space observables for the nodeless ground states of many-body quantum systems. High degree of data parallelism involved in this method facilitates the use of Graphical Processing Units (GPUs), a powerful type of processor well known to computer gamers. In comparison to the other parallel systems, like CPU clusters, GPU hardware can be much faster and is significantly cheaper. The goal of this thesis is to implement the VPI simulation algorithm on GPU to compute the coordinate-space observables of a Neon cluster.

This thesis presents the low power design of a 916MHz Gilbert cell mixer and a Class-A power amplifier for the Bioluminescent Bioreporter Integrated Circuit (BBIC) transmitter. There has been increased use in the man-made sensors which can operate in environments unsuitable for humans and at locations remote from the observer. One such sensor is the bioluminescent bioreporter integrated circuit (BBIC). Bioluminescent bioreporters are the bacteria that are genetically engineered in order to achieve bioluminescence when in contact with the target substance. The BBIC has bioreporters placed on a single CMOS integrated circuit (IC) that detects the bioluminescence, performs the signal processing and finally transmits the senor data. The wireless transmission allows for remote sensing by eliminating the need of costly cabling to communicate with the sensor. The wireless data transmission is performed by the transmitter system. The digital data stream generated by the signal processing circuitry of the BBIC is ASK modulated for transmission. The direct conversion transmitter used in this design includes a PLL, Mixer and a Power amplifier. The PLL is used to generate a 916MHz frequency signal. This signal is mixed with the digital data signal generated from the signal processing circuitry of the BBIC. A double balanced Gilbert cell is used to perform the mixing operation. The mixer output is applied to a power amplifier which provides amplification of the RF output power. The Gilbert cell mixer and the power amplifier have been implemented in 90nm CMOS process available through MOSIS.

A pulse-width locked loop (PWLL) circuit is reported that compensates for process, voltage, and temperature (PVT) variations of a linear ramp generator within a 12-bit multi-channel Wilkinson (single-slope integrating) Analog-to-Digital (ADC). This PWLL was designed and fabricated in a 0.5-um Silicon Germanium (SiGe) BiCMOS process. The PWLL architecture that is comprised of a phase detector, a charge-pump, and a pulse width modulator (PWM), is discussed along with the design details of the primary blocks. Simulation and silicon measurement data are shown that demonstrate a large improvement in the accuracy of the PVT-compensated ADC over the uncompensated ADC.

As VLSI technology moves into the Ultra-Deep Sub-Micron (UDSM) era, manufacturing variations, power supply noise and temperature variations greatly affect the performance and yield of VLSI circuits. Clock Distribution Network (CDN), which is one of the biggest and most important nets in any synchronous VLSI chip, is especially sensitive to these variations. To address this problem variability-aware analysis and optimization techniques for VLSI circuits are needed. In the first part of this thesis an analytical bound for the unwanted skew due to interconnect variation is established. Experimental results show that this bound is safer, tighter and computationally faster than existing approaches. This bound could be used in variation-aware clock tree synthesis.The second part of the thesis deals with optimizing a given clock tree to minimize the unwanted skew variations. Non-tree CDNs have been recognized as a promising approach to overcome the variation problem. We propose a novel non-tree CDN obtained by adding cross links in an existing clock tree. We analyze the effect of the link insertion on clock skew variability and propose link insertion schemes. The non-tree CDNs so obtained are shown to be highly tolerant to skew variability with very little increase in total wire-length. This can be used in applications such as ASIC design where a significant increase in the total wire-length is unacceptable.

As VLSI technology enters the nanoscale regime, a great amount of efforts have been made to reduce interconnect delay. Among them, buffer insertion stands out as an effective technique for timing optimization. A dramatic rise in on-chip buffer density has been witnessed. For example, in two recent IBM ASIC designs, 25% gates are buffers. In this thesis, three buffer insertion algorithms are presented for the procedure of performance and power optimization. The second chapter focuses on improving circuit performance under inductance effect. The new algorithm works under the dynamic programming framework and runs in provably linear time for multiple buffer types due to two novel techniques: restrictive cost bucketing and efficient delay update. The experimental results demonstrate that our linear time algorithm consistently outperforms all known RLC buffering algorithms in terms of both solution quality and runtime. That is, the new algorithm uses fewer buffers, runs in shorter time and the buffered tree has better timing. The third chapter presents a method to guarantee a high fidelity signal transmission in global bus. It proposes a new redundant via insertion technique to reduce via variation and signal distortion in twisted differential line. In addition, a new buffer insertion technique is proposed to synchronize the transmitted signals, thus further improving the effectiveness of the twisted differential line. Experimental results demonstrate a 6GHz signal can be transmitted with high fidelity using the new approaches. In contrast, only a 100MHz signal can be reliably transmitted using a single-end bus with power/ground shielding. Compared to conventional twisted differential line structure, our new techniques can reduce the magnitude of noise by 45% as witnessed in our simulation. The fourth chapter proposes a buffer insertion and gate sizing algorithm for million plus gates. The algorithm takes a combinational circuit as input instead of individual nets and greatly reduces the buffer and gate cost of the entire circuit. The algorithm has two main features: 1) A circuit partition technique based on the criticality of the primary inputs, which provides the scalability for the algorithm, and 2) A linear programming formulation of non-linear delay versus cost tradeoff, which formulates the simultaneous buffer insertion and gate sizing into linear programming problem. Experimental results on ISCAS85 circuits show that even without the circuit partition technique, the new algorithm achieves 17X speedup compared with path based algorithm. In the meantime, the new algorithm saves 16.0% buffer cost, 4.9% gate cost, 5.8% total cost and results in less circuit delay.