This work optimizes a CMOS image pixel sensor circuit for being used in a compressive sensing (CS) image sensor. The CS image sensor sums neighbor pixel outputs and hence reduces analog to digital conversions. Efforts are also made to improve the circuit that performs such pixel summation. With the optimized design, a CMOS image sensor circuit with a compression ratio of 4 is designed using a 130 nm CMOS technology from Global foundries. The design pixel sensor has a 256X256 pixel array. Simulation shows that the developed image sensors can achieve peak signal to noise ratio (PSNR) of 28 dB and 37.8 dB for benchmark images Cameraman and Lenna, respectively.

Recent advances in wireless sensor nodes, data acquisition devices, wearable and implantable medical devices have paved way for low power (sub 50uW) devices. These devices generally use small solid state or thin film batteries for power supply which need replacement or need to be removed for charging. RF energy harvesting technology can be used to charge these batteries without the need to remove the battery from the device, thus providing a sustainable power supply. In other cases, a battery can become unnecessary altogether. This enables us to deploy wireless network nodes in places where regular physical access to the nodes is difficult or cumbersome. This thesis proposes a design of an RF energy harvesting device able to charge commercially available thin film or solid-state batteries. The energy harvesting amplifier circuit is designed in Global Foundry 0.13um CMOS technology using Cadence integrated circuit design tools. This Application Specific Integrated Circuit (ASIC) is intended to have as small a footprint as possible so that it can be easily integrated with the above-mentioned devices. While a dedicated RF power source is a direct solution to provide sustainable power to the harvesting circuit, harvesting ambient RF power from TV and UHF cellular frequencies increases the possibilities of where the harvesting device can be placed. The biggest challenge for RF energy harvesting technology is the availability of adequate amount of RF power. This thesis also presents a survey of available RF power at various ultra-high frequencies in San Luis Obispo, CA.The idea is to determine the frequency band which can provide maximum RF power for harvesting and design a harvester for that frequency band.

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Reproduction de : Thèse de docteur-ingénieur : informatique : Grenoble, INPG : 1985. / Titre provenant de l'écran-titre.

This thesis presents a novel biomimetic cochlea filter which closely resembles the biological cochlea behaviour. The filter is highly feasible for analogue very-large-scale integration (VLSI) circuits, which leads to a micro-watt-power and millimetre-sized hardware implementation. By virtue of such features, the presented filter contributes to a solid foundation for future biologically-inspired audio signal processors. Unlike existing works, the presented filter is developed by taking direct inspirations from the physiologically measured results of the biological cochlea. Since the biological cochlea has prominently different characteristics of frequency response from low to high frequencies, the biomimetic cochlea filter is built by cascading three sub-filters accordingly: a 2nd-order bandpass filter for the constant gentle low-frequency response, a 2nd-order tunable low-pass filter for the variable and selective centre frequency response and a 5th-order elliptic filter for the ultra-steep roll-off at stop-band. As a proof of concept, a biomimetic cochlea filter bank is built to process audio signals, which demonstrates the highly discriminative spectral decomposition and high-resolution time-frequency analysis capabilities similar to the biological cochlea. The filter has simple representation in the Laplace domain which leads to a convenient analogue circuit realisation. A floating-active-inductor circuit cell is developed to build the corresponding RLC ladder for each of the three sub-filters. The circuits are designed based on complementary metal-oxide-semiconductor (CMOS) transistors for VLSI implementation. Non-ideal factors of CMOS transistors including parasitics, noise and mismatches are extensively analysed and consciously considered in the circuit design. An analogue VLSI chip is successfully fabricated using 0.35μ m CMOS process. The chip measurements demonstrate that the centre frequency response of the filter has about 20 dB wide gain tuning range and a high quality factor reaching maximally over 19. The filter has a 20 dB/decade constant gentle low-frequency tail and an over 300 dB/decade sharp stop-band roll-off slope. The measured results agree with the filter model expectations and are comparable with the biological cochlea characteristics. Each filter channel consumes as low as 59.5 ~90μ Wpower and occupies only 0.9 mm2 area. Besides, the biomimetic cochlea filter chip is characterised from a wide range of angles and the experimental results cover not only the auditory filter specifications but also the integrated circuit design considerations. Furthermore, following the progressive development of the acoustic resonator based on microelectro- mechanical systems (MEMS) technology, a MEMS-CMOS implementation of the proposed filter becomes possible in the future. A key challenge for such implementation is the low sensing capacitance of the MEMS resonator which suffers significantly from sensitivity degradation due to the parasitic capacitance. A novel MEMS capacitive interface circuit chip is additionally developed to solve this issue. As shown in the chip results, the interface circuit is able to cancel the parasitic capacitance and increase the sensitivity of capacitive sensors by 35 dB without consuming any extra power. Besides, the chopper-stabilisation technique is employed which effectively reduces the circuit flicker noise and offsets. Due to these features, the interface circuit chip is capable of converting a 7.5 fF capacitance change of a 1-Volt-biased 0.5 pF capacitive sensor pair into a 0.745 V signal-conditioned output while consuming only 165.2μ W power.

International Telemetering Conference Proceedings / October 30-November 02, 1995 / Riviera Hotel, Las Vegas, Nevada / NASA’s use of high bandwidth packetized Consultative Committee for Space Data Systems (CCSDS) telemetry in future missions presents a great challenge to ground data system developers. These missions, including the Earth Observing System (EOS), call for high data rate interfaces and small packet sizes. Because each packet requires a similar amount of protocol processing, high data rates and small packet sizes dramatically increase the real-time workload on ground packet processing systems. NASA’s Goddard Space Flight Center has been developing packet processing subsystems for more than twelve years. Implementations of these subsystems have ranged from mini-computers to single-card VLSI multiprocessor subsystems. The latter subsystem, known as the VLSI Packet Processor, was first deployed in 1991 for use in support of the Solar Anomalous & Magnetospheric Particle Explorer (SAMPEX) mission. An upgraded version of this VMEBus card, first deployed for Space Station flight hardware verification, has demonstrated sustained throughput of up to 50 Megabits per second and 15,000 packets per second. Future space missions including EOS will require significantly higher data and packet rate performance. A new approach to packet processing is under development that will not only increase performance levels by at least a factor of six but also reduce subsystem replication costs by a factor of five. This paper will discuss the development of a next generation packet processing subsystem and the architectural changes necessary to achieve a thirty-fold improvement in the performance/price of real-time packet processing.

International Telemetering Conference Proceedings / October 30-November 02, 1995 / Riviera Hotel, Las Vegas, Nevada / The remote sensing industry is experiencing an unprecedented rush of activity to deploy commercial and scientific satellites. NASA and its international partners are leading the scientific charge with The Earth Observation System (EOS) and the International Space Station Alpha (ISSA). Additionally, there are at least ten countries promoting scientific/commercial remote sensing satellite programs. Within the United States, commercial initiatives are being under taken by a number of companies including Computer Technology Associates, Inc., EarthWatch, Inc., Space Imaging, Inc., Orbital Imaging Corporation and TRW, Inc. This activity is due to factors including: technological advances which have lead to significant reductions in the costs to build and deploy satellites; an awareness of the importance of understanding human impact on the ecosystem; and a desire to collect and sell data some believe will be worth $1.5 billion (USD) per year within five years. The success and usefulness of these initiatives, both scientific and commercial, depends largely on the ease and cost of providing remotely sensed data to value added resellers and end-users. A number of these spacecraft will provide an interface directly to users. To provide these data to the largest possible user base, ground station equipment must be affordable and the data must be distributed in a timely manner (meaning seconds or minutes, not days) over commercial network and communications equipment. TSI TelSys, Inc. is developing ground station equipment that will perform both traditional telemetry processing and the bridging and routing functions required to seamlessly interface commercial local- and wide-area networks and satellite communication networks. These products are based on Very Large Scale Integration (VLSI) components and pipelined, multi-processing architectures. This paper describes TelSys’ product family and its envisioned use within a ground station.

International Telemetering Conference Proceedings / October 27-30, 1997 / Riviera Hotel and Convention Center, Las Vegas, Nevada / The international space community, including National Aeronautics and Space Administration (NASA), European Space Agency (ESA), Japanese National Space Agency (NASDA) and others, are committed to using the Consultative Committee for Space Data Systems (CCSDS) recommendations for low earth orbiting satellites. With the advent of the CCSDS standards and the availability of direct broadcast data from a number of current and future spacecraft, a large number of users could have access to earth science data. However, to allow for the largest possible user base, the cost of processing this data must be as low as possible. By utilizing Very Large Scale Integration (VLSI) Application-Specific Integrated Circuits (ASIC), pipelined data processing, and advanced software development technology and tools, highly integrated CCSDS data processing can be attained in a single desktop system. This paper describes a prototype desktop system based on the Peripheral Component Interconnect (PCI) bus that performs CCSDS standard frame synchronization, bit transition density decoding, Cyclical Redundancy Check (CRC) error checking, Reed-Solomon decoding, data unit sorting, packet extraction, annotation and other CCSDS service processing. Also discussed is software technology used to increase the flexibility and usability of the desktop system. The reproduction cost for the system described is less than 1/8th the current cost of commercially available CCSDS data processing systems.

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No description available.