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Minimizing and exploiting leakage in VLSIJayakumar, Nikhil 15 May 2009 (has links)
Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at
an alarmingly rapid rate. This increase in power consumption, coupled with the increasing
demand for portable/hand-held electronics, has made power consumption a dominant
concern in the design of VLSI circuits today. Traditionally dynamic (switching) power has
dominated the total power consumption of VLSI circuits. However, due to process scaling
trends, leakage power has now become a major component of the total power consumption
in VLSI circuits. This dissertation explores techniques to reduce leakage, as well as
techniques to exploit leakage currents through the use of sub-threshold circuits.
This dissertation consists of two studies. In the first study, techniques to reduce leakage
are presented. These include a low leakage ASIC design methodology that uses high
VT sleep transistors selectively, a methodology that combines input vector control and circuit
modification, and a scheme to find the optimum reverse body bias voltage to minimize
leakage.
As the minimum feature size of VLSI fabrication processes continues to shrink with
each successive process generation (along with the value of supply voltage and therefore the
threshold voltage of the devices), leakage currents increase exponentially. Leakage currents
are hence seen as a necessary evil in traditional VLSI design methodologies. We present
an approach to turn this problem into an opportunity. In the second study in this dissertation,
we attempt to exploit leakage currents to perform computation. We use sub-threshold
digital circuits and come up with ways to get around some of the pitfalls associated with sub-threshold circuit design. These include a technique that uses body biasing adaptively
to compensate for Process, Voltage and Temperature (PVT) variations, a design approach
that uses asynchronous micro-pipelined Network of Programmable Logic Arrays (NPLAs)
to help improve the throughput of sub-threshold designs, and a method to find the optimum
supply voltage that minimizes energy consumption in a circuit.
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Analysis and optimization of VLSI Clock Distribution Networks for skew variability reductionRajaram, Anand K. 15 November 2004 (has links)
As VLSI technology moves into the Ultra-Deep Sub-Micron (UDSM) era, manufacturing variations, power supply noise and temperature variations greatly affect the performance and yield of VLSI circuits. Clock Distribution Network (CDN), which is one of the biggest and most important nets in any synchronous VLSI chip, is especially sensitive to these variations. To address this problem variability-aware analysis and optimization techniques for VLSI circuits are needed. In the first part of this thesis an analytical bound for the unwanted skew due to interconnect variation is established. Experimental results show that this bound is safer, tighter and computationally faster than existing approaches. This bound could be used in variation-aware clock tree synthesis.The second part of the thesis deals with optimizing a given clock tree to minimize the unwanted skew variations. Non-tree CDNs have been recognized as a promising approach to overcome the variation problem. We propose a novel non-tree CDN obtained by adding cross links in an existing clock tree. We analyze the effect of the link insertion on clock skew variability and propose link insertion schemes. The non-tree CDNs so obtained are shown to be highly tolerant to skew variability with very little increase in total wire-length. This can be used in applications such as ASIC design where a significant increase in the total wire-length is unacceptable.
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Data integrity for on-chip interconnectsSinghal, Rohit 17 September 2007 (has links)
With shrinking feature size and growing integration density in the Deep Sub-
Micron (DSM) technologies, the global buses are fast becoming the "weakest-links"
in VLSI design. They have large delays and are error-prone. Especially, in system-onchip
(SoC) designs, where parallel interconnects run over large distances, they pose
difficult research and design problems. This work presents an approach for evaluating
the data carrying capacity of such wires. The method treats the delay and reliability
in interconnects from an information theoretic perspective. The results point to an
optimal frequency of operation for a given bus dimension for maximum data transfer
rate. Moreover, this optimal frequency is higher than that achieved by present day
designs which accommodate the worst case delays.
This work also proposes several novel ways to approach this optimal data transfer
rate in practical designs.From the analysis of signal propagation delay in long wires,
it is seen that the signal delay distribution has a long tail, meaning that most signals
arrive at the output much faster than the worst case delay. Using communication theory,
these "good" signals arriving early can be used to predict/correct the "few"
signals that arrive late. In addition to this correction based on prediction, the approaches
use coding techniques to eliminate high delay cases to generate a higher transmission rate.
The work also extends communication theoretic approaches to other areas of
VLSI design. Parity groups are generated based on low output delay correlation to
add redundancy in combinatorial circuits. This redundancy is used to increase the
frequency of operation and/or reduce the energy consumption while improving the
overall reliability of the circuit.
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Performance and power optimization in VLSI physical designJiang, Zhanyuan 10 October 2008 (has links)
As VLSI technology enters the nanoscale regime, a great amount of efforts have
been made to reduce interconnect delay. Among them, buffer insertion stands out
as an effective technique for timing optimization. A dramatic rise in on-chip buffer
density has been witnessed. For example, in two recent IBM ASIC designs, 25% gates
are buffers.
In this thesis, three buffer insertion algorithms are presented for the procedure
of performance and power optimization. The second chapter focuses on improving circuit performance under inductance effect. The new algorithm works under
the dynamic programming framework and runs in provably linear time for multiple
buffer types due to two novel techniques: restrictive cost bucketing and efficient delay
update. The experimental results demonstrate that our linear time algorithm consistently outperforms all known RLC buffering algorithms in terms of both solution
quality and runtime. That is, the new algorithm uses fewer buffers, runs in shorter
time and the buffered tree has better timing.
The third chapter presents a method to guarantee a high fidelity signal transmission in global bus. It proposes a new redundant via insertion technique to reduce
via variation and signal distortion in twisted differential line. In addition, a new
buffer insertion technique is proposed to synchronize the transmitted signals, thus
further improving the effectiveness of the twisted differential line. Experimental results demonstrate a 6GHz signal can be transmitted with high fidelity using the new
approaches. In contrast, only a 100MHz signal can be reliably transmitted using a
single-end bus with power/ground shielding. Compared to conventional twisted differential line structure, our new techniques can reduce the magnitude of noise by 45%
as witnessed in our simulation.
The fourth chapter proposes a buffer insertion and gate sizing algorithm for
million plus gates. The algorithm takes a combinational circuit as input instead of
individual nets and greatly reduces the buffer and gate cost of the entire circuit.
The algorithm has two main features: 1) A circuit partition technique based on the
criticality of the primary inputs, which provides the scalability for the algorithm, and
2) A linear programming formulation of non-linear delay versus cost tradeoff, which
formulates the simultaneous buffer insertion and gate sizing into linear programming
problem. Experimental results on ISCAS85 circuits show that even without the circuit
partition technique, the new algorithm achieves 17X speedup compared with path
based algorithm. In the meantime, the new algorithm saves 16.0% buffer cost, 4.9%
gate cost, 5.8% total cost and results in less circuit delay.
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An automatic floorplanning system for use in the interactive architectural design of custom VLSI circuitsNadiadi, Y. January 1989 (has links)
No description available.
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Analysis of hardware descriptionsSingh, Satnam January 1991 (has links)
No description available.
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Entwicklung einer Testumgebung für einen ASIC im Rahmen des ATLAS L-1-TriggersWagner, Gregor. January 1999 (has links)
Heidelberg, Univ. Diplomarb., 1996.
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VLSI circuits for MIMO preprocessingLüthi, Peter Jan January 2009 (has links)
Zugl.: Zürich, Techn. Hochsch., Diss., 2009
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Functional programs as reconfigurable networks of communicating processesLeth, Lone January 1991 (has links)
No description available.
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Intermediate frequency CMOS analogue cells for wireless communicationsManetakis, Konstantinos January 1999 (has links)
No description available.
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