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International Telemetering Conference Proceedings / October 30-November 02, 1995 / Riviera Hotel, Las Vegas, Nevada / The Earth Observing System-AM (EOS-AM) spacecraft, the first in a series of spacecraft for the EOS, is scheduled for launch in June of 1998. This spacecraft will carry high resolution instruments capable of generating large volumes of earth science data at rates up to 150 Mbps. Data will be transmitted in a packet format based upon the Consultative Committee for Space Data Systems (CCSDS) Advanced Orbiting Systems (AOS) recommendations. The Data Systems Technology Division (DSTD) at NASA's Goddard Space Flight Center (GSFC) has developed a set of high performance CCSDS return-link processing systems to support testing and verification of the EOS-AM spacecraft. These CCSDS processing systems use Versa Module Eurocard bus (VMEBus) Very Large Scale Integration (VLSI)-based processing modules developed for the EOS ground segment to acquire and handle the high rate EOS data. Functions performed by these systems include frame synchronization, Reed-Solomon error correction, fill frame removal, virtual channel sorting, packet service processing, and data quality accounting. The first of the systems was delivered in October 1994 to support testing of the onboard formatting equipment. The second and third systems, delivered in April 1995, support spacecraft checkout and verification. This paper will describe the function and implementation of these systems.

International Telemetering Conference Proceedings / October 25-28, 1993 / Riviera Hotel and Convention Center, Las Vegas, Nevada / NASA Goddard Space Flight Center (GSFC) has developed a set of functional telemetry processing components based upon Very Large Scale Integration (VLSI) and Application Specific Integrated Circuits (ASIC). These components provide a framework for the assembly of telemetry data ground systems for space projects such as the Earth Observing System (EOS) and the Small Explorer (SMEX) mission series. Implementation of the ground systems for such projects using a common set of functional components has obvious cost benefits in both systems development and maintenance. Given the existence of these components, the next logical step is to utilize a similar approach and create a set of reusable software components for the implementation of telemetry data system monitoring and control functions. This paper describes a generalized set of software components, called the Telemetry Processing Control Environment (TPCE), which has been developed to fulfil this need. This combination of hardware and software components enables the rapid development of flexible, cost-effective telemetry processing systems capable of meeting the performance requirements facing NASA in the coming decade.

In the past decade, one of the major breakthroughs in computer science theory is the first construction of fully homomorphic encryption (FHE) scheme introduced by Gentry. Using a FHE one may perform an arbitrary numbers of computations directly on the encrypted data without revealing of the secret key. Therefore, a practical FHE provides an invaluable security application for emerging technologies such as cloud computing and cloud-based storage. However, FHE is far from real life deployment due to serious efficiency impediments. The main part of this dissertation focuses on accelerating the existing FHE schemes using GPU and hardware design to make them more efficient and practical towards real-life applications. Another part of this dissertation is for the hardware design of the large key-size RSA cryptosystem. As the Moore law continues driving the computer technology, the key size of the Rivest-Shamir-Adelman (RSA) encryption is necessary to be upgraded to 2048, 4096 or even 8192 bits to provide higher level security. In this dissertation, the FFT multiplication is employed for the large-size RSA hardware design instead of using the traditional interleaved Montgomery multiplication to show the feasibility of the FFT multiplication for large-size RSA design.

Zugl.: Hannover, Universiẗat, Diss., 2007.

High-level functional (or behavioral) simulation models are difficult, time-consuming, and expensive to develop. We report on a method for automatically generating the program code for a high-level functional simulation model. The high-level model is produced directly from the program code for the circuit components' functional models and a netlist description of their connectivity. A prototype has been implemented in LISP for the SIMMER functional simulator.

This paper presents the theory behind a model for a two-stage analog network for edge detection and image reconstruction to be implemented in VLSI. Edges are detected in the first stage using the multi-scale veto rule, which eliminates candidates that do not pass a threshold test at each of a set of different spatial scales. The image is reconstructed in the second stage from the brightness values adjacent to edge locations. The MSV rule allows good localization and efficient noise removal. Since the reconstructed images are visually similar to the originals, the possibility exists of achieving significant bandwidth compression.

This thesis describes two programs for generating tests for digital circuits that exploit several kinds of expert knowledge not used by previous approaches. First, many test generation problems can be solved efficiently using operation relations, a novel representation of circuit behavior that connects internal component operations with directly executable circuit operations. Operation relations can be computed efficiently by searching traces of simulated circuit behavior. Second, experts write test programs rather than test vectors because programs are more readable and compact. Test programs can be constructed automatically by merging program fragments using expert-supplied goal-refinement rules and domain-independent planning techniques.

Multiple Input Multiple Output (MIMO) systems are a key technology for next generation high speed wireless communication standards like 802.11n, WiMax etc. MIMO enables spatial multiplexing to increase channel bandwidth which requires the use of multiple antennas in the receiver and transmitter side. The increase in bandwidth comes at the cost of high silicon complexity of MIMO detectors which result, due to the intricate algorithms required for the separation of these spatially multiplexed streams. Previous implementations of MIMO detector have mainly dealt with the issue of complexity reduction, latency minimization and throughput enhancement. Although, these detectors have successfully mapped algorithms to relatively simpler circuits but still, latency and throughput of these systems need further improvements to meet standard requirements. Additionally, most of these implementations don’t deal with the requirements of reconfigurability of the detector to multiple modulation schemes and different antennae configurations. This necessary requirement provides another dimension to the implementation of MIMO detector and adds to the implementation complexity. This thesis focuses on the efficient VLSI implementation of the MIMO detector with an emphasis on performance and re-configurability to different modulation schemes. MIMO decoding in our detector is based on the fixed sphere decoding algorithm which has been simplified for an effective VLSI implementation without considerably degrading the near optimal bit error rate performance. The regularity of the architecture makes it suitable for a highly parallel and pipelined implementation. The decoder has intrinsic traits for dynamic re-configurability to different modulation and encoding schemes. This detector architecture can be easily tuned for high/low performance requirements with slight degradation/improvement in Bit Error Rate (BER) depending on needs of the overlying application. Additionally, various architectural optimizations like pipelining, parallel processing, hardware scheduling, dynamic voltage and frequency scaling have been explored to improve the performance, energy requirements and re-configurability of the design.

Application of neural prostheses in today's medicine successfully helps patients to increase their activities of daily life and participate in social activities again. These implantable microsystems provide an interface to the nervous system, giving cellular resolution to physiological processes unattainable today with non-invasive methods. The latest developments in genetic engineering, nanotechnologies and materials science have paved the way for these complex systems to interface the human nervous system. The ideal system for neural signal recording would be a fully implantable device which is capable of amplifying the neural signals and transmitting them to the outside world while sustaining a long-term and accurate performance, therefore different sciences from neurosciences, biology, electrical engineering and computer science have to interact and discuss the synergies to develop a practical system which can be used in daily medicine practice. This work investigates the main building blocks necessary to improve the quality of acquired signal from the micro-electronics and MEMS perspectives. While all of these components will be ultimately embedded in a fully implantable recording probe, each of them addresses and deals with a specific obstacle in the neural signal recording path. Specifically we present a low-voltage low-noise low-power CMOS amplifier particularly designed for neural recording applications. This is done by surveying a number of designs and evaluating each design against the requirements for a neural recording system such as power dissipation and noise, and then choosing the most suitable topology for design and implementation of a fully implantable system. In addition a surface modification method is investigated to improve the sacrificial properties and biocompatibility of probe in order to extend the implant life and enhance the signal quality.