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This dissertation presents new concepts in front end design for receivers with large, multiband tuning ranges. Such receivers are required to support large bandwidths (up to 10's of MHz) over very large tuning ranges (30:1 and beyond) with antennas that are usually narrowband, or which at best support multiple narrow bandwidths. Traditional techniques to integrate a single antenna with such receivers are limited in their ability to handle simultaneous channels distributed over very large tuning ranges, which is important for frequency-agile cognitive radio, surveillance, and other applications requiring wideband or multiband monitoring. Direct conversion architecture is gaining popularity due to the recent advancements in CMOS--based RFIC technology. The possibility of multiple parallel transceivers in RF CMOS suggests an approach to antenna--receiver integration using multiplexers. This dissertation describes an improved use of multiplexers to integrate antennas to receivers. First, the notion of sensitivity--constrained design is considered. In this approach, the goal is first to achieve sensitivity which is nominally dominated by external (environmental) noise, and then secondly to improve bandwidth to the maximum possible consistent with this goal. Next, a procedure is developed for designing antenna-multiplexer-preamplifier assemblies using this philosophy. It is shown that the approach can significantly increase the usable bandwidth and number of bands that can be supported by a single, traditional antenna. This performance is verified through field experiments. A prototype multiband multimode radio for public safety applications using these concepts is designed and demonstrated. / Ph. D.

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This dissertation presents novel Harmonic Rejection (HR) Mixer architectures to obtain a high level of harmonic rejection. This is achieved by reducing the sensitivity to mismatches in devices operating at high frequencies. Consequently, the HR performance for this mixer architecture is primarily determined by resistor and capacitor matching at low intermediate frequencies (IF). Since large resistor areas can be used at relatively less power penalty in the low frequency IF section, superior HR performance is realized. A design fabricated in 110 nm CMOS process, rejects up to the fi rst 14 local oscillator (LO) harmonics and achieves 3rd, 5th and 7th HR ratios in excess of 52, 54 and 55 dB respectively, without any calibration or trimming. This mixer architecture also rejects flicker noise, has improved image rejection (IR) and second-order input-intercept-point (IIP2) performance. By using a clock N times the desired LO frequency, this scheme rejects the (N-1)th LO harmonic only by an amount of 20log(N-1) dB. A new technique is presented that enables better HR for the (N-1)th harmonic while preserving the level of rejection for other harmonics. This mixer fabricated in 55 nm standard CMOS process has a programmable number of 8, 10, 12 or 14 mixer phases and achieves an improvement of 29 dB for the (N-1)th harmonic while achieving 52 dB of rejection for the 3rd harmonic. It also rejects flicker noise and has an IIP2 performance of 68 dBm. The mixers presented in this dissertation set the state-of-the-art in HR performance for single-stage mixers with configurable number of phases without using any calibration or trimming. / text

Le convertisseur analogique-numérique (ADC), fait fonction d’interface entre les domaines de représentation analogique et numérique des systèmes mixtes de traitement du signal.Il est un élément central en cela que ses performances circonscrivent celles des traitements numériques qui lui succèdent et a fortiori celles de son dispositif hôte. C’est notamment le casdes récepteurs radioélectriques numériques à large bande instantanée. De fait, ces systèmes voient leurs performances de dynamiques instantanées monotonale (DTDR) et bitonale (STDR)– i.e. leur capacité à traiter simultanément des composantes de faible puissance en présence d’une ou plusieurs autres composantes de plus forte puissance – limitées par la linéarité de leur ADC.Ce dernier caractère est quantifié par les performances de dynamique sans raies parasites (SFDR)et distorsion d’intermodulation (IMD) d’un ADC.Les critères de DTDR et de STDR sont essentiels pour les récepteurs radios numériques de guerre électronique conçus pour le traitement des signaux de radiocommunications. En effet, ces dispositifs sont employés à l’établissement de la situation tactique de l’environnement électromagnétique à des fins de support de manoeuvres militaires. La fidélité de la représentation numérique du signal analogique reçu est donc critique. Ainsi, cette thèse vise à étudier la linéarisation des ADC, i.e. l’augmentation des SFDR et IMD, en vue de l’amélioration des dynamiques instantanées de ces récepteurs.Dans ce manuscrit, nous traitons cette problématique selon deux axes différents. Le premier consiste à corriger les distorsions introduites par un ADC au moyen de tables de correspondances(LUT) pré-remplies. À cette fin, nous proposons un algorithme de remplissage de LUT procédant d’une méthode de la littérature par la réduction de moitié du nombre de coefficients à déterminer pour estimer la non-linéarité intégrale (INL) d’un ADC. Sur la base de cette nouvelle méthode,nous développons une approche de correction des non-linéarités dynamiques introduites par un ADC reposant sur une paire de LUT statiques et présentons un exemple d’algorithme permettant de l’opérer. Le second axe du manuscrit repose sur la modélisation comportementale de l’ADC par les séries de Volterra à temps discrets et leurs dérivés. En premier lieu, nous considérons les trois problématiques fondamentales de cette approche de linéarisation : la modélisation ;l’identification de modèle ; et l’inversion de modèle. Puis, nous définissons trois solutions de linéarisation d’ADC aveugles. Enfin, nous analysons l’implémentation sur circuits à réseaux logiques programmables (FPGA) de l’un de ces algorithmes afin d’évaluer la pertinence d’uneopération en temps-réel des échantillons de sortie d’un ADC échantillonnant à une fréquence d’environ 400 MHz. / The analog-to-digital converter (ADC) is a central component of mixed signal systems as the interface between the analog and digital representation spaces. Its performance bounds that of the device it is integrated in. Indeed, ADC linearity is essential for maintaining in the digital space the reliability of its input signal and then that of the information it carries.Wideband digital radio receivers are particularly sensitive to ADC non-linearities. Single-tone and dual-tone dynamic range (respectively STDR and DTDR) of such systems – i.e. the abilityto process simultaneously signal components with high power ratio – are limited by the spurious free dynamic range (SFDR) and intermodulation distortion (IMD) of their internal ADC.DTDR et de STDR are key metrics for electronic warfare wideband digital radio receivers developed for radiocommunication signal processing. As a matter of fact, these equipments are employed for analyzing the tactical situation of the radiofrequency spectrum in order to support military maneuvers. Hence, signal integrity is critical. This thesis deals with the ADC linearization issue in this context. Thus, it aims to study techniques for increasing ADC SFDRand IMD for the purpose of improving dynamic ranges of electronic warfare wideband digitalr eceivers.In this dissertation, the problematic of ADC linearization is approached in two different ways.On the one hand, we consider distortion compensation using pre-filled look-up tables (LUT). Wepropose an algorithm for filling LUTs that stems from an existing method by halving the numberof coefficients required for the integral non-linearity (INL) estimation. Then, based on this new method, we develop an approach for correcting ADC dynamic non-linearities using a couple ofstatic LUTs and we present an example of algorithm for operating this method. On the other hand,we study linearization solutions that rely on behavioural modelling of ADCs using discrete-time Volterra series and its derivatives. First, we address the three fundamental issues of this approach:modelling ; model identification ; and model inversion. Then, we propose three blind linearization algorithms. Finally, we consider the implementation on field programmable gate array (FPGA) of one of them for the purpose of evaluating the relevance of real-time linearization of an ADC sampling at about 400 MHz.