Před necelými dvaceti lety byl představen nekonvenční přístup k implementaci multifunkčních obvodů, tzv. polymorfní elektronika. Polymorfní elektronika umožňuje implementovat jedním obvodem dvě nebo více funkcí, přičemž aktuálně funkce závisí na stavu okolního prostředí obvodu. Klíčovými komponentami takových obvodů jsou polymorfní hradla. Od představení konceptu polymorfní elektroniky bylo publikováno několik desítek polymorfních hradel. Parametry většiny z nich však neumožňují jejich využití v reálných aplikacích. Bez dostatečného množství polymorfních hradel s dobrými parametry však nejspíše zůstane v aplikacích založených na multifunkčním chování nebo rekonfiguraci konvenční elektronika preferována před tou polymorfní. Tato disertační práce představuje nový přístup k polymorfní elektronice. Je založen na hradlech, jejichž funkce závisí na polaritě napájecích přívodů. Cílem této disertační práce je ukázat, že takový přístup umožňuje navrhnout hradla s výrazně lepšími parametry. Aby bylo možné systematicky navrhovat na úrovni tranzistorů takováto hradla, byla navržena evoluční metoda založená na kartézském genetickém programování (CGP). To umožnilo navrhnout několik sad efektivních polymorfních hradel založených jak na konvenčních MOSFET tranzistorech, tak na double-gate ambipolárních tranzistorech. Z těchto sad hradel byla vytvořena knihovna, která je v současné době volně dostupná pro ostatní vědce. Dále byla v této práci navržena řada složitějších obvodů založená na navržených hradlech. Na různých úrovních návrhu obvodů (hradla, RTL, cílová aplikace) je pak ukázáno, že navrhovaný polymorfismus na úrovni hradel představuje velké výhody v porovnání s předchozí generací polymorfních hradel, ale může být také konkurenceschopný nebo výrazně lepší než konvenční řešení takovýchto obvodů.

The goal of this Master thesis is to design a power convertor for BLDC motor 48V/2kW. Emphasis is placed on the small dimensions of the final printed circuit board. Therefore, power SMD transistors STL135N8F7AG are used in small packages PowerFlat 5x6. To reduce area of the PCB, electrolytic capacitors are mounted on a separate board, which is located above the main PCB. Small high-capacity 22F/100V ceramic capacitors are used in the DC-LINK as well. They are located as close as possible to the power SMD tranzistors. Control logic will be provided by microprocesor STM32G474RE. High resolution timer HRTIM1 is used. The first part of this thesis is devoted to the brief description of BLDC motor construction and driving. Next parts are focused on the design itself.

This work is focused on the design and construction of component parts of resistance saw. Mechanical parts consist of a movable bracket and a taut cutting wire of Constantan. Electrical parts are designed to supply and control temperature of the cutting wire. The current intensity in the cutting wire is compared with the required current intensity. The difference of these two measurements is fed into a PI - controller. The next part is a PWM generator which generates the square wave signal. The pulse ratio of this signal is proportional to the required temperature of the cutting wire. This signal switches a switching converter that consists of a power transistor P-MOSFET IRF5210 and a diode MBR20100CT. Choking coil with a ferrite E core and with the cutting wire is connected to the output of the converter.

Work is focused on computer modeling of PN junction and MOSFET transistor in the program COMSOL Multiphysics and in program TiberCAD. The text is discussed on the drift and diffusion in semiconductors. Also shown is a method of modeling the PN junction and MOSFET transistor in the programs and compare models.

This master’s thesis deals with the design of the switching power supply on the principle of high frequency converter. The goal of this thesis is construction of converter which is using GaN MOSFET transistors and SiC diodes for switching. The converter uses two switch forward power supply topology. Unusually high switching frequency was chosen for the design with power transformer with open magnetic core. The outcome of this work is functional converter which is primarily intended for educational and demonstrational purposes. Multiple parts of this converter are divided into individual blocks, which can be further used for construction of other types of switching converters.

Die vorliegende Arbeit beschäftigt sich mit DC/DC-Wandlern zur Einbindung von Doppelschichtkondensatoren in das Fahrzeugenergiebordnetz. Zunächst werden die Anforderungen an derartige DC/DC-Wandler anhand dreier entsprechender Beispielanwendungen zusammengestellt und verglichen. Für die Anwendung zur Entkopplung transienter Hochleistungsverbraucher, wie beispielsweise eine elektrische Lenkung, wird ein DC/DC-Wandler-Konzept entwickelt. Es findet ein Vergleich von drei geeigneten Topologien mittels einer hierfür erarbeiteten Methode statt, mit dem Ziel die beste Lösung für den betrachteten Anwendungsfall zu ermitteln. Um adäquate Kritierien für die Wahl der Schaltfrequenz und der Induktivitäten von Speicherdrosseln aufzustellen, erfolgt eine Untersuchung des Einflusses des Drosselstromwechselanteils auf das Schaltverhalten der MOSFETs sowie auf bestimmte Bereiche der EMV-Störemissionen. Als Methoden zur Optimierung des Synchrongleichrichterbetriebs werden das Parallelschalten von Schottky-Dioden und Synchrongleichrichtern sowie die Variation der Ausschalttotzeiten von Synchrongleichrichtern untersucht. Weiterhin wird unter Berücksichtigung der Besonderheiten der Anwendung und Topologie ein Konzept für die Regelung des Wandlers entwickelt. Abschließend findet eine Vorstellung ausgewählter Aspekte zur Umsetzung des DC/DC-Wandler-Konzepts sowie der Ergebnisse experimenteller Untersuchungen statt.

Scaling has been pivotal in the success of the Moore's law. Using scaling techniques to improve the MOSFET comes at a risk of growing short channel effects. This publication deals with the theoretical study of impact of gate length scaling on planar bulk MOSFET. A systematical study shows that the impact of short channel effects like drain induced barrier lowering, subthreshold leakage, hot carrier generation and channel length modulation grows with gate length scaling. Thereby degrading the MOSFET performance. In addition to the numerical device simulation an analytical modelling of the device is also performed. Though the analytical model explains the device characteristic trends, it is found to be quantitative inaccurate in comparison to the numerical model especially when scaling below deep sub-micrometer regime.

This thesis presents the modeling and fabrication of a new solid-state device meant to be used for digital logic circuits. Most current logic circuits are based on MOSFETs. The new logic device uses some of the same operating principles, but also relies on optical illumination to provide input power. In order to obtain the desired current-voltage behavior of the new device, the Silvaco (Atlas) device simulation was used to give some insight into the correct doping levels in the semiconductor and device geometries. Prototypes were fabricated on p-type silicon wafers using CMOS fabrication processes including oxide growth, photolithography, precise plasma or chemical wet etching, diffusion processes, and thin film evaporation. Electrical measurements were done by using an HP4156 parameter analyzer to measure several output voltage signals at one time while an illuminating the device with laser light. The current-voltage characteristics under different biasing conditions with an optical illumination condition were measured and showed characteristics similar to an nMOS transistor.

Modern technology needs and advancements have introduced various new concepts such as Internet-of-Things, electric automotive, and Artificial intelligence. This implies an increased activity in the electronics domain of analog and high frequency. Silicon devices have emerged as a cost-effective solution for such diverse applications. As these silicon devices are pushed towards higher performance, there is a continuous need to improve fabrication, power efficiency, variability, and reliability. Often, a direct trade-off of higher performance is observed in the reliability of semiconductor devices. The acceleration-based methodologies used for reliability assessment are the adequate time-saving solution for the lifetime's extrapolation but come with uncertainty in accuracy. Thus, the efforts to improve the accuracy of reliability characterization methodologies run in parallel. This study highlights two goals that can be achieved by incorporating high-frequency characterization into the reliability characteristics. The first one is assessing high-frequency performance throughout the device's lifetime to facilitate an accurate description of device/circuit functionality for high-frequency applications. Secondly, to explore the potential of high-frequency characterization as the means of scanning reliability effects within devices. S-parameters served as the high-frequency device's response and mapped onto a small-signal model to analyze different components of a fully depleted silicon-on-insulator MOSFET. The studied devices are subjected to two important DC stress patterns, i.e., Bias temperature instability stress and hot carrier stress. The hot carrier stress, which inherently suffers from the self-heating effect, resulted in the transistor's geometry-dependent magnitudes of hot carrier degradation. It is shown that the incorporation of the thermal resistance model is mandatory for the investigation of hot carrier degradation. The property of direct translation of small-signal parameter degradation to DC parameter degradation is used to develop a new S-parameter based bias temperature instability characterization methodology. The changes in gate-related small-signal capacitances after hot carrier stress reveals a distinct signature due to local change of flat-band voltage. The measured effects of gate-related small-signal capacitances post-stress are validated through transient physics-based simulations in Sentaurus TCAD.:Abstract Symbols Acronyms 1 Introduction 2 Fundamentals 2.1 MOSFETs Scaling Trends and Challenges 2.1.1 Silicon on Insulator Technology 2.1.2 FDSOI Technology 2.2 Reliability of Semiconductor Devices 2.3 RF Reliability 2.4 MOSFET Degradation Mechanisms 2.4.1 Hot Carrier Degradation 2.4.2 Bias Temperature Instability 2.5 Self-heating 3 RF Characterization of fully-depleted Silicon on Insulator devices 3.1 Scattering Parameters 3.2 S-parameters Measurement Flow 3.2.1 Calibration 3.2.2 De-embedding 3.3 Small-Signal Model 3.3.1 Model Parameters Extraction 3.3.2 Transistor Figures of Merit 3.4 Characterization Results 4 Self-heating assessment in Multi-finger Devices 4.1 Self-heating Characterization Methodology 4.1.1 Output Conductance Frequency dependence 4.1.2 Temperature dependence of Drain Current 4.2 Thermal Resistance Behavior 4.2.1 Thermal Resistance Scaling with number of fingers 4.2.2 Thermal Resistance Scaling with finger spacing 4.2.3 Thermal Resistance Scaling with GateWidth 4.2.4 Thermal Resistance Scaling with Gate length 4.3 Thermal Resistance Model 4.4 Design for Thermal Resistance Optimization 5 Bias Temperature Instability Investigation 5.1 Impact of Bias Temperature Instability stress on Device Metrics 5.1.1 Experimental Details 5.1.2 DC Parameters Drift 5.1.3 RF Small-Signal Parameters Drift 5.2 S-parameter based on-the-fly Bias Temperature Instability Characterization Method 5.2.1 Measurement Methodology 5.2.2 Results and Discussion 6 Investigation of Hot-carrier Degradation 6.1 Impact of Hot-carrier stress on Device performance 6.1.1 DC Metrics Degradation 6.1.2 Impact on small-signal Parameters 6.2 Implications of Self-heating on Hot-carrier Degradation in n-MOSFETs 6.2.1 Inclusion of Thermal resistance in Hot-carrier Degradation modeling 6.2.2 Convolution of Bias Temperature Instability component in Hot-carrier Degradation 6.2.3 Effect of Source and Drain Placement in Multi-finger Layout 6.3 Vth turn-around effect in p-MOSFET 7 Deconvolution of Hot-carrier Degradation and Bias Temperature Instability using Scattering parameters 7.1 Small-Signal Parameter Signatures for Hot-carrier Degradation and Bias Temperature Instability 7.2 TCAD Dynamic Simulation of Defects 7.2.1 Fixed Charges 7.2.2 Interface Traps near Gate 7.2.3 Interface Traps near Spacer Region 7.2.4 Combination of Traps 7.2.5 Drain Series Resistance effect 7.2.6 DVth Correction 7.3 Empirical Modeling based deconvolution of Hot-carrier Degradation 8 Conclusion and Recommendations 8.1 General Conclusions 8.2 Recommendations for Future Work A Directly measured S-parameters and extracted Y-parameters B Device Dimensions for Thermal Resistance Modeling C Frequency response of hot-carrier degradation (HCD) D Localization Effect of Interface Traps Bibliography

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