M. Tech. (Engineering: Electrical, Department Electronic Engineering, Faculty of Engineering and Technology), Vaal University of Technology / The global trends towards energy efficiency have facilitated the need for technological advancements in the design and control of power electronic converters for energy processing. The proposed design is intended to make the practical implementation of converters easier. The development of a universal bidirectional galvanic isolated switch module will be used to drive any MOSFET or IGBT in any position in any topology whether the load is AC or DC. Semiconductor switches are required and are also integrated for fast switching times in power converter applications The structure of the power switch module consists of an opto-coupler which will provide an isolation barrier for maximum galvanic isolation between the control circuitry and power stage. It also consists of a high performance gate drive circuit for high speed switching applications with a floating supply. / Telkom South Africa Ltd, TFMC Pty Ltd, M-TEC, THRIP

O presente trabalho descreve o projeto de modelos neurais pulsados em tecnologia CMOS. Foram projetados dois modelos: um neurônio baseado em condutâncias e um neurônio do tipo integra e dispara. O primeiro gera impulsos elétricos similares aos potenciais de ação gerados pelo neurônio biológico. Mediante simulação, foram observadas as seguintes características: disparo do impulso quando se atinge a tensão de limiar, hiperpolarização após o potencial de ação, retorno passivo à tensão de repouso, presença de período refratário e relação sigmoide entre a frequência de disparo e a intensidade do estímulo. Da mesma maneira, foi reproduzida a curva mínima duração x amplitude de estímulo típico dos neurônios biológicos. O segundo realiza a codificação de uma grandeza analógica na fase relativa dos impulsos elétricos gerados. Os impulsos gerados pelo circuito estão afastados em relação a um sinal periódico, em um intervalo que apresenta uma dependência logarítmica de uma corrente de entrada. John Hopfield propus esse tipo de codificação para explicar o reconhecimento de padrões com independência de escala, realizado pelo cérebro humano. No decorrer da pesquisa, foi necessário desenvolver algumas expressões analíticas para o projeto de circuitos de baixa frequência em CMOS, não encontradas na literatura estudada. As expressões estão baseadas na equação da corrente do transistor MOS proposta no modelo conhecido como Advanced Compact Mosfet (ACM). O projeto, implementação e testes de um transcondutor linearizado, e os resultados das simulações dos modelos neurais projetados, demonstram a validade das expressões desenvolvidas. / This work describes the design of pulsed neural models in CMOS technology. Two models were designed: a conductance based neuron and an integrate and fire neuron. The first generates electrical impulses similar to action potentials generated by the biological neuron. Through simulation, the following characteristics were observed: pulse trigger after reaching threshold voltage, hyperpolarization after the action potential, passive return to resting potential, presence of refractory period and sigmoid relationship between the firing rate and the stimulus intensity. Likewise, the curve minimal duration vs stimulus amplitude typical of biological neurons was reproduced. The second one performs the encoding of an analog input in the relative phase of electrical impulses. The impulses generated by the circuit are delayed with respect to a reference periodic signal, in a range that has a logarithmic dependence on an input current. John Hopfield proposed this type of encoding to explain the scale independent pattern recognition performed by the human brain. During the research, it was necessary to develop some analytical expressions for the design of low-frequency circuits in CMOS, not found in the literature studied. The expressions are based on the Advanced Compact MOSFET (ACM) model. The design, implementations and testing of a linearized transconductor, and the simulations results of the neural models designed, demonstrate the validity of the expressions developed.

O Ruído de Baixa Frequência (LFN), tais como o ruído flicker e o Random Telegraph Noise (RTN), são limitadores de performance em muitos circuitos analógicos e digitais. Para transistores diminutos, a densidade espectral de potência do ruído pode variar muitas ordens de grandeza, impondo uma séria limitação na performance do circuito e também em sua confiabilidade. Nesta tese, nós propomos um novo modelo de RTN estatístico para descrever o ruído de baixa frequência em MOSFETs. Utilizando o modelo proposto, pode-se explicar e calcular o valor esperado e a variabilidade do ruído em função das polarizações, geometrias e dos parâmetros físicos do transistor. O modelo é validado através de inúmeros resultados experimentais para dispositivos com canais tipo n e p, e para diferentes tecnologias CMOS. É demonstrado que a estatística do ruído LFN dos dispositivos de canal tipo n e p podem ser descritos através do mesmo mecanismo. Através dos nossos resultados e do nosso modelo, nós mostramos que a densidade de armadilhas dos transistores de canal tipo p é fortemente dependente do nível de Fermi, enquanto para o transistor de tipo n a densidade de armadilhas pode ser considerada constante na energia. Também é mostrado e explicado, através do nosso modelo, o impacto do implante de halo nas estatísticas do ruído. Utilizando o modelo demonstra-se porque a variabilidade, denotado por σ[log(SId)], do RTN/LFN não segue uma dependência 1/√área; e fica demonstrado que o ruído, e sua variabilidade, encontrado em nossas medidas pode ser modelado utilizando parâmetros físicos. Além disso, o modelo proposto pode ser utilizado para calcular o percentil do ruído, o qual pode ser utilizado para prever ou alcançar certo rendimento do circuito. / Low Frequency Noise (LFN) and Random Telegraph Noise (RTN) are performance limiters in many analog and digital circuits. For small area devices, the noise power spectral density can easily vary by many orders of magnitude, imposing serious threat on circuit performance and possibly reliability. In this thesis, we propose a new RTN model to describe the statistics of the low frequency noise in MOSFETs. Using the proposed model, we can explain and calculate the Expected value and Variability of the noise as function of devices’ biases, geometry and physical parameters. The model is validated through numerous experimental results for n-channel and p-channel devices from different CMOS technology nodes. We show that the LFN statistics of n-channel and p-channel MOSFETs can be described by the same mechanism. From our results and model, we show that the trap density of the p-channel device is a strongly varying function of the Fermi level, whereas for the n-channel the trap density can be considered constant. We also show and explain, using the proposed model, the impact of the halo-implanted regions on the statistics of the noise. Using this model, we clarify why the variability, denoted by σ[log(SId)], of RTN/LFN doesn't follow a 1/√area dependence; and we demonstrate that the noise, and its variability, found in our measurements can be modeled using reasonable physical quantities. Moreover, the proposed model can be used to calculate the percentile quantity of the noise, which can be used to predict or to achieve certain circuit yield.

O presente trabalho descreve o projeto de modelos neurais pulsados em tecnologia CMOS. Foram projetados dois modelos: um neurônio baseado em condutâncias e um neurônio do tipo integra e dispara. O primeiro gera impulsos elétricos similares aos potenciais de ação gerados pelo neurônio biológico. Mediante simulação, foram observadas as seguintes características: disparo do impulso quando se atinge a tensão de limiar, hiperpolarização após o potencial de ação, retorno passivo à tensão de repouso, presença de período refratário e relação sigmoide entre a frequência de disparo e a intensidade do estímulo. Da mesma maneira, foi reproduzida a curva mínima duração x amplitude de estímulo típico dos neurônios biológicos. O segundo realiza a codificação de uma grandeza analógica na fase relativa dos impulsos elétricos gerados. Os impulsos gerados pelo circuito estão afastados em relação a um sinal periódico, em um intervalo que apresenta uma dependência logarítmica de uma corrente de entrada. John Hopfield propus esse tipo de codificação para explicar o reconhecimento de padrões com independência de escala, realizado pelo cérebro humano. No decorrer da pesquisa, foi necessário desenvolver algumas expressões analíticas para o projeto de circuitos de baixa frequência em CMOS, não encontradas na literatura estudada. As expressões estão baseadas na equação da corrente do transistor MOS proposta no modelo conhecido como Advanced Compact Mosfet (ACM). O projeto, implementação e testes de um transcondutor linearizado, e os resultados das simulações dos modelos neurais projetados, demonstram a validade das expressões desenvolvidas. / This work describes the design of pulsed neural models in CMOS technology. Two models were designed: a conductance based neuron and an integrate and fire neuron. The first generates electrical impulses similar to action potentials generated by the biological neuron. Through simulation, the following characteristics were observed: pulse trigger after reaching threshold voltage, hyperpolarization after the action potential, passive return to resting potential, presence of refractory period and sigmoid relationship between the firing rate and the stimulus intensity. Likewise, the curve minimal duration vs stimulus amplitude typical of biological neurons was reproduced. The second one performs the encoding of an analog input in the relative phase of electrical impulses. The impulses generated by the circuit are delayed with respect to a reference periodic signal, in a range that has a logarithmic dependence on an input current. John Hopfield proposed this type of encoding to explain the scale independent pattern recognition performed by the human brain. During the research, it was necessary to develop some analytical expressions for the design of low-frequency circuits in CMOS, not found in the literature studied. The expressions are based on the Advanced Compact MOSFET (ACM) model. The design, implementations and testing of a linearized transconductor, and the simulations results of the neural models designed, demonstrate the validity of the expressions developed.

<div>Germanium-based MOS device which is considered as one of the promising alternative channel materials has been studied with well-known FinFET, nanowire structures and HKMG (High-k metal gate). Recent introduction of Ferroelectric (FE) Zr-doped HfO₂ (Hf_xZr_1-xO₂, HZO) has opened various possibilities both in memory and logic</div><div>applications.</div><div><br></div><div>First, integration of FE HZO into the conventional Ge platform was studied to demonstrate Ge FeFET. The FE oxide was deposited with optimized atomic layer deposition (ALD) recipe by intermixing HfO₂ and ZrO₂. The HZO film was characterized with FE tester, XRD and AR-XPS. Then, it was integrated into conventional gate stack of Ge devices to demonstrate Ge FeFETs. Polarization switching was measured with ultrafast measurement set-up down to 100 ps.</div><div><br></div><div>Then, HZO layer was controlled for the first demonstration of hysteresis-free Ge negative capacitance (NC) CMOS FinFETs with sub-60mV/dec SS bi-directionally at room temperature towards possible logic applications. Short channel effect in Ge NCFETs were compared with our reported work to show superior robustness. For smaller widths that cannot be directly written by the e-beam lithography tool, digital etching on Ge fins were optimized.</div><div>Lastly, Ge FeFET-based synaptic device for neuromorphic computing was demonstrated. Optimum pulsing schemes were tested for both potentiation and depression which resulted in highly linear and symmetric conductance profiles. Simulation was done to analyze Ge FeFET's role as a synaptic device for deep neural network.</div>

La réalisation de jonctions ultra-minces et fortement dopées est un enjeu majeur pour poursuivre la miniaturisation des dispositifs microélectroniques. En effet, la réduction de taille du transistor MOS, composant de base de la microélectronique silicium, exige des conditions drastiques notamment sur les caractéristiques dimensionnelles et électriques des zones dopées constituant la source et le drain du transistor. Les technologies utilisées actuellement pour la réalisation de ces couches dopées seront, à court terme, incapables de tenir les spécifications imposées par l'évolution prévue pour les dix années à venir. Au cours de ce travail de thèse nous avons étudié des procédés de dopage par laser, susceptibles de répondre à ces exigences, primordiales pour le bon fonctionnement du MOS. Nous avons disposé pour étudier les procédés de recuit et de dopage, de deux montages expérimentaux qui utilisent deux lasers impulsionnels ayant des caractéristiques temporelles très différentes: un laser industriel VEL 15 XeCl (15J, 200ns) développé et mis à disposition par la société SOPRA dans ses locaux, et un laser, plus conventionnel, Lambda Physik XeCl (200mJ, 20ns), installé à l'IEF. Après avoir présenter les différentes techniques utilisées ou susceptibles d'être utilisées pour la réalisation de jonctions dopées, les dispositifs optiques expérimentaux utilisés dans ce travail ont été décrit en détail, ainsi que les différents phénomènes mis enjeu lors de l'irradiation laser. Des modélisations thermiques ont permis de mieux comprendre les paramètres clés du recuit laser et se sont avéré en bon accord avec de nombreuses caractérisations réalisées. Puis l'intégration du procédé laser aux autres technologies de fabrication du MOSFET a été étudiée et testée. Cette étude a permis d'obtenir des transistors fonctionnels démontrant la possibilité de l'utilisation de techniques laser pour la réalisation de jonctions ultra fines dans la chaîne de fabrication des transistors CMOS.

La réduction constante de la taille des transistors conduit aujourd'hui à des dispositifs nano-métriques dans lesquels les effets quantiques sont de plus en plus prédominants. Ce travail modélise des transistors MOSFET ultimes et détermine l'impact des effets quantiques dans les architectures multi-grilles émergeantes. Nous utilisons le formalisme auto-cohérent des fonctions de Green hors-équilibre exprimé dans la théorie des liaisons fortes. Nous simulons tout d'abord un transistor double-grille 2D confiné, dans lequel l'axe source-drain est représenté par une chaîne atomique. Nous étudions l'amplitude du courant tunnel source-drain en fonction de la longueur de grille et montrons que les transistors conservent des caractéristiques électriques acceptables jusqu'à une longueur de grille de 7 nm. Nous développons ensuite un modèle 3D pour décrire les architectures à nanofil de silicium (Tri-gate, Pi-gate, Omega-gate, Gate-all-around). Une étude détaillée illustre plusieurs concepts de la théorie de transport de Landauer (quantum de conductance, résistance des réservoirs) et compare les performances électriques de chaque configuration de grille. Nous discutons l'influence du contrôle électrostatique en fonction de la longueur de grille et des dimensions de la section transverse. Enfin, nous proposons un modèle capable de traiter la présence de défauts ponctuels dans de tels composants 3D et analysons l'impact de leur type et de leur position.

La course à la miniaturisation des transistors MOS (Métal Oxyde Semiconducteur) implique l'utilisation de nouvelles technologies d'amélioration des performances. Notamment, l'ingénierie de contrainte mécanique est aujourd'hui devenue une étape incontournable. Dans ce contexte, les objectifs de ce travail sont de modéliser les dispositifs des prochains nœuds technologiques et de quantifier l'impact de la contrainte mécanique sur le transport. La mobilité est le facteur de mérite principalement exploité pour quantifier les performances d'une technologie et l'un des paramètres clés des simulateurs commerciaux. Dans ce cadre, le concept de mobilité effective et de mobilité de magnétorésistance dans les dispositifs courts est analysé et le rôle prépondérant des effets non stationnaires dans leur extraction est clairement identifié et quantifié par des modèles avancés. Ensuite, grâce à la version « Full Band » du simulateur particulaire Monte Carlo MONACO développée durant cette thèse, l'influence de la contrainte sur la structure de bandes et ses répercussions sur le transport dans les transistors courts sont étudiées. En bande de valence, le régime balistique est loin d'être atteint et la mobilité reste représentative des performances. Enfin, l'impact de la contrainte uniaxiale sur la mobilité des trous en couche d'inversion est étudiée par le biais d'expériences de flexion mécanique. Grâce à l'outil de calcul de mobilité Kubo-Greenwood (couplé à une résolution autocohérente des équations de k.p Schrödinger à 6 bandes et de Poisson) développé dans cette thèse, les tendances observées sont expliquées par les forts couplages existants entre les effets de contrainte et de confinement des trous.

The continuous and aggressive dimensional miniaturization ofthe conventional complementary-metal-oxide semiconductor (CMOS)architecture has been the main impetus for the vast growth ofIC industry over the past decades. As the CMOS downscalingapproaches the fundamental limits, unconventional materials andnovel device architectures are required in order to guaranteethe ultimate scaling in device dimensions and maintain theperformance gain expected from the scaling. This thesisinvestigates both unconventional materials for the gate stackand the channel and a novel notched-gate device architecture,with the emphasis on the challenging issues in processintegration. High-κ gate dielectrics will become indispensable forCMOS technology beyond the 65-nm technology node in order toachieve a small equivalent oxide thickness (EOT) whilemaintaining a low gate leakage current. HfO2and Al2O3as well as their mixtures are investigated assubstitutes for the traditionally used SiO2in our MOS transistors. These high-κ filmsare deposited by means of atomic layer deposition (ALD) for anexcellent control of film composition, thickness, uniformityand conformality. Surface treatments prior to ALD are found tohave a crucial influence on the growth of the high-κdielectrics and the performance of the resultant transistors.Alternative gate materials such as TiN and poly-SiGe are alsostudied. The challenging issues encountered in processintegration of the TiN or poly-SiGe with the high-k are furtherelaborated. Transistors with TiN or poly-SiGe/high-k gate stackare successfully fabricated and characterized. Furthermore,proof-of-concept strained-SiGe surface-channel pMOSFETs withALD high-κ dielectrics are demonstrated. The pMOSFETs witha strained SiGe channel exhibit a higher hole mobility than theuniversal hole mobility in Si. A new procedure for extractionof carrier mobility in the presence of a high density ofinterface states found in MOSFETs with high-κ dielectricsis developed. A notched-gate architecture aiming at reducing the parasiticcapacitance of a MOSFET is studied. The notched gate is usuallyreferred to as a local thickness increase of the gatedielectric at the feet of the gate above the source/drainextensions. Two-dimensional simulations are carried out toinvestigate the influence of the notched gate on the static anddynamic characteristics of MOSFETs. MOSFETs with optimizednotch profile exhibit a substantial enhancement in the dynamiccharacteristics with a negligible effect on the staticcharacteristics. Notched-gate MOSFETs are also experimentallyimplemented with the integration of a high-κ gatedielectric and a poly-SiGe/TiN bi-layer gate electrode. Key words:CMOS technology, MOSFET, high-κ, gatedielectric, ALD, surface pre-treatment, metal gate, poly-SiGe,strained SiGe, surface-channel, buried-channel, notchedgate.

The steady and aggressive downscaling of the physical dimensions of the conventional metal-oxide-semiconductor field-effect-transistor (MOSFET) has been the main driving force for the IC industry and information technology over the past decades. As the device dimensions approach the fundamental limits, novel double/trigate device architecture such as FinFET is needed to guarantee the ultimate downscaling. Furthermore, Schottky barrier source/drain technology presents a promising solution to reducing the parasitic source/drain resistance in the FinFET. The ultimate goal of this thesis is to integrate Schottky barrier source/drain in FinFETs, with an emphasis on process development and integration towards competitive devices. First, a robust sidewall transfer lithography (STL) technology is developed for mass fabrication of Si-nanowires in a controllable manner. A scalable self-aligned silicide (SALICIDE) process for Pt-silicides is also developed. Directly accessible and uniform NWs of Ni- and Pt-silicides are routinely fabricated by combining STL and SALICIDE. The silicide NWs are characterized by resistivity values comparable to those of their thin–film counterparts. Second, a systematic experimental study is performed for dopant segregation (DS) at the PtSi/Si and NiSi/Si interfaces in order to modulate the effective SBHs needed for competitive FinFETs. Two complementary schemes SIDS (silicidation induced dopant segregation) and SADS (silicide as diffusion source) are compared, and both yield substantial SBH modifications for both polarities of Schottky diodes (i.e. φbn and φbp). Third, Schottky barrier source/drain MOSFETs are fabricated in UTB-SOI. With PtSi that is usually used as the Schottky barrier source/drain for p-channel SB-MOSFETs, DS with appropriate dopants leads to excellent performance for both types of SBMOSFETs. However, a large variation in position of the PtSi/Si interface with reference to the gate edge (i.e., underlap) along the gate width is evidenced by TEM. Finally, integration of PtSi NWs in FinFETs is carried out by combining the STL technology, the Pt-SALICIDE process and the DS technology, all developed during the course of this thesis work. The performance of the p-channel FinFETs is improved by DS with B, confirming the SB-FinFET concept despite device performance fluctuations mostly likely due to the presence of the PtSi-to-gate underlap. / QC 20100923