Este trabalho propõe uma estratégia para projeto de circuitos VLSI operando em amplo ajuste de tensão e frequência (VFS), desde o regime em Near-threshold, onde uma tensão de VDD caracteriza-se por permitir o funcionamento do circuito com o mínimo dispêndio de energia por operação (MEP), até tensões nominais, dependendo da carga de trabalho exigida pela aplicação. Nesta dissertação é proposto o dimensionamento de transistores para três bibliotecas de células utilizando MOSFETs com tensões de limiar distintas: Regular-VT (RVT), High-VT (HVT) e Low-VT (LVT). Tais bibliotecas possuem cinco células combinacionais: INV, NAND, NOR, OAI21 e AOI22 em múltiplos strengths. A regra para dimensionamento dos transistores das células lógicas foi adaptada de trabalhos relacionados, e fundamenta-se na equalização dos tempos de subida e descida na saída de cada célula, objetivando à redução dos efeitos de variabilidade em baixas tensões de operação. Dois registradores também foram incluídos na biblioteca RVT e sua caracterização foi realizada considerando os parâmetros de processo CMOS 65 nm typical, fast e slow; nas temperaturas de operação de -40°C, 25°C e 125°C, e para tensões variando de 200 mV até 1,2V, para incluir a região de interesse, próxima ao MEP. Os experimentos foram realizados utilizando dez circuitos VLSI de teste: filtro digital notch, um núcleo compatível com o micro-controlador 8051, quatro circuitos combinacionais e quatro sequenciais do benchmark ISCAS. Em termos de economia de energia, operar no MEP resulta em uma redução média de 54,46% em relação ao regime de sub-limiar e até 99,01% quando comparado com a tensão nominal, para a temperatura de 25°C e processo típico. Em relação ao desempenho, operar em regime de VFS muito amplo propicia frequências máximas que variam de centenas de kHz até a faixa de centenas de MHz a GHz, para as temperaturas de -40°C e 25°C, e de MHz até GHz em 125°C. Os resultados desta dissertação, quando comparados a trabalhos relacionados, demonstraram, em média, redução de energia e ganho de desempenho de 24,1% e 152,68%, respectivamente, considerando os mesmos circuitos de teste, operando no ponto de mínima energia (MEP). / This work proposes a strategy for designing VLSI circuits to operate in a very-wide Voltage-Frequency Scaling (VFS) range , from the supply voltage at which the minimum energy per operation (MEP) is achieved, at the Near-Threshold regime, up to the nominal supply voltage for the processes, if so demanded by applications workload. This master thesis proposes the sizing of transistors for three library cells using MOSFETs with different threshold voltages: Regular-VT (RVT), High-VT (HVT), and Low-VT (LVT). These libraries have five combinational cells: INV, NAND, NOR, OAI21, and AOI22 with multiple strengths. The sizing rule for the transistors of the digital cells was an adapted version from related works and it is directly driven by requiring equal rise and fall times at the output for each cell in order to attenuate variability effects in the low supply voltage regime. Two registers were also included in the RVT library cell. This library cell was characterized for typical, fast, and slow processes conditions of a CMOS 65nm technology; for operation at -40ºC, 25ºC, and 125ºC temperatures, and for supply voltages varying from 200 mV up to 1.2V, to include the region of interest, for VDD near the MEP. Experiments were performed with ten VLSI circuit benchmarks: notch filter, 8051 compatible core, four combinational and four sequential ISCAS benchmark circuits. From the energy savings point of view, to operate in MEP results on average reduction of 54.46% and 99.01% when compared with the sub-threshold and nominal supply voltages, respectively. This analysis was performed for 25⁰C and typical process. When considered the performance, the very-wide VFS regime enables maximum operating frequencies varying from hundreds of kHz up to MHz/GHz at -40ºC and 25ºC, and from MHz up to GHz at 125ºC. This master thesis results, when compared with related works, showed on average an energy reduction and performance gain of 24.1% and 152.68%, respectively, for the same circuit benchmarks operating with VDD at the minimum energy point (MEP).

Em nossos dias a crescente busca por portabilidade e desempenho resulta em esforços focados na maximização da duração de bateria dos equipamentos em fabricação, ou seja, busca-se a conflitante solução de circuitos com baixo consumo e ao mesmo tempo com alto desempenho. Neste contexto usualmente na composição de equipamentos portáteis empregam-se SOC´s (Systems On Chip) o que barateia o custo de produção e integração destes circuitos. SOC´s são sistemas completos que executam uma determinada função integrados em uma pastilha de silício única, normalmente possuem memórias SRAM como componente do sistema, que são utilizadas como memórias de alta performance e baixa latência e/ou também como caches. O grande desafio de projeto em memórias SRAMS é a relação de desempenho versus potência consumida a ser otimizada. Basicamente por sua construção estes circuitos apresentam alto consumo de potência, dinâmica e estática, relacionada a primeira diretamente ao aumento de freqüência de operação. Um dos focos desta dissertação é explorar soluções para a redução de consumo de energia tanto dinâmica como estática, sendo a redução de consumo estático de células de memória em standby buscando desempenho, estabilidade e baixo consumo de energia. No desenvolvimento de técnicas para projeto de circuitos analógicos em tecnologias nanométricas, os TST´s (T-Shaped Transistors – Transistor tipo T) surgem como dispositivos com características potenciais para projeto analógico de baixa potência. TSTs / TATs (Trapezoidal Associations of Transistors – Associação Trapezoidal de transistores) são estruturas self-cascode que podem tornar-se uma boa escolha por apresentar redução do leakage, redução na área utilizada e com incremento na regularidade do layout e no casamento entre transistores, propriedade importantíssima para circuitos analógicos. Sendo este o segundo foco deste texto através do estudo e análise das medidas elétricas dos TSTs executadas para comprovação das características destes dispositivos. Também apresenta-se uma análise das possibilidades de utilização dos TSTs em projeto analógico para tecnologias nanométricas. / Nowadays the increasing needs for portability and performance has resulted in efforts to increase battery life, i. e., the conflicting demands for low power consumption and high performance circuits. In this context using SOC´s (System On Chip) in the development for portable equipments composition, an integration of an entire system for a given function in a single silicon die will provide less production costs and less integration costs. SOC´s normally include a SRAM memory as its building block and are used to achieve memories with low latency and short access time or (and) as caches. A performance versus power consumption analysis of SRAM memory building blocks shows a great challenge to be solved. The electrical design aspects of these blocks reveal high power consumption, dynamic and static, and the former is directly proportional to the operating frequency. The design space exploration for dynamic and leakage consumption reduction in these circuits is one of the focus of this work. The main contribution of this topic is the leakage reduction techniques based in performance, stability and low energy consumption for the memory cell stand-by mode. Among the electrical techniques developed for analog circuits at the 20-100 nanometer scale, the TST (T-Shaped Transistors) rises with potential characteristics for analog low power design. TST /TAT (Trapezoidal Associations of Transistors) are selfcascode structures and can be turning into a good alternative for leakage and area reduction. Another point is the increment in mismatch and layout regularity, all these characteristics being very important in analog designs. The TST electrical measurements study and analysis are developed to show the device properties. An analysis of the TST desired properties and extrapolation for nanometer technologies analog design are also presented.

Após quatro décadas de sucesso do SiO2 (e SiOxNy), as novas gerações de Transistores de Efeito de Campo Metal-Óxido-Semicondutor utilizarão dielétricos de porta de materiais alternativos, dentre os quais se destacam o óxido (HfO2) e os silicatos de háfnio (HfSixOy). Para implementar esses novos dielétricos, é crucial controlar seus defeitos, em particular aqueles relacionados a hidrogênio, que é um elemento químico onipresente e que influencia as características elétricas dos transistores. Nesse contexto, esta Tese investiga a físico-química do hidrogênio em filmes de HfO2 e HfSixOy (2,5–73 nm) depositados sobre silício. Tratamentos térmicos, substituição isotópica, Análise por Reação Nuclear e Espectroscopia de Fotoelétrons Induzidos por Raios-X são algumas das técnicas que foram utilizadas. Observouse que as superfícies dos filmes de HfO2 são particularmente reativas, incorporando H com tratamentos em H2 a 400–600 °C e formando hidroxilas de superfície por exposição a vapor de água à temperatura ambiente. Além disso, no volume dos filmes de HfO2 e HfSixOy foram detectados 1021–1022 H cm-3 (comparados a 1018–1019 H cm-3 no volume de SiO2 crescido sobre Si) cujas origens são os precursores metalorgânicos das deposições por vapor químico, H residual da deposição por sputtering ou absorção de vapor de água. Pelo menos parte desse H no volume do HfO2 e do HfSixOy foi atribuída a hidroxilas, que são parcialmente removidas com tratamento em H2 a 500–600 °C. No caso particular das interações com vapor de água, observou-se que espécies derivadas da água difundem através do HfO2 a temperatura ambiente. Absorção de água no volume dos filmes só foi observada para HfO2 com regiões amorfas ou para HfO2 cristalizado do qual O fora previamente removido. Além disso, em filmes de HfSixOy, foi estabelecida uma relação entre incorporação de H e pré-existência de deficiência de O. Essa relação também foi explorada por cálculos de primeiros princípios, os quais mostraram que vacâncias de O em HfSixOy capturam átomos de H exotermicamente, embasando a relação entre incorporação de H e deficiência de O que fora observada experimentalmente. / After four successful decades employing SiO2 (and SiOxNy), new generations of Metal- Oxide-Semiconductor Field-Effect Transistors will employ gate dielectrics of alternative materials, among which hafnium oxide (HfO2) and hafnium silicates (HfSixOy) are prominent. In order to implement these novel gate dielectrics, it is crucial to control their defects, particularly those related to hydrogen, which is a ubiquitous chemical element and influences the transistors electrical characteristics. In this scenario, this Thesis investigates the physical chemistry of hydrogen in HfO2 and HfSixOy films (2.5–73 nm thick) deposited on silicon. Thermal treatments, isotopic substitution, Nuclear Reaction Analysis, and X-Ray Photoelectron Spectroscopy are a few techniques that were employed. It was observed that HfO2 film surfaces are particularly reactive, incorporating H by annealing in H2 at 400– 600 °C and forming surface hydroxyls by exposing to water vapor at room temperature. Moreover, 1021–1022 H cm-3 were detected in bulk regions of the HfO2 and HfSixOy films (compared with 1018–1019 H cm-3 in bulk regions of SiO2 grown on Si). The origins of this H are the metalorganic precursors from the chemical vapor depositions, residual H from the sputtering deposition, or water vapor absorption. At least part of this H in bulk regions of HfO2 and HfSixOy was assigned to hydroxyls, which are partially removed by annealing in H2 at 500–600 °C. Particularly in the case of water vapor interactions, it was observed that waterderived species diffuse through HfO2 at room temperature. Water absorption in bulk regions of the films was only observed for HfO2 with amorphous regions or for crystallized HfO2 from where O had been previously removed. In addition, in HfSixOy films a relation between H incorporation and pre-existent O deficiency was established. This relation was further explored by first-principles calculations, which showed that oxygen vacancies in HfSixOy exothermically trap H atoms, supporting the relation between H incorporation and O deficiency that had been experimentally observed.

As estruturas metal-óxido-semicondutor (MOS) são o coração dos transistores de efeito de campo. O estudo e caracterização físico-química desses dispositivos foram a chave para o avanço da tecnologia do Si na indústria microeletrônica. Hoje, a ciência busca novos materiais para a produção de dispositivos de alta mobilidade. Um dos materiais visados é o Ge, pois apresenta mobilidade de cargas superior ao Si (duas vezes para elétrons e quatro vezes para lacunas). Porém, a interface Ge/GeO2 é de natureza reativa, limitando seu uso na construção de tais dispositivos. Muitos esforços têm sido feitos para superar as limitações. Entre eles, encontram-se a passivação da superfície do Ge a partir de solução aquosa de (NH4)2S, previamente a deposição do dielétrico. Outra etapa do processamento desse material na indústria a ser investigada são os tratamentos térmicos posteriores à deposição: a caracterização de estruturas MOS de Pt/HfO2/Ge submetidas a tratamentos térmicos levaram a melhoria das propriedades elétricas. Nesse sentido, o trabalho tem como objetivos investigar o papel da passivação sulfídrica em estruturas dielétrico/Ge e a influência do eletrodo de Pt nas estruturas Pt/HfO2/Ge quando submetidas a tratamentos térmicos. / The heart of field effect transistors is the metal-oxide-semiconductor (MOS) structure. Physico-chemical characterization of the materials employed in such structures enabled the development of Si technology. Nowadays, in order to build high mobility devices, new material are needed. Ge is an alternative material, since its carrier mobilities are higher than those of Si (almost two times for electrons and four times higher for holes). However, the GeO2/Ge interface is not thermally stable, which is a problem for its use on electronic devices. Many attempts to enhance this stability were already investigated. Among them, sulfur passivation of the Ge surface was employed using (NH4)2S aqueous solution prior to the deposition of dielectric layers. Another important step in the fabrication of MOS structures is post-deposition annealing. Pt/HfO2/Ge MOS structures presented improved electrical characteristics following post deposition annealing. The main objectives of this work are to investigate the role of sulfur passivation on dielectric/Ge structures and the influence of Pt electrode in Pt/HfO2/Ge structures submitted to post deposition annealing.

abstract: In recent years, the Silicon Super-Junction (SJ) power metal-oxide semiconductor field-effect transistor (MOSFET), has garnered significant interest from spacecraft designers. This is due to their high breakdown voltage and low specific on-state resistance characteristics. Most of the previous research work on power MOSFETS for space applications concentrated on improving the radiation tolerance of low to medium voltage (~ 300V) power MOSFETs. Therefore, understanding and improving the reliability of high voltage SJMOS for the harsh space radiation environment is an important endeavor.In this work, a 600V commercially available silicon planar gate SJMOS is used to study the SJ technology’s tolerance against total ionizing dose (TID) and destructive single event effects (SEE), such as, single event burnout (SEB) and single event gate rupture (SEGR). A technology computer aided design (TCAD) software tool is used to design the SJMOS and simulate its electrical characteristics. Electrical characterization of SJMOS devices showed substantial decrease in threshold voltage and increase in leakage current due to TID. Therefore, as a solution to improve the TID tolerance, metal-nitride-oxide-semiconductor (MNOS) capacitors with different oxide/nitride thickness combinations were fabricated and irradiated using a Co-60 gamma-source. Electrical characterization showed all samples with oxide/nitride stack gate insulators exhibited significantly higher tolerance to irradiation when compared to metal-oxide-semiconductor capacitors. Heavy ion testing of the SJMOS showed the device failed due to SEB and SEGR at 10% of maximum rated bias values. In this work, a 600V SJMOS structure is designed that is tolerant to both SEB and SEGR. In a SJMOS with planar gate, reducing the neck width improves the tolerance to SEGR but significantly changes the device electrical characteristics. The trench gate SJ device design is shown to overcome this problem. A buffer layer and larger P+-plug are added to the trench gate SJ power transistor to improve SEB tolerance. Using TCAD simulations, the proposed trench gate structure and the tested planar gate SJMOS are compared. The simulation results showed that the SEB and SEGR hardness in the proposed structure has improved by a factor of 10 and passes at the device’s maximum rated bias value with improved electrical performance. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2020

This master thesis deals with the problematics of CT filters and focuses on Gm – C filter. Three linearisation techniques are listed and compared in terms of linear input range, distortion and retuning. In the practical part – second - order low – pass filter is designed and its tuning capabilities are examined.

This thesis studies the options of using PCB embedding bare die power MOSFET and new packaging of MOSFET to increase the power density in a PCB. This is to decrease the winding losses in an isolated DC/DC converter which, according to "Flex Power Modules", can be done by improving the interleaving between the layers of the transformer and/or decreasing the AC loop. To test the MOSFET packaging two layout are made from a reference PCB, one using embedded MOSFET and the other using the new packaging. The leakage induction and winding losses are simulated and if they are lower compared to the reference PCB prototypes are manufactured. The simulated result is that PCB embedded MOSFET decrease the leakage induction but the winding loss is higher. With the new packaging the leakage induction is higher and the winding loss has linear characteristics. Only the PCB with the new MOSFET packaging is made because the MOSFET die gate pad is too small for the PCB manufacturer to make a via connection to it. The PCB is tested that it operates as a DC/DC converter with a 40-60 V input and a 12 V output. The PCB is put on a test board in a wind-tunnel to test its characteristics under different wind speeds, input voltage and loads. The result is that the PCB has a higher efficiency than the reference PCB but it has worse thermal resistance. Further development of the design needs to be made to improve the thermal resistance. Using new packaging is a way to continue the development of power converter with lower efficiency but embedding MOSFET needs a less complicated manufacturing process before there is any widespread usage.

No description available.

Long-term hot-carrier induced degradation of MOS devices has become more severe as the device size continues to scale down to submicron range. In our work, a simple yet effective method has been developed to provide the degradation laws with a better predictability. The method can be easily augmented into any of the existing degradation laws without requiring additional algorithm. With more accurate extrapolation method, we present a direct and accurate approach to modeling empirically the 0.18-ìm MOS reliability, which can predict the MOS lifetime as a function of drain voltage and channel length. With the further study on physical mechanism of MOS device degradation, experimental results indicated that the widely used power-law model for lifetime estimation is inaccurate for deep submicron devices. A better lifetime prediction method is proposed for the deep-submicron devices. We also develop a Spice-like reliability model for advanced radio frequency RF MOS devices and implement our reliability model into SpectreRF circuit simulator via Verilog-A HDL (Hardware Description Language). This RF reliability model can be conveniently used to simulate RF circuit performance degradation

Galactic-cosmic-rays (GCR) exist in space from unknown origins. A cosmic ray is a very high energy electron, proton, or heavy ion. As a GCR transverses a power semiconductor device, electron-hole-pairs (ehps) are generated along the ion track. Effects from this are referred to as single-event-effects (SEEs). A subset of a SEE is single-event burnout (SEB) which occurs when the parasitic bipolar junction transistor is triggered leading to thermal runaway. The failure mechanism is a complicated mix of photo-generated current, avalanche generated current, and activation of the inherent parasitic bipolar transistor. Current space-borne power systems lack the utility and advantages of terrestrial power systems. Vertical-double-diffused MOSFETs (VDMOS) is by far the most common power semiconductor device and are very susceptible to SEEs by their vertical structure. Modern space power switches typically require system designers to de-rate the power semiconductor switching device to account for this. Consequently, the power system suffers from increased size, cost, and decreased performance. Their switching speed is limited due to their vertical structure and cannot be used for MHz frequency applications limiting the use of modern digital electronics for space missions. Thus, the Power Semiconductor Research Laboratory at the University of Central Florida in conjunction with Sandia National Laboratories is developing a rad-hard by design lateral-double-diffused MOSFET (LDMOS). The study provides a novel in-depth physical analysis of the mechanisms that cause the LDMOS to burnout during an SEE and provides guidelines for making the LDMOS rad-hard to SEB. Total dose radiation, another important radiation effect, can cause threshold voltage shifts but is beyond the scope of this study. The devices presented have been fabricated with a known total dose radiation hard CMOS process. Single-event burnout data from simulations and experiments are presented in the study to prove the viability of using the LDMOS to replace the VDMOS for space power systems. The LDMOS is capable of higher switching speeds due to a reduced drain-gate feedback capacitance (Miller Capacitor). Since the device is lateral it is compatible with complimentary-metal-oxide-semiconductor (CMOS) processes, lowering developing time and fabrication costs. High switching frequencies permit the use of high density point-of-load conversion and provide a fast dynamic response.