We report and discuss the performance of an enhancement mode n-channel pseudo-vertical GaN metal oxide semiconductor field effect transistor (MOSFET). The trench gate structure of the MOSFET is uniformly covered with an Al₂O₃ dielectric and TiN electrode material, both deposited by atomic layer deposition (ALD). Normally-off device operation is demonstrated in the transfer characteristics. Special attention is given to the estimation of the active acceptor concentration in the Mg doped body layer of the device, which is crucial for the prediction of the threshold voltage in terms of device design. A method to estimate the electrically active dopant concentration by applying a body bias is presented. The method can be used for both pseudo-vertical and truly vertical devices. Since it does not depend on fixed charges near the channel region, this method is advantageous compared to the estimation of the active doping concentration from the absolute value of the threshold voltage.

Heteroepitaxial SiGe(C) layers have attracted immense attention as a material for performance boost in state of the art electronic devices during recent years. Alloying silicon with germanium and carbon add exclusive opportunities for strain and bandgap engineering. This work presents details of epitaxial growth using chemical vapor deposition (CVD), material characterization and integration of SiGeC layers in MOS devices. Non-selective and selective epitaxial growth of Si1-x-yGexCy (0≤x≤0.30, 0≤y≤0.02) layers have been performed and optimized aimed for various metal oxide semiconductor field effect transistor (MOSFET) applications. A comprehensive experimental study was performed to investigate the growth of SiGeC layers. The incorporation of C into the SiGe matrix was shown to be strongly sensitive to the growth parameters. As a consequence, a much smaller epitaxial process window compared to SiGe epitaxy was obtained. Incorporation of high boron concentrations (up to 1×1021 atoms/cm3) in SiGe layers aimed for recessed and/or elevated source/drain (S/D) junctions in pMOSFETs was also studied. HCl was used as Si etchant in the CVD reactor to create the recesses which was followed (in a single run) by selective epitaxy of B-doped SiGe. The issue of pattern dependency behavior of selective epitaxial growth was studied in detail. It was shown that a complete removal of pattern dependency in selective SiGe growth using reduced pressure CVD is not likely. However, it was shown that the pattern dependency can be predicted since it is highly dependent on the local Si coverage of the substrate. The pattern dependency was most sensitive for Si coverage in the range 1-10%. In this range drastic changes in growth rate and composition was observed. The pattern dependency was explained by gas depletion inside the low velocity boundary layer. Ni silicide is commonly used to reduce access resistance in S/D and gate areas of MOSFET devices. Therefore, the effect of carbon and germanium on the formation of NiSiGe(C) was studied. An improved thermal stability of Ni silicide was obtained when C is present in the SiGe layer. Integration of SiGe(C) layers in various MOSFET devices was performed. In order to perform a relevant device research the dimensions of the investigated devices have to be in-line with the current technology nodes. A robust spacer gate technology was developed which enabled stable processing of transistors with gate lengths down to 45 nm. SiGe(C) channels in ultra thin body (UTB) silicon on insulator (SOI) MOSFETs, with excellent performance down to 100 nm gate length was demonstrated. The integration of C in the channel of a MOSFET is interesting for future generations of ultra scaled devices where issues such as short channel effects (SCE), temperature budget, dopant diffusion and mobility will be extremely critical. A clear performance enhancement was obtained for both SiGe and SiGeC channels, which point out the potential of SiGe or SiGeC materials for UTB SOI devices. Biaxially strained-Si (sSi) on SiGe virtual substrates (VS) as mobility boosters in nMOSFETs with gate length down to 80 nm was demonstrated. This concept was thoroughly investigated in terms of performance and leakage of the devices. In-situ doping of the relaxed SiGe was shown to be superior over implantation to suppress the junction leakage. A high channel doping could effectively suppress the source to drain leakage. / <p>QC 20100715</p>

La réduction (" scaling ") continue des dimensions des transistors MOSFET nous a conduits à l'ère de la nanoélectronique. Le transistor à effet de champ multi-grilles (MultiGate FET, MuGFET) avec l'architecture "nanofil canal" est considéré comme un candidat possible pour le scaling des MOSFET jusqu'à la fin de la roadmap. Parallèlement au scaling des CMOS classiques ou scaling suivant la loi de Moore, de nombreuses propositions de nouveaux dispositifs, exploitant des phénomènes nanométriques, ont été faites. Ainsi, le transistor monoélectronique (SET), utilisant le phénomène de "blocage de Coulomb", et le transistor à atome unique (SAT), en tant que transistors de dimensions ultimes, sont les premiers dispositifs nanoélectroniques visant de nouvelles applications comme la logique à valeurs multiples ou l'informatique quantique. Bien que le SET a été initialement proposé comme un substitut au CMOS ("Au-delà du dispositif CMOS"), il est maintenant largement considéré comme un complément à la technologie CMOS permettant de nouveaux circuits fonctionnels. Toutefois, la faible température de fonctionnement et la fabrication incompatible avec le procédé CMOS ont été des contraintes majeures pour l'intégration SET avec la technologie FET industrielle. Cette thèse répond à ce problème en combinant les technologies CMOS de dimensions réduites, SET et SAT par le biais d'un schéma d'intégration unique afin de fabriquer des transistors " Trigate " nanofil. Dans ce travail, pour la première fois, un SET fonctionnant à température ambiante et fabriqués à partir de technologies CMOS SOI à l'état de l'art (incluant high-k/grille métallique) est démontré. Le fonctionnement à température ambiante du SET nécessite une île (ou canal) de dimensions inférieures à 5 nm. Ce résultat est obtenu grâce à la réduction du canal nanofil ''trigate'' à environ 5 nm de largeur. Une étude plus approfondie des mécanismes de transport mis en jeu dans le dispositif est réalisée au moyen de mesures cryogéniques de conductance. Des simulations NEGF tridimensionnelles sont également utilisées pour optimiser la conception du SET. De plus, la cointégration sur la même puce de MOSFET FDSOI et SET est réalisée. Des circuits hybrides SET-FET fonctionnant à température ambiante et permettant l'amplification du courant SET jusque dans la gamme des milliampères (appelé "dispositif SETMOS" dans la littérature) sont démontrés de même que de la résistance différentielle négative (NDR) et de la logique à valeurs multiples. Parallèlement, sur la même technologie, un transistor à atome unique fonctionnant à température cryogénique est également démontré. Ceci est obtenu par la réduction de la longueur de canal MOSFET à environ 10 nm, si bien qu'il ne comporte plus qu'un seul atome de dopant dans le canal (diffusée à partir de la source ou de drain). A basse température, le transport d'électrons à travers l'état d'énergie de ce dopant unique est étudié. Ces dispositifs fonctionnent également comme MOSFET à température ambiante. Par conséquent, une nouvelle méthode d'analyse est développée en corrélation avec des caractéristiques à 300K et des mesures cryogéniques pour comprendre l'impact du dopant unique sur l'échelle MOSFET à température ambiante.

Apresentamos mecanismos de formação e de degradação térmica de filmes fi- nos (espessura da ordem de 10 nm) de diferentes dielétricos sobre substrato de silício monocristalino. Tendo em vista a aplicação dessas estruturas em MOSFETs (transistores de efeito de campo metal-óxido-semicondutor), estudamos o consagrado óxido de silício (SiO2), os atuais substitutos oxinitretos de silício (SiOxNy) e o possível substituto futuro óxido de alumínio (Al2O3). Nossos resultados experimentais baseiam-se em técnicas preparativas de substituição isotópica e de caracterização física com feixes de íons (análise com reações nucleares) ou raios- X (espectroscopia de fotoelétrons). Observamos que: (a) átomos de silício não apresentam difusão de longo alcance (além de ~ 2 nm) durante o crescimento de SiO2 por oxidação térmica do silício em O2; (b) nitretação hipertérmica é capaz de produzir filmes finos de oxinitreto de silício com até dez vezes mais nitrogênio que o resultante do processamento térmico usual, sendo que esse nitrogênio tende a se acumular na interface SiOxNy/Si; e (c) átomos de oxigênio, alumínio e silício migram e promovem reações químicas durante o recozimento térmico de estruturas Al2O3/SiO2/Si em presença de O2. Desenvolvemos um modelo de difusão-reação que poderá vir a permitir o estabelecimento de condições ótimas de processamento térmico para filmes finos de Al2O3 sobre silício a serem empregados na fabricação de MOSFETs. / We present mechanisms of formation and thermal degradation of thin films (thickness about 10 nm) of different dielectrics on monocrystalline silicon substrate. Having in sight the application of such structures in MOSFETs (metal-oxidesemiconductor field effect transistors), we studied the standard silicon oxide (SiO2 ), its current substitutes silicon oxynitrides (SiO xNy) and the possible future substitute aluminum oxide (Al 203 ). The experimental results in this thesis are based on preparation techniques involving isotopic substitution and on physical characterization with ion beams (nuclear reaction analysis) or X-rays (photoelectron spectroscopy). We have observed that: (a) silicon atoms do not present long range diffusion (more than 2 nm) during the growth of SiO 2 by thermal oxidation of silicon in 02 ; (b) hyperthermal nitridation can yield silicon oxynitride thin films with up to ten times more nitrogen than the resulting from conventional thermal processing, and this nitrogen tends to accumulate at the SiO xNy/Si interface (c) oxygen, aluminum, and silicon atoms migrate and promote chemical reactions during thermal annealing of Al203/Si02/Si structures in the presence of 02 . A diffusion-reaction model was developed based on these results. In the future, this model may lead to optimal thermal processing conditions for Al 203 films on silicon to be used in MOSFET fabrication.

As estruturas metal-óxido-semicondutor (MOS) são o coração dos transistores de efeito de campo. O estudo e caracterização físico-química desses dispositivos foram a chave para o avanço da tecnologia do Si na indústria microeletrônica. Hoje, a ciência busca novos materiais para a produção de dispositivos de alta mobilidade. Um dos materiais visados é o Ge, pois apresenta mobilidade de cargas superior ao Si (duas vezes para elétrons e quatro vezes para lacunas). Porém, a interface Ge/GeO2 é de natureza reativa, limitando seu uso na construção de tais dispositivos. Muitos esforços têm sido feitos para superar as limitações. Entre eles, encontram-se a passivação da superfície do Ge a partir de solução aquosa de (NH4)2S, previamente a deposição do dielétrico. Outra etapa do processamento desse material na indústria a ser investigada são os tratamentos térmicos posteriores à deposição: a caracterização de estruturas MOS de Pt/HfO2/Ge submetidas a tratamentos térmicos levaram a melhoria das propriedades elétricas. Nesse sentido, o trabalho tem como objetivos investigar o papel da passivação sulfídrica em estruturas dielétrico/Ge e a influência do eletrodo de Pt nas estruturas Pt/HfO2/Ge quando submetidas a tratamentos térmicos. / The heart of field effect transistors is the metal-oxide-semiconductor (MOS) structure. Physico-chemical characterization of the materials employed in such structures enabled the development of Si technology. Nowadays, in order to build high mobility devices, new material are needed. Ge is an alternative material, since its carrier mobilities are higher than those of Si (almost two times for electrons and four times higher for holes). However, the GeO2/Ge interface is not thermally stable, which is a problem for its use on electronic devices. Many attempts to enhance this stability were already investigated. Among them, sulfur passivation of the Ge surface was employed using (NH4)2S aqueous solution prior to the deposition of dielectric layers. Another important step in the fabrication of MOS structures is post-deposition annealing. Pt/HfO2/Ge MOS structures presented improved electrical characteristics following post deposition annealing. The main objectives of this work are to investigate the role of sulfur passivation on dielectric/Ge structures and the influence of Pt electrode in Pt/HfO2/Ge structures submitted to post deposition annealing.

Efeitos causados pela interação da radiação ionizante em dispositivos eletrônicos consis- tem numa preocupação crescente em diversos segmentos, como as aplicações aeroespaci- ais e em física de altas energias. Entre os efeitos de radiação induzidos por íons pesados estão os chamados de Efeitos de Eventos Isolados (Single Event Effects - SEE), em que o impacto de um único íon pode ser capaz de gerar um efeito observável, através da elevada deposição de energia e consequente geração de pares elétron-lacuna. O estudo destes efeitos requer um acelerador de partículas capaz de prover feixes uniformes de íons pesados com baixo fluxo. Neste trabalho, desenvolvemos um sistema para produ- ção de feixes de íons pesados para estudar SEE no Acelerador Pelletron 8UD, utilizando as técnicas de desfocalização e espalhamento múltiplo em folhas de ouro. O sistema foi projetado para prover feixes com intensidades entre 10 2 e 10 5 partículas/s/cm 2 com uniformidade maior que 90% numa área circular de diâmetro de 1,5 cm, operando em regime de alto-vácuo. Um manipulador de amostras permite a movimentação do dispo- sitivo sob teste com precisão de 2,5 m e um sistema de aquisição de dados dedicado foi desenvolvido, permitindo a automação de medidas. O sistema foi caracterizado com feixes de 1 H, 12 C, 16 O, 19 F, 28 Si, 35 Cl e 63 Cu a várias energias, apresentando fluxo e uni- formidade adequados aos experimentos em diversas configurações de focalização e folhas espalhadoras, e tem sido utilizado por diversos grupos de pesquisa. O novo sistema foi utilizado para estudar o efeito das camadas de isolamento e metalização na coleta de carga e geração de eventos observáveis em um dispositivo analógico e em um disposi- tivo digital, de modo a estabelecer metodologias de trabalho adequadas para estudos precisos de mecanismos de ocorrência de efeitos de radiação. O dispositivo analógico estudado foi um transistor p-MOS, onde o sinal de corrente induzido pelo impacto de íons diversos foi analisado de modo a obter a seção de choque de eventos e a cargaix gerada, permitindo determinar a espessura da camada de metalização em 1,28(2) m, e a camada de coleta de carga dependente do LET e alcance da partícula incidente, variando entre 6,0 e 11,0 m. O dispositivo digital estudado foi uma memória SRAM 28nm, onde foi observada uma forte dependência da seção de choque de eventos com a penetração do feixe no dispositivo. Associando as camadas de metalização e isolamento a um meio efetivo de interação, obteve-se que toda a área sensível do dispositivo só pode ser excitada, isto é, nela ocorrerem eventos observáveis, para partículas com alcance, no meio efetivo, entre 14 e 20 m, embora partículas com alcance de até 10 m sejam capazes de sensibilizar até 50% da área ativa do dispositivo. / Effects on electronic devices caused by interactions of ionizing radiation are a main concern in several fields, such as aerospace applications and high-energy physics. Among the heavy-ion induced radiation effects are the Single Event Effects, in which a strike of a single ion can be enough to generate an observable effect, as a result of the high energy deposition and thus electron-hole pairs generation. The study of these effects requires the use of uniform, low-flux particle beams. In this work, we developed a system for production of heavy ion beams for SEE studies at Pelletron 8UD accelerator, through the defocusing and multiple scattering in gold foil techniques. The setup can provide ion beams with intensities ranging from 10 2 e 10 5 particles/s/cm 2 with uniformity better than 90% in an circular area of 1.5 cm diameter, operating under high-vacuum. A sample manipulador allows device under test positioning with a precision of 2.5 m, and a dedicated data acquisition system was developed, allowing measurement automation. The system was characterized with 1 H, 12 C, 16 O, 19 F, 28 Si, 35 Cl and 63 Cu ion beams at several energies, presenting flux and uniformity adequate for SEE studies in many different configurations, and it is being used by several research groups. The new facility was used to study the effect of isolation and metalization layers in charge collection and observable events generation in an analog and in a digital device, in order to establish proper metodologies for precise studies of radiation effects mecanisms. The analog device studied was a p-MOS transitor, from which the heavy-ion impact induced current signal was analised to obtain cross-section and colected charge, allowing to determine metalization layer thickness to be 1.28(2) m, and charge collection dependency on particle LET and range, varying from 6.0 to 11.0 m. The digital device studied was a 28nm SRAM memory, where a strong dependency of cross-section with particle range in the device was observed. Associating to the metal and insulating layers an effectivexi medium, it was observed that the complete sensitive area can be excited only by particle with ranges in effective medium between 14 and 20 m, although particles with ranges up to 10 m are capable of sensibilizing up to 50% of devices active area.

This thesis consists of three main parts, starting with the use of improved nitridation processes to grow acceptable quality gate oxides on silicon carbide (SiC)[1]–[7], to the comprehensive investigation of basic electron-hole generation process in 4H SiC-based metal–oxide–semiconductor (MOS) capacitors [8], [9], and concluding with the experimental demonstration and analysis of nonvolatile characteristics of 4H SiC-based memory devices [10]–[15]. In the first part of the thesis, two improved versions of nitridation techniques have been introduced to alleviate oxide-growth rate and toxicity problems. Using a combination of nitridation and oxidation processes, a sandwich technique (nitridation–oxidation–nitridation) has been proposed and verified to solve the lengthy and expensive oxide-growing process in direct nitric oxide (NO) gas [1]. The nitrogen source from the toxic-NO gas has been replaced by using a nontoxic nitrous oxide (N2O) gas. The best combination of process parameters in this gas is oxide-growing temperature at 1300oC with 10% N2O [2], [3]. The quality of nitrided gate oxides obtained by this technique is lower than the sandwich technique [6], [13]. Using 4H SiC-based MOS with nitrided gate oxides grown by either of the abovementioned nitridation techniques, the fundamentals of electron-hole generation have been investigated using high-temperature capacitance–transient measurements. The contributions of carrier generation, occurring at room temperature, in the bulk and at the SiC–SiO2 interface are evaluated and compared using a newly developed method [8], [9]. The effective bulk-generation rates are approximately equal for both types of nitrided oxides, whereas the effective surface-generation rates have been shown to exhibit very strong dependencies on the methods of producing the nitrided gate oxide. Based on analysis, the prevailing generation component in a SiC-based MOS capacitor with nitrided gate oxide is at SiC–SiO2 interface located below the gate. Utilizing the understanding of electron-hole generation in SiC, the nonvolatile characteristics of memory device fabricated on SiC have been explored. The potential of developing a SiC-based one-transistor one-capacitor (1T/1C) nonvolatile-dynamic memory (NDM) has been analyzed using SiC-based MOS capacitors as storage elements or test structures. Three possible leakage mechanisms have been evaluated [10]–[16]: (1) leakage via MOS capacitor dielectric, (2) leakage due to electron-hole generation in a depleted MOS capacitor, and (3) junction leakage due to generation current occurred at a reverse-biased pn junction surrounding the drain region of a select metal–oxide– semiconductor field–effect–transistor (MOSFET). Among them, leakage through capacitor oxide remains an important factor that could affect the nonvolatile property in the proposed device, whereas others leakage mechanisms are insignificant. Based on the overall results, the potential of developing a SiC-based 1T/1C NDM is encouraging.

Les composants à grille isolée, omniprésents dans les structures de conversion d'énergie, sont soumis à des exigences de plus en plus poussées : performances électriques, intégrabilité, fiabilité... Nous avons modélisé le comportement électrique dynamique de MOSFETs de puissance à partir de leurs caractéristiques physiques et géométriques. Cette modélisation, validée par la réalisation de prototypes, permet un dimensionnement des besoins énergétiques du composant en commutation, autorisant ainsi l'étude de solutions permettant l'intégration de l'alimentation de l'étage de commande. Deux structures d'auto-alimentation, compatibles avec la filière technologique du composant principal, ont été développées. Enfin, des travaux d'optimisation, portant sur la géométrie du composant, montrent qu'il est possible de dimensionner ce dernier de manière à minimiser ses besoins énergétiques en commutation, perspective intéressante pour l'intégration.

Les structures de conversion d'énergie trouvent de plus en plus leur place dans des produits grand public. Ce marché étant fortement concurrentiel, les efforts des industriels sont concentrés sur la réduction de leurs coûts et l'augmentation de leur fiabilité. Un moyen pour répondre à ces contraintes est l'intégration des structures de conversion d'énergie. Ce mémoire de thèse traite le sujet de l'intégration monolithique des fonctionnalités autour des interrupteurs semi-conducteurs de puissance. L'étude est plus particulièrement portée sur l'intégration de l'alimentation de la commande rapprochée. Deux solutions techniques, distinctes et complémentaires, toutes les deux intégrables, ont été développées. Des méthodes de dimensionnement et de conception sont présentées, tenant compte des conditions et des contraintes technologiques propres aux composants de puissance à structure verticale. La première solution contenant deux composants MOSFETs a été étudiée sur la base de simulations et de réalisations expérimentales. Cette solution a été testée avec des composants discrets et avec les composants réalisés. La seconde solution contient un MOSFET et un JFET. Cette dernière a été présentée et étudiée quasi exclusivement à base de travaux de simulations. Plusieurs "familles" de prototypes ont été conçues, dimensionnées et réalisées avec pour objectif de valider le concept, la démarche de conception, les principes de fonctionnement et "l'intégrabilité" d'une fonction d'auto-alimentation.

Dans les transistors MOS (Métal Oxyde Semiconducteur) fortement submicroniques (<100 nm), l'augmentation de la densité d'intégration des composants s'accompagne d'une dégradation de certaines caractéristiques électriques (effets de canal court), tout particulièrement dans le régime sous le seuil. Parmi les solutions possibles pour atteindre les longueurs de grille de « fin de roadmap », les architectures MOSFET (Transistor à effet de champ de type MOS) à grille multiple sur SOI (Silicium sur Isolant) apparaissent particulièrement séduisantes, surtout en termes de contrôle électrostatique. <br />Grâce au simulateur particulaire MONACO de type Monte Carlo, ce travail commence par analyser la transition apparaissant dans les transistors ultracourts entre un régime de transport diffusif vers un régime de plus en plus balistique. D'après notre étude, les dispositifs ultimes devraient délivrer des courants très proches de la limite balistique.<br />Ensuite, l'optimisation du dimensionnement de tels transistors MOS à grille multiple sur SOI a été étudiée, entre autres pour limiter l'augmentation des impédances parasites. Le meilleur compromis entre comportement sous le seuil acceptable et rapidité est obtenu dans le cas des architectures à double grille.<br />Enfin, une nouvelle version très novatrice du logiciel MONACO développée durant cette thèse est présentée. Par résolution de l'équation de Schrödinger 1D, elle permet la prise en compte des effets de quantification d'énergie qui ont lieu perpendiculairement à la direction du transport de charges 2Dk, c'est à dire selon l'axe des grilles, dans les MOSFET à double grille ultra courts qui sont aussi ultrafins.