Over the past two decades, power consumption has increased exponentially worldwide, posing new challenges to power grids to meet the load requirements. With this growing power demand, the need for efficient high-density medium-voltage (MV) power converters has increased to support flexible power distribution grids. The modular multilevel converters (MMC) became the most typical MV power converters in applications from 2010. This topology has many advantages, such as voltage scalability, excellent output performance, and low voltage ratings for switching devices. However, without the excellent reliability of the MMC, applications cannot reap these benefits. The MMC topology comprises several series-connected submodules (typically a half-bridge or a full-bridge inverter). As a result of increased switching devices, the converter becomes vulnerable since a single device fault can disrupt the whole converter operation. Therefore, fault-tolerant strategies to replace faulty SM with a redundant SM are developed using additional bypass switches. Conventionally TRIACs and vacuum switches are employed as bypass switches that operate in the range of 2-10 microseconds. Despite having performance advantages, MMCs are still not fully employed in aerospace and naval industries due to their enormous size. Many Power Electronics Building Blocks (PEBB) are proposed, with size optimization, as submodules for modular converters. The PEBB1000, a 1000 V- PEBB proposed by Dr. Jun Wang, achieved a significant size reduction of 80% with a novel switching cycle control (SCC) scheme. This novel control scheme requires high switching frequency and high di/dt-currents for MMC operation. Due to di/dt-rate limitations, TRIAC-based switch cannot perform bypass operation. Therefore, research work has been conducted on bypass switches for PEBB1000 using wide-bandgap SiC devices. This thesis presents the design of a SiC MOSFET-based bypass switch for PEBB1000 in MMC application. A detailed fault case analysis is presented to show the feasibility of the bypass operation for 90% PEBB-level faults. Significant variations in PEBB1000 bypass requirements are observed through SCC-based MMC simulations. Accordingly, a 1700 V, 100 A bypass switch has been designed using the anti-series topology of MOSFETs. Various specifications, such as 142 nanoseconds operation time, 500 nanoseconds bypass commutation time, and 277A transient current conduction capability, are validated through practical tests. Results prove that SiC-MOSFETs work better than TRIACs in high di/dt-current conduction and operation times. For future work, false-triggering endurance has to be analyzed for 1000 V switching voltage. / Master of Science / When a building is on fire, the safety of people inside depends on the timely arrival of the fire rescue departments. Similarly, for an electrical fault, the safety of electrical systems depends on fast and secure fault protection devices. This thesis presents work on one such fault-protection device used in the power distribution grid: solid-state bypass switch. Distribution grids supply power majorly to households and industries at the city or state level. They employ medium-voltage (MV) converters to step down the voltages to meet the distribution requirements. In MV converters, several low-voltage modules are connected in series to achieve the high-voltage power conversion. When a fault occurs at one of the low-voltage modules in MV converters, power flow gets disrupted due to a series connection like a chain. Therefore, bypass switches are connected in parallel to low-voltage modules for an alternate power flow path. Conventionally used bypass switches have 2-10 microseconds operation time. Recent advancements in semiconductor devices, SiC MOSFETs, allow operation times less than one microsecond. Therefore, research work has been conducted on bypass switches using SiC MOSFETs. Finally, the SiC-MOSFET based bypass switch is built and tested according to converter requirements. Results proved that the designed switch operates in 142 nanoseconds, ten times faster than a conventional switch.

Numerous power electronics building blocks (PEBB) based power conversion systems have been developed to explore modular design, scalable voltage and current ratings, low-cost operations, etc. This paper further extends the modular concept from the power stage to the control system. The communication network in SiC-based modular power converters is becoming significant for distributed control architecture, with the requirements of tight synchronization and low latency. The influence of the synchronization accuracy on harmonics under the phase-shifted carrier pulse width modulation (PSC-PWM) is evaluated. When the synchronization is accurate, the influence of an increase in harmonics can be ignored. Thus, a synchronous distributed control and communication protocol with well-performed synchronization of 25 ns accuracy is proposed and verified for a 120 kHz SiC-based impedance measurement unit (IMU) with cascaded H-bridge PEBBs. An improved synchronization method with additional analog circuits is further implemented and verified with sub-ns synchronization accuracy. / The power electronics building block (PEBB) concept is proposed for medium-voltage converter applications in order to realize the modular design of the power stage. Traditionally, the central control architecture is popular in converter systems. The voltage and current are sensed and then processed in one central controller. The control hardware interfaces and software have to be customized for a specified number of power cells, and the scalability of controller is lost. In stead, in the distributed control architecture, a local controller in each PEBB can communicate with the sensors, gate drivers, etc. A high-level controller collects the information from each PEBB and conducts the control algorithm. In this way, the design can be more modular, and the local controller can share the computation burden with the high-level controller, which is good for scalability. In such distributed control architecture, a synchronous communication system is required to transmit data and command between the high-level controller and local controllers. A power converter always requires a highly synchronized operation to turn on or turn off the devices. In this work, a synchronous communication protocol is proposed and experimentally validated on a SiC-based modular power converter.

Nowadays, major public concern is concentrated on reducing the usage of fossil fuels and reducing emissions of CO₂ by different energy advancement. Electric vehicle technology presents extremely effective way of reducing carbon emissions and paves the way of having sustainable and renewable energy future. In order to wear the cost of electric vehicles down, batteries have to be improved as well as higher power density and high reliability has to be achieved. This research work mainly focuses on achieving higher power density and higher reliability of the inverter stage by utilizing wide-bandgap SiC MOSFET semiconductor devices in electric vehicle application. In order to achieve higher reliability of the inverter stage, high bandwidth, high performance Rogowski coil switch current sensors are employed. These sensor were embedded on the PCB and integrated on the gate driver. High bandwidth switch current sensor measurement is used for fast short-circuit detection and protection of the SiC MOSFET semiconductor switches. Furthermore, comparison with conventional detection and protection method used in automotive IGBT applications is shown where novel protection showed superior performance. This thesis also shows principle of how to obtain phase currents of the system using Rogowski coil switch current sensor measurements. Digital reconstruction principle is employed to obtain the phase currents. Accurate and linear current sensor is achieved. By successfully realizing this integrated phase current measurement on the gate driver, elimination of the commercial current sensors from the system is possible. By eliminating existing phase current sensors, higher power density could be achieved. Sensor is evaluated in both continuous and discontinuous PWM schemes. / Master of Science / Together with renewable sources, electric vehicle will play an important role as a part of sustainable and renewable energy future by significantly reducing emissions of CO₂ into the atmosphere. In order to make electric cars more acceptable and accessible and make a significant impact on the environment, cost must be lowered down. To wear the cost of the electric vehicles down, powertrain of the car must be significantly improved and made smaller as well as lighter. This thesis mainly focuses on improving the reliability of the motor driving stage by implementing novel protection during fault periods such as short-circuit event. Furthermore, this novel protection allows current sensing that is crucial for motor control during normal operation periods. This will enable more compact motor driving stage since existing current sensing elements can be eliminated.

To support the study of potential utilization of the emerging silicon carbide (SiC) devices, two SiC active switches, namely 1.2 kV, 5 A SiC JFET manufactured by SiCED, and 1.2 kV, 20 A SiC MOSFET by CREE, have been investigated systematically in this thesis. The static and switching characteristics of the two switches have firstly been characterized to get the basic device information. Specific issues in the respective characterization process have been explored and discussed. Many of the characterization procedures presented are generic, so that they can be applied to the study of any future SiC unipolar active switches. Based on the characterization data, different modeling procedures have also been introduced for the two SiC devices. Considerations and measures about model improvement have been investigated and discussed, such as predicting the MOSFET transfer characteristics under high drain-source bias from switching waveforms. Both models have been verified by comparing simulation waveforms with the experimental results. imitations of each model have been explained as well. In order to capture the parasitic ringing in the very fast switching transients, a modeling methodology has also been proposed considering the circuit parasitics, with which a device-package combined simulation can be conducted to reproduce the detailed switching waveforms during the commutation process. This simulation, however, is inadequate to provide deep insights into the physics behind the ringing. Therefore a parametric study has also been conducted about the influence of parasitic impedances on the device's high-speed switching behavior. The main contributors to the parasitic oscillations have been identified to be the switching loop inductance and the device output junction capacitances. The effects of different parasitic components on the device stresses, switching energies, as well as electromagnetic interference (EMI) have all been thoroughly analyzed, whose results exhibit that the parasitic ringing fundamentally does not increase the switching loss but worsens the device stresses and EMI radiation. Based on the parametric study results, this thesis finally compares the difference of SiC JFET and MOSFET in their respective switching behavior, comes up with the concept of device switching speed limit under circuit parasitics, and establishes a general design guideline for high-speed switching circuits on device selection and layout optimization. / Master of Science

This thesis presents the development of a double-side cooled 3.3 kV, 100 A SiC MOSFET phase-leg power module for heavy-duty traction applications. Parasitic extraction and thermal simulations of the module showed a parasitic inductance of 2.89 nH and junction temperature of 108.3 °C at a heat flux of 156 W/cm² under a typical water-cooling condition. Electric field simulations identified high electric field stress at the module's outer surface edges exposed to air, posing a risk for partial discharge. To mitigate this risk, a solution that involves covering the critical point in an epoxy was proposed, analyzed, and validated through partial discharge inception voltage tests. Steps for fabricating the module are presented. Static electrical characterization of the fabricated module showed an average on-resistance of 31 mΩ and an average leakage current of 356 nA at VDS of 3 kV, which are similar to those of the unpackaged devices. The module with a double-side cooling design achieved an exceptional power density of 116.6 kW/cm³, more than twice that of any single-side cooled 3.3 kV SiC module. This makes it highly suitable for next-generation electric transportation systems that require high power density and efficient thermal management, such as electric trucks, railways, and eVTOL aircraft. / Master of Science / This thesis presents the development of a highly efficient and compact power module designed for electric vehicles and other high power applications. By utilizing advanced silicon carbide technology and double-side cooling structure, the module achieves outstanding performance, making it ideal for heavy-duty uses such as electric trucks, railways, and eVTOL aircraft. The module operates at 3.3 kV and 100 A, with low electrical losses and excellent thermal management. Extensive simulations and testing demonstrated that the module significantly reduced unwanted electrical effects and maintained a stable temperature under high power conditions. An epoxy coating was applied to critical areas to prevent electrical discharge, enhancing the module's reliability. The fabrication process incorporated packaging techniques like silver-sintering for attaching the semiconductor chips and other components, resulting in strong and reliable connections. Static tests confirmed that the electrical performance of the packaged power module maintained consistently high efficiency compared with the bare chips. Overall, this double-side cooled power module offers more than twice the power density of traditional designs, paving the way for the development of future electric vehicle traction systems that require high power density and efficient cooling.

付記する学位プログラム名: 京都大学卓越大学院プログラム「先端光・電子デバイス創成学」 / 京都大学 / 新制・課程博士 / 博士(工学) / 甲第25291号 / 工博第5250号 / 京都大学大学院工学研究科電気工学専攻 / (主査)教授 木本 恒暢, 教授 引原 隆士, 准教授 三谷 友彦, 教授 川上 養一 / 学位規則第4条第1項該当 / Doctor of Philosophy (Engineering) / Kyoto University / DFAM

Nowadays high power density has become an emerging need for the medium-voltage (MV) high-power converters in applications of power distribution systems in urban areas and transportation carriers like ship, airplane, and so forth. The limited footprint or space resource cost such immensely high price that introducing expensive advanced equipment to save space becomes a cost-effective option. To this end, replacing conventional Si IGBT with the superior SiC MOSFET to elevate the power density of MV modular converters has been defined as the concentration of this research work. As the modular multilevel converter (MMC) is the most typical modular converter for high power applications, the research topic is narrowed down to study the SiC MOSFET-based MMC. Fundamentals of the MMC is firstly investigated by introducing a proposed state-space switching model, followed by unveiling all possible operation scenarios of the MMC. The lower-frequency energy fluctuation on passive components of the MMC is interpreted and prior-art approaches to overcome it are presented. By scrutinizing the converter's switching states, a new switching-cycle control (SCC) approach is proposed to balance the capacitor energy within one switching cycle is explored. An open-loop model-predictive method is leveraged to study the behavior of the SCC, and then a hybrid-current-mode (HCM) approach to realize the closed-loop SCC on hardware is proposed and verified in simulation. In order to achieve the hybrid-current-mode SCC (HCM-SCC), a high-performance Rogowski switch-current sensor (RSCS) is proposed and developed. As sensing the switching current is a critical necessity for HCM-SCC, the RSCS is designed to meet all the requirement for the control purposes. A PCB-embedded shielding design is proposed to improve the sensor accuracy under high dv/dt noises caused by the rapid switching transients of SiC MOSFET. The overall system and control validations have been conducted on a high-power MMC prototype. The basic unit of the MMC prototype is a SiC Power Electronics Building Block (PEBB) rated at 1 kV DC bus voltage. Owing to the proposed SCC, the PEBB development has achieved high power density with considerable reduction of passive component size. Finally, experimental results exhibit the excellent performance of the RSCS and the HCM-SCC. / Ph. D. / Electricity is the fastest-growing type of end-use energy consumption in the world, and its generation and usage trends are changing. Hence, the power electronics that control the flow and conversion of electrical energy are an important research area. As a typical example, the modular multilevel converter (MMC) is a popular voltage-source converter for high-voltage dc electric transmission systems (VSC-HVDC). The MMC features in excellent voltage scalability that fits various HVDC transmission projects. Though, the huge passive energy storage components of the MMC remains a hurdle to improve its power density. On the other hand, wide-bandgap (WBG) power semiconductors are enabling power electronics to meet higher power density and efficiency, and have thus begun appearing in commercial products, such as traction and solar inverters. Silicon-carbide metal-oxide-semiconductor field-effect transistor (SiC MOSFET), as one type of WBG devices, is able to switch higher voltages faster and with lower losses than existing semiconductor technologies will drastically reduce the size, weight, and complexity of medium-voltage and high-voltage systems. However, these devices also bring new challenges for designers. The objective of this research work is to develop a new control approach that takes advantage of the merits of the SiC MOSFET to reduce the passive components of the MMC. In order to achieve that, a switching-state model of the MMC, a closed-loop hybrid-current-mode switching-cycle control (HCM-SCC) method, a Rogowski switch-current sensor (RSCS), and a SiC-based power electronics building block (PEBB) have been developed. Analytical and experimental results show that the new control approach is able to reduce the capacitance by 93%, inductance by 74%, and semiconductor losses by 11% at the same time, and thus to improve the power density of the MMC power stage by a factor of 23X.

L’avantage de cette architecture FDSOI par rapport à l’architecture Si-bulk est qu’elle possède une face arrière qui peut être utilisée comme une deuxième grille permettant de moduler la tension de seuil Vth du transistor. Pour améliorer les performances des transistors canal p (PMOS), du Germanium est introduit dans le canal (SiGe) et au niveau des sources/drain pour la technologie 14nm FDSOI. Par ailleurs, la réduction de la géométrie des transistors à ces dimensions nanométriques fait apparaître des effets de design physique qui impactent à la fois les performances et la fiabilité des transistors.Ce travail de recherche est développé sur quatre chapitres dont le sujet principal porte sur les performances et la fiabilité des dernières générations CMOS soumises aux mécanismes de dégradation BTI (Bias Temperature Instability) et par injections de porteurs chauds (HCI) dans les dernières technologies 28nm et 14nm FDSOI. Dans le chapitre I, nous nous intéressons à l’évolution de l’architecture du transistor qui a permis le passage des nœuds Low-Power 130-40nm sur substrat silicium à la technologie FDSOI (28nm et 14nm). Dans le chapitre II, les mécanismes de dégradation BTI et HCI des technologies 28nm et 14nm FDSOI sont étudiés et comparés avec les modèles standards utilisés. L’impact des effets de design physique (Layout) sur les paramètres électriques et la fiabilité du transistor sont traités dans le chapitre III en modélisant les contraintes induites par l’introduction du SiGe. Enfin le vieillissement et la dégradation des performances en fréquence ont été étudiés dans des circuits élémentaires de type oscillateurs en anneau (ROs), ce qui fait l’objet du chapitre IV. / The subject of this thesis developed on four chapters, aims the development of advanced CMOS technology nodes fabricated by STMicroelectronics in terms of speed performance and reliability. The main reliability issues as Bias Temperature Instability (BTI) and Hot-Carriers (HC) degradation mechanisms have been studied in the most recent 28nm and 14nm FDSOI technologies nodes. In the first chapter, we presents the evolution of transistor architecture from the low-power 130-40nm CMOS nodes on silicon substrate to the recent FDSOI technology for 28nm and 14nm CMOS nodes. The second chapter presents the specificity of BTI and HCI degradation mechanisms involved in 28nm and 14nm FDSOI technology nodes. In the third chapter, we have studied the impact of layout effects on device performance and reliability comparing symmetrical and asymmetrical geometries. Finally the trade-off between performance and reliability is studied in the fourth chapter using elementary circuits. The benefit of using double gate configuration with the use of back bias VB in FDSOI devices to digital cells, allows to compensate partially or totally the aging in ring oscillators (ROs) observed by the frequency reduction. This new compensation technique allows to extend device and circuit lifetime offering a new way to guaranty high frequency performance and long-term reliability.

Dans les années 2000, les composants de puissance en carbure de silicium (SiC) font leur apparition sur le marché industriel offrant d'excellentes performances. Elles se traduisent par de meilleurs rendements et des fréquences de découpage plus élevées, entrainant une réduction significative du volume et de la masse des convertisseurs de puissance. Le SiC présente de plus un potentiel important de fonctionnement en haute température (>200°C) et permet donc d'envisager de placer l'électronique dans des environnements très contraints jusqu'alors inaccessibles. Pourtant les parts de marche du SiC restent limitées dans l'industrie vis à vis du manque de retour d'expérience concernant la fiabilité de ces technologies relativement nouvelles. Cette question reste aujourd'hui sans réponse et c'est avec cet objectif qu'a été menée cette étude axée sur le vieillissement et l'analyse des mécanismes de dégradation sur des composants de puissance SiC pour des applications haute température. Les tests de vieillissement ont été réalisés sur des transistors MOSFET SiC car ces composants attirent les industriels grâce à leur simplicité de commande et leur sécurité "normalement bloqué" (Normally-OFF). Néanmoins, la fiabilité de l'oxyde de grille est le paramètre limitant de cette structure. C'est pourquoi l'étude de la dérive de la tension de seuil a été mesurée avec une explication du phénomène d'instabilité du VTH. Les résultats ont montré qu'avec l'amélioration des procédés de fabrication, l'oxyde du MOSFET est robuste même pour des températures élevées (jusqu'à 300°C) atteintes grâce à un packaging approprié. Les durées de vie moyennes ont été extraites grâce à un banc de vieillissement accéléré développé pour cette étude. Des analyses macroscopiques ont été réalisées afin d'observer l'évolution des paramètres électriques en fonction du temps. Des études microscopiques sont conduites dans l'objectif d'associer l'évolution des caractéristiques électriques par rapport aux dégradations physiques internes à la puce. Pour notre véhicule de test, la défaillance se traduit par un emballement du courant de grille en régime statique et par l'apparition de fissures dans le poly-Silicium de la grille. Pour finir, une étude de comparaison avec des nouveaux transistors MOSFET a été réalisée. Ainsi l'analogie entre ces composants s'est portée sur des performances statiques, dynamiques, dérivé de la tension de seuil et sur la durée de vie moyenne dans le test de vieillissement. Le fil rouge de ces travaux de recherche est une analyse des mécanismes de dégradation avec une méthodologie rigoureuse permettant la réalisation d'une étude de fiabilité. Ces travaux peuvent servir de base pour toutes analyses d'anticipation de défaillances avec une estimation de la durée de vie extrapolée aux températures de l'application visée / Since 2000, Silicon Carbide (SiC) power devices have been available on the market offering tremendous performances. This leads to really high efficiency power systems, and allows achieving significative improvements in terms of volume and weight, i.e. a better integration. Moreover, SiC devices could be used at high temperature (>200°C). However, the SiCmarket share is limited by the lack of reliability studies. This problem has yet to be solved and this is the objective of this study : aging and failure mechanisms on power devices for high temperature applications. Aging tests have been realized on SiC MOSFETs. Due to its simple drive requirement and the advantage of safe normally-Off operation, SiCMOSFET is becoming a very promising device. However, the gate oxide remains one of the major weakness of this device. Thus, in this study, the threshold voltage shift has been measured and its instability has been explained. Results demonstrate good lifetime and stable operation regarding the threshold voltage below a 300°C temperature reached using a suitable packaging. Understanding SiC MOSFET reliability issues under realistic switching conditions remains a challenge that requires investigations. A specific aging test has been developed to monitor the electrical parameters of the device. This allows to estimate the health state and predict the remaining lifetime.Moreover, the defects in the failed device have been observed by using FIB and SEM imagery. The gate leakage current appears to reflect the state of health of the component with a runaway just before the failure. This hypothesis has been validated with micrographs showing cracks in the gate. Eventually, a comparative study has been realized with the new generations of SiCMOSFET

A rápida e crescente demanda por tecnologias que permitam a redução das dimensões dos transistores planares de porta única leva a uma nova era de dispositivos tensionados mecanicamente. Os transistores de múltiplas portas (MuGFET) com canal de silício e o MOSFET planar convencional com canal de germânio são alguns destes promissores dispositivos avançados a receberem o tensionamento mecânico para aumento da mobilidade dos portadores. O tensionamento mecânico uniaxial, biaxial e ambos combinados são analisados através de simulação numérica de processos e dispositivos e medidas experimentais em três técnicas de tensionamento diferentes, além da análise de medidas obtidas de dispositivos experimentais para análise do aumento da mobilidade dos portadores através da transcondutância máxima. A linha de corte 1D de cada componente do tensionamento simulado é estudado de acordo com a sua dependência com a largura, altura, comprimento do canal e materiais utilizados, assim como a influência que as componentes de tensionamento exercem sobre os parâmetros elétricos analógicos, como transcondutância, ganho intrínseco de tensão e frequência de ganho de tensão unitário. A operação dos dispositivos de silício sobre isolante (SOI Silicon On Insulator) MuGFETs de porta tripla com variações no formato da secção transversal do canal do transistor e variações no comprimento e largura da aleta é estudada em casos selecionados. Um completo estudo da distribuição do tensionamento mecânico gerado por tensionamento global e por tensionamento local é realizado em estruturas com aleta retangular e trapezoidal, juntamente com o impacto destas na mobilidade e nos parâmetros analógicos são realizados. Estruturas nMuGFET SOI com comprimento de canal mais curto alcançaram aumentos maiores de mobilidade utilizando-se o tensionamento uniaxial, enquanto que as estruturas com comprimento de canal mais longo retornaram maior mobilidade com o tensionamento biaxial, resultado da diferente efetividade de cada técnica de tensionamento em cada estrutura. Estruturas MOSFETs convencionais planares com tensionadores embutidos na fonte e dreno em canal de germânio para incremento da mobilidade também são analisadas. Simulações numéricas do processo de fabricação são realizadas e calibradas com dispositivos experimentais em transistores tipo n e tipo p, possibilitando o estudo futuro de estruturas MuGFET de germânio. / The fast and growing demand for technologies that enable the reduction of dimensions of planar single gate transistors leads to a new era of mechanically stressed devices. Multiple gate transistors (MuGFET) with silicon channel and planar bulk MOSFET with germanium channel are some of these promising advanced devices to receive the mechanical stress to increase carriers mobility. The uniaxial stress, biaxial stress and both of them combined are analyzed by process and device numerical simulations in three different strain techniques and also the analysis of experimental measurements for analysis of carriers mobility increase through maximum transconductance. The 1D cut line of each simulated stress component is studied according to their dependence on the width, height and length of the channel and the materials used, as well as the influence that stress components causes on analog electrical parameters, such as transconductance, intrinsic voltage gain and unity gain frequency. The operation of silicon-on-insulator (SOI) triple gate MuGFETs with variations in the shape of the cross section of the transistor channel and variations in the length and width of the fin is studied in selected cases. A complete study in the distribution of the mechanical stress generated by the local and global stress is performed in rectangular and trapezoidal fins and also the impact of these on mobility and analog parameters are studied. SOI nMuGFET structures with shorter channel length achieved higher mobility increases using the uniaxial stress, while structures with longer channel lengths returned higher mobility using the biaxial stress, result of the different effectiveness in each stress technique for each structure. Conventional MOSFET structures with embedded stressors in the source and drain regions with germanium channel are also analyzed. Numerical process simulations are realized and calibrated with experimental devices in both n and p type transistors, making possible the future study of MuGFET structures with germanium.