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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
181

Low-Power, Low-Voltage SRAM Circuits Design For Nanometric CMOS Technologies

Shakir, Tahseen 29 August 2011 (has links)
Embedded SRAM memory is a vital component in modern SoCs. More than 80% of the System-on-Chip (SoC) die area is often occupied by SRAM arrays. As such, system reliability and yield is largely governed by the SRAM's performance and robustness. The aggressive scaling trend in CMOS device minimum feature size, coupled with the growing demand in high-capacity memory integration, has imposed the use of minimal size devices to realize a memory bitcell. The smallest 6T SRAM bitcell to date occupies a 0.1um2 in silicon area. SRAM bitcells continue to benefit from an aggressive scaling trend in CMOS technologies. Unfortunately, other system components, such as interconnects, experience a slower scaling trend. This has resulted in dramatic deterioration in a cell's ability to drive a heavily-loaded interconnects. Moreover, the growing fluctuation in device properties due to Process, Voltage, and Temperature (PVT) variations has added more uncertainty to SRAM operation. Thus ensuring the ability of a miniaturized cell to drive heavily-loaded bitlines and to generate adequate voltage swing is becoming challenging. A large percentage of state-of-the-art SoC system failures are attributed to the inability of SRAM cells to generate the targeted bitline voltage swing within a given access time. The use of read-assist mechanisms and current mode sense amplifiers are the two key strategies used to surmount bitline loading effects. On the other hand, new bitcell topologies and cell supply voltage management are used to overcome fluctuations in device properties. In this research we tackled conventional 6T SRAM bitcell limited drivability by introducing new integrated voltage sensing schemes and current-mode sense amplifiers. The proposed schemes feature a read-assist mechanism. The proposed schemes' functionality and superiority over existing schemes are verified using transient and statistical SPICE simulations. Post-layout extracted views of the devices are used for realistic simulation results. Low-voltage operated SRAM reliability and yield enhancement is investigated and a wordline boost technique is proposed as a means to manage the cell's WL operating voltage. The proposed wordline driver design shows a significant improvement in reliability and yield in a 400-mV 6T SRAM cell. The proposed wordline driver design exploit the cell's Dynamic Noise Margin (DNM), therefore boost peak level and boost decay rate programmability features are added. SPICE transient and statistical simulations are used to verify the proposed design's functionality. Finally, at a bitcell-level, we proposed a new five-transistor (5T) SRAM bitcell which shows competitive performance and reliability figures of merit compared to the conventional 6T bitcell. The functionality of the proposed cell is verified by post-layout SPICE simulations. The proposed bitcell topology is designed, implemented and fabricated in a standard ST CMOS 65nm technology process. A 1.2_ 1.2 mm2 multi-design project test chip consisting of four 32-Kbit (256-row x 128-column) SRAM macros with the required peripheral and timing control units is fabricated. Two of the designed SRAM macros are dedicated for this work, namely, a 32-Kbit 5T macro and a 32-Kbit 6T macro which is used as a comparison reference. Other macros belong to other projects and are not discussed in this document.
182

Groundbased instrumentation for measurements of atmospheric airglow

Loewen, Paul 04 January 2005 (has links)
A groundbased instrument to measure the Atmospheric airglow of the molecular oxygen infrared atmospheric band emission was designed, built, tested and operated. The two channel photometer constructed was based on the original design by Evans (1967) that had been used in balloon experiments. The two channel photometer system specifications are presented. The major difference between the presented design and the earlier two channel photometers is the detector. An Indium Gallium Arsenide (InGaAs) photodiode provided better signal to noise in the conversion of the infrared light signal to an electronic signal than the previously used Lead Sulphide (PbS) detectors. The completed instrument was tested to determine its performance characteristics. Through these tests it was found that the photometer output offset is sensitive to ambient temperature fluctuations. An analysis of the instrument noise was done in an attempt to explain this sensitivity. The output noise performance was characterized and is presented together with the absolute brightness and wavelength calibrations. Data was collected with the instrument in Saskatoon, SK and Eureka, NU. After an initial observation campaign in the high arctic (Eureka, NU) modifications were made to the environmental housing of the instrument in order to improve the scientific value of the data collected. The collected data was processed and a simple analysis performed to demonstrate the capability of the photometer to measure the infrared atmospheric airglow. The collected data can be used to determine the mesospheric ozone height profile. The required data analysis to do so is beyond the scope of this presentation. However, the presented data does demonstrate that the designed and constructed two channel photometer can make the necessary measurements.
183

Fabrication of Single-mode Cr-doped Fibers

Lin, Ting-chien 16 July 2010 (has links)
The fabrication of broadband single-mode Cr-doped silica fibers (SMCDSFs) using the fiber drawing-tower method with the modified rod-in-tube technique is demonstrated for the first time. A preform was assembled by using the grown Cr:YAG rod as core and the silica tube as cladding. The outer and inner diameters of the silica tube are 20 and 7 mm, respectively. The initial dimension of the Cr:YAG crystal rod had a length of 0.03 m and a diameter of 500 £gm. The Cr:YAG crystal was grown into a diameter of a 290 £gm with a length of 0.12 m by the LHPG method. The SMCDSFs had a 6 £gm core and a 125 £gm cladding. The transmission loss was 0.08 dB/cm at 1550 nm. The far-field pattern measurements indicated the single-mode characteristic when the propagation wavelength was longer than 1310 nm. In order to solve the interface of core and cladding, a novel rod-in-tube(RIT) perform was employed by inserting the Cr:YAG crystal rod of 0.03m length and 500 £gm diameter into the silica capillary tube, which had the same diameter with the drilled silica rod. The single-mode Cr-doped fibers had successfully been fabricated and the loss had been reduced to 0.03 dB/cm at 1550 nm with a 5 £gm core and a 125 £gm cladding. Furthermore, the SMCDSFs also had the single-mode characteristic when they operated in the optical communication window. The successful fabrication of SMCDSFs may be one step forward towards the achievement of utilizing the SMCDSFs as ultra-broadband fiber optical amplifiers to cover the bandwidths in the whole 1300 to 1600 nm range of low-loss and low-dispersion windows of silica fibers and a broadband source for enabling high resolution in optical coherence tomography (OCT).
184

Implementation of a 1.8V 12bits 100-MS/s Pipelined Analog-to-Digital Converter

Ma, Ting-Chang 04 August 2010 (has links)
Because IC (Integrated Circuit) has some good features like: little, low power consumption, and high stable, so it already popularly applied to our daily life. Operation is one of the main functions of IC, and now operate function achieve in digital mode of many IC products. Although digital circuits have many advantages, but we live in the analog world, natural signals are all analog. Digital circuits can¡¦t direct process analog signals, and therefore we have a requirement of analog-to-digital converter. As time goes by, IC technology has made great progress; digital circuits have faster process ability, and we also require a high speed analog-to-digital converter. Besides, in order to achieve higher picture quality and clearer voice, we also require a high resolution analog-to-digital converter. For portable products, the power consumption also needs to take into account. As mentioned above, I will implement a high speed, high resolution and low power analog-to-digital converter. In this thesis, the circuits are designing with TSMC.18£gm 1P6M CMOS process and 1.8V of supply voltage. The speed and resolution of ADC are 100Ms/s and 12bits individually. The pipelined coupling with 1.5bit/stage constitutes the main architecture of analog-to-digital converter. The dynamic comparator is used for lower power. Finally, the output codes are translated by digital correction circuit. Keywords: ADC, Analog-to-Digital Converter, pipeline, low power, amplifier, comparator.
185

RF Front-End Heterogeneous Chip Integration and the Use of Magnetically Coupled Interconnection Techniques

Lee, Cheng-Tse 19 July 2011 (has links)
The first part of this thesis studies the wire-bonding technology for use in an integrated design of transformer balun and RF front-end receiver, which is realized by IPD and CMOS technology, respectively. In this part, the RF front-end receiver and the balun were designed separately, and the bondwire model was established based on electromagnetic simulation. For the maximum power transfer and optimal noise performance, the input impedance between the CMOS RF front-end receiver and the IPD balun was conjugate-matched. The IPD balun, placed in front of the differential LNA of a direct-conversion receiver, is designed using the IPD technology, thereby reducing the insertion loss, and subsequently improving the noise figure of the CMOS receiver. The second part of this thesis uses a vertically coupled transformer balun with a primary coil made by IPD technology and a secondary coil made by CMOS technology. This balun has a low-loss advantage when integrated with a posterior differential LNA. Finally, the magnetic resonance coupling for use in signal transmission is studied and experimented on a printed circuit board.
186

Design of a programmable multi-parameter amplifier front-end for bio-potential recording

Lin, Yu-bin 30 August 2011 (has links)
Home medical equipment becomes increasingly popular as VLSI fabrication technology advances. However, there are two important factors for realizing a miniaturized biochip: low noise [1] and low power. Firstly, physiological signals are very susceptible to interference while the amplitude of the signal is only a few millivolts or less. If the circuit cannot reject noise effectively, it is hard to amplify the signal and obtain the output voltage of the recording system accurately. Secondly, it is not convenient to replace the batteries frequently when using the portable measurement instrument for the patients. This thesis is focused on the measurement of physiological signals, such as electrocardiography (ECG) [2], electroneurogram (ENG) [3] and electromyography (EMG) [4] , and designing an all-in-one recording system to measure the different physiological signals in a chip. For this purpose, a programmable multi-parameter system for recording of the wide range of physiological signals is designed. The system provides two types of input transconductance stages, BiCMOS and CMOS. BiCMOS amplifiers provide high gain , low noise [5] and low offset voltage suitable for the small amplitude of the physiological signal. On the other hand, CMOS amplifiers provide practically infinite input impedance and ultra-low leakage current. The system also provides three selectable amplifier modes: (a) double-differential amplifier, (b) single-differential amplifier in channel 1, (c) single-differential amplifier in channel 2. The double-differential amplifier provides a high common-mode rejection and adjustable gain for each channel to further reduce common-mode interference. The single-differential amplifier (channel 1 or channel 2) in the recording system are also accessible as differential-input and single-ended output channels. Moreover, the system provides an offset compensation structure to prevent the amplifier from exceeding the input range. The offset compensation system can selectively be turned off to reduce the power consumption.
187

The Design and Simulation of a 24 GHz Class-A Cascode Configured Power Amplifier

Wang, Shun-Hong 20 February 2012 (has links)
Abstract Recently, the proliferating needs of high data rate communication systems are increasing the demand for higher frequency bands with broader bandwidth. The K-band (18~26.5 GHz), which include point to point communications (18~23 GHz), ISM band (24 GHz), and automotive radar applications (24 GHz and 22~29 GHz) is one of the most important frequency bands in modern wireless communication systems. This thesis mainly includes three parts. The first part of the thesis is the introduction to the principles and characteristics for active and passive components of CMOS process and the description of common transistors , such as BJT, CMOSFET, HBT and pHEMT. The principles of resistors, capacitors and inductors in simulations is shown. It is useful for the microwave circuit design to understand the structure and characteristics of active components and passive components in CMOS process. The second part describes the design principles and characteristics of power amplifier. The third part is the design and simulation of the 2 stages cascode configuration Class A power amplifier and the 3 stages cascode configuration Class A power amplifier with power combination. There are two important scaling trends that are making CMOS increasingly attractive for RF applications. One is the well known dramatic shrinkage of device size, so that transistors in the advanced process generation of CMOS have peak fT values in excess of 55 GHz.The other is the reverse scaling of interconnect. The thicker metal layer and more layers of wiring are enabling the realization of high-quality passive components which are critical for RF circuits. CMOS is the most attractive technology for its low cost, high yield and high level of integration. However, It is challenging to design a power amplifier with high output power. In the sub-micron CMOS technology, the challenges of CMOS power amplifier design include the low breakdown voltage, low transconductance (gm), and high substrate loss as compared with SiGe HBTs GaAs HBTs and InP-GaAs HBTs technologies. We made efforts in implementing a power amplifier at K-band. The design and simulation of two power amplifier is present. One is the 2 stages power amplifier, the other is the 3 stages power amplifier with power combination. In order to realize the inductive element and capacitive element in sub-milimeter wave or millimeter wave circuit design, the short stub microstrip line and open stub mircrostrip line are used in matching networks between all stages. The cascade configuration is effective structure to minimize Miller effect in high frequency. The peak gain of 2 stages power amplifier is 17 dB at 24 GHz and the saturation output power is 20 dBm. The OP1dB is over 16 dBm. The peak gain of 3 stages power amplifier with power combination is 20 dB at 24 GHz and the saturation output power is 20.5 dBm. The OP1dB is over 15 dBm.The power amplifier with the cascode configuration and power combination techniques is designed and simulated in TSMC 0.18 um CMOS process, which provides deep n-well, and MiM capacitors.
188

2.45 GHz ZigBee Receiver Frontend and Delta-Sigma ADC with Constant-gm Amplifier for Battery Management Systems

Luo, Wayne 07 July 2012 (has links)
This thesis consists of two topics: A 2.45 GHz ZigBee Receiver Frontend design for home energy-saving systems and a Delta-Sigma ADC with constant-gm amplifier for Battery Management Systems (BMS). A 2.45 GHz ZigBee Receiver Frontend for home energy-saving systems is pre-sented in the first part of this thesis. The proposed ZigBee receiver can be used in areas where wireline solutions are hard to be realized. By employing an LNA at the very frontend of the receiver, the gain is simulated to be 17.376 dB at 2.45 GHz. Besides, by using the double-balanced Gilbert mixer with a current bleeding MOS transistor, the NF and the IIP3 of the mixer are only 5.074 dB and -7.234 dB, respectively. To reduce the phase noise of the receiver, a fractional-N frequency synthesizer with a complementary cross-coupled VCO is adopted. The phase noise of the fractional-N frequency synthe-sizer is 137.7 dBc/Hz. The proposed circuit is carried out and measured on silicon using the standard TSMC 0.18 £gm CMOS process. In the second topic, a Delta-Sigma ADC with constant-gm amplifier is presented. The proposed ADC is particularly designed for the voltage detection circuit in BMS. A constant-gm amplifier is also presented to resolve the nonlinearity of the amplifier de-grading the performance of Delta-Sigma modulator, which is the frontend of the Del-ta-Sigma ADC. With the 4 KHz signal bandwidth, 512 KHz sampling frequency, and 128 oversampling rate, it shows a 85.2 dB SNR, and 12-bit resolution. The backend of the ADC is the decimator, which reduces the sampling frequency compliant with the Nyquist rate rule. The decimator is realized by Verilog code and verified by FPGA. By following the mixed-signal flow, the ADC is realized on a single chip using the standard TSMC 0.25 £gm 60V HV CMOS process.
189

Erbium-doped fiber ring laser tuning using an intra-cavity Fabry-Perot filter

Malik, Bilal Hameed 02 June 2009 (has links)
A tunable erbium-doped fiber ring laser using an intra-cavity Fabry-Perot filter as the tuning element is investigated. Tuning is achieved by varying the applied voltage which controls the FP cavity length. The laser's wavelength is monitored using an optical spectrum analyzer to determine the laser's spectral characteristics under static conditions at different wavelengths over its tuning range of approximately 50nm. When the laser is tuned rapidly, the frequency versus time characteristic is determined using a fiber Fabry-Perot interferometer with a photodetector to convert the optical signal to an electrical signal. The core of the research is to determine the degree of spectral broadening of the laser as a function of the spectral tuning rate. The fringe contrast of fiber Fabry-Perot interferometer transmittance curves decreases with increase in the tuning frequency. The gain at a certain wavelength becomes a function of time putting an upper limit on the tuning frequency of the system. The carrier lifetime of erbium ions dictates the maximum achievable tuning speed.
190

Design Techniques for High Speed Low Voltage and Low Power Non-Calibrated Pipeline Analog to Digital Converters

Assaad, Rida Shawky 2009 December 1900 (has links)
The profound digitization of modern microelectronic modules made Analog-to- Digital converters (ADC) key components in many systems. With resolutions up to 14bits and sampling rates in the 100s of MHz, the pipeline ADC is a prime candidate for a wide range of applications such as instrumentation, communications and consumer electronics. However, while past work focused on enhancing the performance of the pipeline ADC from an architectural standpoint, little has been done to individually address its fundamental building blocks. This work aims to achieve the latter by proposing design techniques to improve the performance of these blocks with minimal power consumption in low voltage environments, such that collectively high performance is achieved in the pipeline ADC. Towards this goal, a Recycling Folded Cascode (RFC) amplifier is proposed as an enhancement to the general performance of the conventional folded cascode. Tested in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18?m Complementary Metal Oxide Semiconductor (CMOS) technology, the RFC provides twice the bandwidth, 8-10dB additional gain, more than twice the slew rate and improved noise performance over the conventional folded cascode-all at no additional power or silicon area. The direct auto-zeroing offset cancellation scheme is optimized for low voltage environments using a dual level common mode feedback (CMFB) circuit, and amplifier differential offsets up to 50mV are effectively cancelled. Together with the RFC, the dual level CMFB was used to implement a sample and hold amplifier driving a singleended load of 1.4pF and using only 2.6mA; at 200MS/s better than 9bit linearity is achieved. Finally a power conscious technique is proposed to reduce the kickback noise of dynamic comparators without resorting to the use of pre-amplifiers. When all techniques are collectively used to implement a 1Vpp 10bit 160MS/s pipeline ADC in Semiconductor Manufacturing International Corporation (SMIC) 0.18[mu]m CMOS, 9.2 effective number of bits (ENOB) is achieved with a near Nyquist-rate full scale signal. The ADC uses an area of 1.1mm2 and consumes 42mW in its analog core. Compared to recent state-of-the-art implementations in the 100-200MS/s range, the presented pipeline ADC uses the least power per conversion rated at 0.45pJ/conversion-step.

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