As CMOS technologies advance to 22-nm dimensions and below, constructing analog circuits are difficult to design within permitted specifications. One of the reasons for this is a limit of voltage resolution. In this situation, time-mode processing is a technique that is believed to be well suited for solving many of these challenges. A primary advantage of this technique is the ability to achieve analog functions using digital logic structures. Time difference amplifiers (TDA) can be a key component to realize fine time solutions. TDA are an innovative method to improve the time resolution as well as the evolution of ADC. This thesis introduces a TDA that amplifies the input time difference between two signals by a fractional gain. The closed loop gain control system used in this work consists of a pseudo differential current starved delay element (PDCSDE) and a monotonic digitally controlled delay element (DCDE). By using these elements to create a delay chain and a control loop, the result is a stable fractional time difference gain (TD gain). The system was designed and simulated in 65nm process at 1.2V power supply. The measured results show that this TDA achieves a fractional TD gain offset lower than 1.3%, with supply variation of ±15%, and input range as wide as ±250ps. The new design was also more resilient to process, voltage and temperature (PVT) variations

The mid-infrared (MIR) system presented in the thesis is based on a sub-100-fs erbium-doped fiber laser operating at 1.55 µm. The output of the laser is split in two, each arm seeding an erbium-doped fiber amplifier. The output of the first amplifier is sent to a grating-based stretcher to be stretched to 50 ps before seeding the optical parametric chirped-pulse amplifier (OPCPA). The output of the second amplifier is coupled to a highly nonlinear fiber to generate the 1 µm needed to seed the a neodymium-doped yttrium lithium fluoride (Nd:YLF) system. This work represents the first time this synchronization scheme is used, and the timing jitter between the two arms at the OPCPA is reduced to 333 fs. The pump laser for the OPCPA is a regenerative amplifier producing 1.6 W followed by a double-pass amplifier, for a final output power of 2.5 W at 1 kHz. Etalons were inserted into the cavity of the regenerative amplifier to stretch the pulses to 50 ps The OPCPA consists of two potassium titanyl arsenate crystals in a noncollinear configuration. With three passes, the gain is 3.8 · 10 6 . Using a grating compressor, the pulse duration is reduced to 140 fs, with a power of 300 mW. Because of the reduction of the timing jitter, the amplitude stability is 1 %, which is a great improvement compare to existing systems. To generate ultrafast light in the MIR, an optical parametric amplifier is used, pumped ii by the output of the OPCPA and seeded with its 3-µm idler. Two crystals were tested, both in a single-pass configuration. For the first crystal, a 4-mm thick silver thiogallate, an efficiency of 7.4 % was reached, with 8.76 mW in the signal and 7.2 mW in the idler. For the second crystal, a 2-mm thick lithium gallium selenide, the efficiency was higher, reaching 10.8 %. The power for the signal was 11.5 mW, and for the idler, 11.11 mW. Using this new scheme, energies on par with current systems are achieved with much higher efficiencies.

The objective of this work was to integrate an optical receiver in a modern standard technology in a form amenable to multiple lanes. To accomplish this goal, a photodiode was integrated with the receiver in a standard 90nm CMOS process and the nominal process voltage of 1.2V was not exceeded. Two optical lanes were integrated on chip with a pitch compatible with existing industry photodiode arrays. This work uses a non-SML photodiode to increase optical responsivity to 0.141A/W, almost 3 times higher than values typically reported for SML photodiodes. This receiver is the first integrated optical receiver reported in a standard CMOS technology with a feature size smaller than 0.13μm, which is necessary for the eventual integration of optical receivers with modern digital processing blocks on a single die. The traditional analog equalizer used in most integrated optical receivers is replaced with a high-pass filter and hysteresis latch for equalization. The receiver occupies a core area of 0.197mm2 and has an optical sensitivity of -3.7dBm at a 2Gbps data rate, while consuming 46.3mW.

The mid-infrared (MIR) system presented in the thesis is based on a sub-100-fs erbium-doped fiber laser operating at 1.55 µm. The output of the laser is split in two, each arm seeding an erbium-doped fiber amplifier. The output of the first amplifier is sent to a grating-based stretcher to be stretched to 50 ps before seeding the optical parametric chirped-pulse amplifier (OPCPA). The output of the second amplifier is coupled to a highly nonlinear fiber to generate the 1 µm needed to seed the a neodymium-doped yttrium lithium fluoride (Nd:YLF) system. This work represents the first time this synchronization scheme is used, and the timing jitter between the two arms at the OPCPA is reduced to 333 fs. The pump laser for the OPCPA is a regenerative amplifier producing 1.6 W followed by a double-pass amplifier, for a final output power of 2.5 W at 1 kHz. Etalons were inserted into the cavity of the regenerative amplifier to stretch the pulses to 50 ps The OPCPA consists of two potassium titanyl arsenate crystals in a noncollinear configuration. With three passes, the gain is 3.8 · 10 6 . Using a grating compressor, the pulse duration is reduced to 140 fs, with a power of 300 mW. Because of the reduction of the timing jitter, the amplitude stability is 1 %, which is a great improvement compare to existing systems. To generate ultrafast light in the MIR, an optical parametric amplifier is used, pumped ii by the output of the OPCPA and seeded with its 3-µm idler. Two crystals were tested, both in a single-pass configuration. For the first crystal, a 4-mm thick silver thiogallate, an efficiency of 7.4 % was reached, with 8.76 mW in the signal and 7.2 mW in the idler. For the second crystal, a 2-mm thick lithium gallium selenide, the efficiency was higher, reaching 10.8 %. The power for the signal was 11.5 mW, and for the idler, 11.11 mW. Using this new scheme, energies on par with current systems are achieved with much higher efficiencies.

The objective of this work was to integrate an optical receiver in a modern standard technology in a form amenable to multiple lanes. To accomplish this goal, a photodiode was integrated with the receiver in a standard 90nm CMOS process and the nominal process voltage of 1.2V was not exceeded. Two optical lanes were integrated on chip with a pitch compatible with existing industry photodiode arrays. This work uses a non-SML photodiode to increase optical responsivity to 0.141A/W, almost 3 times higher than values typically reported for SML photodiodes. This receiver is the first integrated optical receiver reported in a standard CMOS technology with a feature size smaller than 0.13μm, which is necessary for the eventual integration of optical receivers with modern digital processing blocks on a single die. The traditional analog equalizer used in most integrated optical receivers is replaced with a high-pass filter and hysteresis latch for equalization. The receiver occupies a core area of 0.197mm2 and has an optical sensitivity of -3.7dBm at a 2Gbps data rate, while consuming 46.3mW.

Embedded SRAM memory is a vital component in modern SoCs. More than 80% of the System-on-Chip (SoC) die area is often occupied by SRAM arrays. As such, system reliability and yield is largely governed by the SRAM's performance and robustness. The aggressive scaling trend in CMOS device minimum feature size, coupled with the growing demand in high-capacity memory integration, has imposed the use of minimal size devices to realize a memory bitcell. The smallest 6T SRAM bitcell to date occupies a 0.1um2 in silicon area. SRAM bitcells continue to benefit from an aggressive scaling trend in CMOS technologies. Unfortunately, other system components, such as interconnects, experience a slower scaling trend. This has resulted in dramatic deterioration in a cell's ability to drive a heavily-loaded interconnects. Moreover, the growing fluctuation in device properties due to Process, Voltage, and Temperature (PVT) variations has added more uncertainty to SRAM operation. Thus ensuring the ability of a miniaturized cell to drive heavily-loaded bitlines and to generate adequate voltage swing is becoming challenging. A large percentage of state-of-the-art SoC system failures are attributed to the inability of SRAM cells to generate the targeted bitline voltage swing within a given access time. The use of read-assist mechanisms and current mode sense amplifiers are the two key strategies used to surmount bitline loading effects. On the other hand, new bitcell topologies and cell supply voltage management are used to overcome fluctuations in device properties. In this research we tackled conventional 6T SRAM bitcell limited drivability by introducing new integrated voltage sensing schemes and current-mode sense amplifiers. The proposed schemes feature a read-assist mechanism. The proposed schemes' functionality and superiority over existing schemes are verified using transient and statistical SPICE simulations. Post-layout extracted views of the devices are used for realistic simulation results. Low-voltage operated SRAM reliability and yield enhancement is investigated and a wordline boost technique is proposed as a means to manage the cell's WL operating voltage. The proposed wordline driver design shows a significant improvement in reliability and yield in a 400-mV 6T SRAM cell. The proposed wordline driver design exploit the cell's Dynamic Noise Margin (DNM), therefore boost peak level and boost decay rate programmability features are added. SPICE transient and statistical simulations are used to verify the proposed design's functionality. Finally, at a bitcell-level, we proposed a new five-transistor (5T) SRAM bitcell which shows competitive performance and reliability figures of merit compared to the conventional 6T bitcell. The functionality of the proposed cell is verified by post-layout SPICE simulations. The proposed bitcell topology is designed, implemented and fabricated in a standard ST CMOS 65nm technology process. A 1.2_ 1.2 mm2 multi-design project test chip consisting of four 32-Kbit (256-row x 128-column) SRAM macros with the required peripheral and timing control units is fabricated. Two of the designed SRAM macros are dedicated for this work, namely, a 32-Kbit 5T macro and a 32-Kbit 6T macro which is used as a comparison reference. Other macros belong to other projects and are not discussed in this document.

É apresentado um amplificador de potência (PA) com controle digital da potência de saída, operando na banda S de frequência (2,2 GHz). Este PA utiliza um transformador de entrada para reduzir as flutuações dos sinais de terra. Um estágio de excitação oferece uma impedância apropriada para a fonte de entrada e ganho para o próximo estágio. O estágio de controle é usado para melhorar a eficiência do PA, composto por quatro ramos paralelos de chaves, onde os estados (ligado ou desligado) são separadamente ativados por uma palavra de controle de 4 bits. O estágio de saída implementa um amplificador classe E, usando uma topologia cascode para minimizar o estresse de tensão sobre os transistores, permitindo sua utilização sob tensão de alimentação de 3,3 V para se atingir uma potência de saída máxima em torno de 1 W, em um processo CMOS 130 nm, cuja tensão típica de alimentação é 1,2 V. O PA proposto foi projetado em uma tecnologia CMOS 130 nm para RF, ocupa uma área de 1,900 x 0,875 mm2 e os resultados das simulações em leiaute extraído obtidos demonstram uma potência de saída máxima de 28,5 dBm (707 mW), com PAE (Power- Added Efficiency) correspondente de 49,7%, para uma tensão de alimentação de 3,3 V. O controle de 4 bits permite um ajuste dentro da faixa dinâmica da potência de saída entre 13,6 a 28,5 dBm (22,9 a 707 mW), divididos em 15 passos, com o PAE variando de 9,1% a 49,7%. O PA proposto permite redução do consumo de potência quando este não está transmitindo na potência máxima. A potência consumida atinge um mínimo de 0,21Wquando a potência de saída é de 13,6 dBm (22,9 mW) e um máximo de 1,4 W quando a potência de saída é de 28,5 dBm (707 mW), o que representa 1,19 W de economia, aumentando a vida da bateria. A linearidade obtida neste circuito mostrou-se suficiente para atender os requisitos da máscara de emissão de espúrios de um padrão de comunicação com envoltória constante largamente utilizado, apresentando desempenho adequado para atender as especificações dos sistemas de comunicações modernos. / A power amplifier with digital power control useful to S-Band (2.2 GHz) applications and with an output power around 1 W is presented. It uses an input transformer to reduce ground bounce effects. A tuned driver stage provides impedance matching to the input signal source and proper gain to the next stage. A control stage is used for efficiency improvement, composed by four parallel branches where the state (on or off) is separately activated by a 4-bit input. The class-E power stage uses a cascode topology to minimize the voltage stress over the power transistors, allowing higher supply voltages. The PA was designed in a 130 nm RF CMOS process and the layout has a total area of 1.900 x 0.875 mm2, post-layout simulations resulted a peak output power of 28.5 dBm with a maximum power added efficiency (PAE) around 49.7% under 3.3 V of supply voltage. The 4-bit control allows a total output power dynamic range adjustment of 14.9 dB, divided in 15 steps, with the PAE changing from 9.1% to 49.7%. The proposed PA allows reduce the power consumption when it isn’t transmitting at the maximum output power. Where the power consumption is only 0.21 W when the PA is at the minimum output power level of 13.6 dBm (22.9 mW), which is 1.19 W smaller than the power consumption at full mode (1.4 W), increasing the battery life. The linearity in this circuit meet the emission mask requirements for a widely used communication standard with constant envelope. Post-layout simulation results indicate an overall performance adequate to fulfill the specifications of modern wireless communication systems.

É apresentado um amplificador de potência (PA) com controle digital da potência de saída, operando na banda S de frequência (2,2 GHz). Este PA utiliza um transformador de entrada para reduzir as flutuações dos sinais de terra. Um estágio de excitação oferece uma impedância apropriada para a fonte de entrada e ganho para o próximo estágio. O estágio de controle é usado para melhorar a eficiência do PA, composto por quatro ramos paralelos de chaves, onde os estados (ligado ou desligado) são separadamente ativados por uma palavra de controle de 4 bits. O estágio de saída implementa um amplificador classe E, usando uma topologia cascode para minimizar o estresse de tensão sobre os transistores, permitindo sua utilização sob tensão de alimentação de 3,3 V para se atingir uma potência de saída máxima em torno de 1 W, em um processo CMOS 130 nm, cuja tensão típica de alimentação é 1,2 V. O PA proposto foi projetado em uma tecnologia CMOS 130 nm para RF, ocupa uma área de 1,900 x 0,875 mm2 e os resultados das simulações em leiaute extraído obtidos demonstram uma potência de saída máxima de 28,5 dBm (707 mW), com PAE (Power- Added Efficiency) correspondente de 49,7%, para uma tensão de alimentação de 3,3 V. O controle de 4 bits permite um ajuste dentro da faixa dinâmica da potência de saída entre 13,6 a 28,5 dBm (22,9 a 707 mW), divididos em 15 passos, com o PAE variando de 9,1% a 49,7%. O PA proposto permite redução do consumo de potência quando este não está transmitindo na potência máxima. A potência consumida atinge um mínimo de 0,21Wquando a potência de saída é de 13,6 dBm (22,9 mW) e um máximo de 1,4 W quando a potência de saída é de 28,5 dBm (707 mW), o que representa 1,19 W de economia, aumentando a vida da bateria. A linearidade obtida neste circuito mostrou-se suficiente para atender os requisitos da máscara de emissão de espúrios de um padrão de comunicação com envoltória constante largamente utilizado, apresentando desempenho adequado para atender as especificações dos sistemas de comunicações modernos. / A power amplifier with digital power control useful to S-Band (2.2 GHz) applications and with an output power around 1 W is presented. It uses an input transformer to reduce ground bounce effects. A tuned driver stage provides impedance matching to the input signal source and proper gain to the next stage. A control stage is used for efficiency improvement, composed by four parallel branches where the state (on or off) is separately activated by a 4-bit input. The class-E power stage uses a cascode topology to minimize the voltage stress over the power transistors, allowing higher supply voltages. The PA was designed in a 130 nm RF CMOS process and the layout has a total area of 1.900 x 0.875 mm2, post-layout simulations resulted a peak output power of 28.5 dBm with a maximum power added efficiency (PAE) around 49.7% under 3.3 V of supply voltage. The 4-bit control allows a total output power dynamic range adjustment of 14.9 dB, divided in 15 steps, with the PAE changing from 9.1% to 49.7%. The proposed PA allows reduce the power consumption when it isn’t transmitting at the maximum output power. Where the power consumption is only 0.21 W when the PA is at the minimum output power level of 13.6 dBm (22.9 mW), which is 1.19 W smaller than the power consumption at full mode (1.4 W), increasing the battery life. The linearity in this circuit meet the emission mask requirements for a widely used communication standard with constant envelope. Post-layout simulation results indicate an overall performance adequate to fulfill the specifications of modern wireless communication systems.

Aim of this thesis is to construct a demonstration model of a vacuum tube amplifier with a possibility of measurement of signal on more places and a possibility to see the wiring and construction of the amplifier. The first part of the work treats some important themes concerning vacuum tubes and wiring with them, for example a principle of signal intensification by vacuum tubes, categories of low-frequency amplifiers and description of several types of undesirable distortions. Next part deals with the design of the constructed amplifier, the description of the construction itself and placement of the components on the printed circuit boards and used vacuum tubes and transformers. The following part is focused on measurement of the basic properties of the amplifier and vacuum tubes by means of TESLA BM215A appliance. The final part contains technical parameters of the amplifier and photo documentation.

abstract: This thesis is a study of Bandwidth limitation of basestation power amplifier and its Doherty application. Fundamentally, bandwidth of a power amplifier (PA) is limited by both its input and output prematch networks and its Doherty architecture, specifically the impedance inverter between the main and auxiliary amplifier. In this study, only the output prematch network and the Doherty architecture follows are being investigated. A new proposed impedance inverter in the Doherty architecture exhibits an extended bandwidth compared to traditional quarterwave line. Base on the loadline analysis, output impedance of the power amplifier can be represented by a loadline resistor and an output shunt capacitor. Base on this simple model, the maximum allowed bandwidth of the output impedance of the power amplifier can be estimated using the Bode-Fano method. However, since power amplifier is in fact nonlinear, harmonic balance simulation is used to loadpull the device across a broad range of frequencies. Base on the simulated large signal impedance at maximum power, the prematch circuitry can be designed. On a system level, the prematch power amplifier is used in Doherty amplifier. Two different prematch circuitries, T- section and shunt L methods are investigated along with their comparison in the Doherty architecture at both back off power and peak power condition. The last section of the thesis will be incorporating the proposed impedance inverter structure between the main and auxiliary amplifiers. The simulated results showed the shunt L prematch topology has the least impedance dispersion across frequency. Along with the new impedance inverter structure, the 65% efficiency bandwidth improves by 50% compared to the original impedance inverter structure at back off power level. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2014