Three high performance circuits for a low power supply DRAM¡¦s are presented in this thesis. First, a modified multi-stage sense amplifier is proposed, that utilizes the auxiliary transmission gate and charge recycling technique. The auxiliary NMOS transistor of the multi-stage sense amplifier is replaced by the transmission gate to improve the sensing speed. In addition, the charge recycling technique is used to reduce the power dissipation of multi-stage sense amplifier. It improves the sensing time by 6.1ns (24.4%) compared to that of the conventional multi-stage sense amplifier and the power saving percentage of 25.6% compared to that of the conventional one. Second, an improved Standby Power Reduction (SPR) Circuit is reported. The capacitor boosting technique is utilized in our proposed Static Current Cut-off Standby Power Reduction (SCCSPR) Circuit, which turns off the always-on MOS transistor of SPR circuit. The power consumption is 30.9% reduced by our design compared to that of the conventional SPR circuit. Third, an improved voltage doubler is developed. The indirect switch is utilized in our proposed circuit, it provides larger gate source bias applied to the PMOS pass transistor. Thus, the current drivability is arisen and the pumping speed is improved as well. In the 2V supply voltage, the pumping speed of our modified voltage doubler is arisen about 18.6% compared to that of the conventional voltage doubler. These high performance circuits in this thesis are applied in a 1-Kbit DRAM circuits. A data access time of 36ns and total power consumption 52.58mW are attained when the supply voltage is 2V. The access time of 10.3ns (22.2%) and power consumption of 6.44mW (11%) are reduced compared to that of the conventional DRAM.

Three improved operational amplifiers with low voltage and rail-to-rail constant are proposed. Two of the amplifiers are modified from the amplifier with a level shifting circuit. One improved amplifier has fewer devices, higher speed, and reduced area and the other improved amplifier is added an additional adjustable gain. The third amplifier is a floating voltage controlled voltage source (FVCVS) amplifier, which has reduced area and improved frequency response. The first two level shifting operational amplifiers are designed in a 0.5£gm UMC CMOS process. They use about half number of devices. The supply voltage is 1.3V, and the current consumes just only 22.6¢H of the original circuits. The unity gain frequency increases 56.8%. The slew rate, CMRR and PSRR are higher. The 2nd amplifier still has a rail-to-rail constant gm; however, the gm can be adjusted. The third amplifier uses the 0.35£gm UMC CMOS process with 1.2V operating voltage. The gain-bandwidth product is 53.8¢H larger than the original circuits. No frequency compensation is used and the devices are fewer. The results are obtained in HSPICE simulation.

A rail-to-rail op-amp with high stability over temperature variation at 1-V supply voltage is presented in this thesis. It incorporates a modified CM adapter and a modified bandgap reference. First, the modified CM adapter utilizes a level-shifting technique to shift the input common mode voltage of 0-1 V to the level below 0.1 V. By introducing this circuit as the front-end block of the proposed op-amp, the PMOS differential input stage can be operated appropriately with the rail-to-rail input common mode range. Second, the modified bandgap reference that combines two voltages with opposite temperature coefficients generates a temperature-insensitive bias current to the input stage. Besides, by the technique of cascading a diode with an additional BJT, the junction area of the original diodes can be reduced and in the actual application, fewer parallel-connected BJTs are needed. The two circuits are applied to the proposed op-amp operated at 1-V supply voltage in TSMC 1P4M 0.35£gm CMOS technology. At 25¢J, the dc gain is 78.9 dB and unity-gain bandwidth is 3.73 MHz. The phase margin is 42.9¢X. For the temperature from 0¢J to 75¢J, the frequency response is temperature-insensitive and the dc gain variation is 2dB. The layout view of the proposed op-amp is also presented and the area is 0.2 mm2.

Traveling-wave semiconductor optical amplifiers¡]TWSOAs¡^of symmetric and asymmetric multiple quantum wells¡]MQWs¡^have been implemented by using angled-facet structures. The asymmetric MQWs structures are designed to increase the wavelength range of the gain spectrum. The angled-facet structures, which can suppress gain ripple from FP resonance, are of 3mm-wide and 700mm-long ridge waveguides, and of different angles¡]q¡^at 3o, 5o, 7o, and 9o. From Marcuse¡¦s model, the calculation shows that the angled-facet structures have reflectivities lower than 10-4. We have also developed a single-trench process to fabricate the angled-facet TWSOAs. The l=1.55mm asymmetric structure, which shows a low epitaxial quality of large leakage current, is not suitable for SOA application. For the l=1.3mm asymmetric structure, the threshold current¡]Ith¡^at q=0o was 22.5mA, while at q=7o the Ith increased to 45mA. We have also measured the spectrum below threshold current. The differences between FP resonance peak and valley become smaller at larger q. We estimated that the reflectivity is about 0.2 at 5o. The results show that the reflectivity was decreased by angled-facet structure.

Optical communications is expanding into new applications such as infrared wireless communications; therefore, designing high performance circuits has gained considerable importance. In this dissertation a wide dynamic-range variable-gain transimpedance amplifier (TIA) is introduced. It adopts a regulated cascode (RGC) amplifier and an operational transconductance amplifier (OTA) as the feed forward gain element to control gain and improve the overload of the optical receiver. A fully-differential variable-gain TIA in a 0.35µm CMOS technology is realized. It provides a bit error rate (BER) less than 10-12 for an input current from 6µA-3mA at 3.3V power supply. For the transimpedance gain variation, from 0.1kΩ to 3kΩ, -3dB bandwidth is higher than 1.7GHz for a 0.6pF photodiode capacitance. The power dissipations for the highest and the lowest gains are 8.2mW and 24.9mW respectively. A new technique for designing uniform multistage amplifiers (MA) for high frequency applications is introduced. The proposed method uses the multi-peak bandwidth enhancement technique while it employs identical, simple and inductorless stages. It has several advantages, such as tunability of bandwidth and decreased sensitivity of amplifier stages, to process variations. While all stages of the proposed MA topology are identical, the gain-bandwidth product can be extended several times. Two six-stage amplifiers in a TSMC 0.35µm CMOS process were designed using the proposed topology. Measurements show that the gain can be varied for the first one between 16dB and 44dB within the 0.7-3.2GHz bandwidth and for the second one between 13dB and 44dB within a 1.9-3.7GHz bandwidth with less than 5.2nV/√Hz noise. Although the second amplifier has a higher gain bandwidth product, it consumes more power and occupies a wider area. A technique for capacitance multiplication is utilized to design a tunable loop filter. Current and voltage mode techniques are combined to increase the multiplication factor (M). At a high input dynamic range, M is adjustable and the capacitance multiplier performs linearly at high frequencies. Drain-source voltages of paired transistors are equalized to improve matching in the current mirrors. Measurement of a prototype loop filter IC in a 0.5µm CMOS technology shows 50µA current consumption for M=50. Where 80pF capacitance is employed, the capacitance multiplier realizes an effective capacitance varying from 1.22nF up to 8.5nF.

In this work, the circuit implementation of the front-end for Frequency Domain (FD) Sampling Receiver is presented. Shooting for two different applications, two transconductance amplifiers are designed. A high linear transconductance amplifier with 25 dBm IIP3 is proposed to form the high resolution and high sampling rate FD receiver. The whole system achieves an overall sampling rate of 2 Gs/s and resolution of 10 bits. Another low noise transconductance amplifier exploiting noise cancelling is designed to build up the FD wireless communication receiver, which is an excellent candidate for Software Define Radio (SDR) and Cognitve Radio (CR). The proposed noise cancelling scheme can suppress both thermal noise and flicker noise at the frontend. The system Noise Figure (NF) is improved by 3.28 dB. The two transconductance amplifiers are simulated and fabricated with TI 45nm CMOS technology.

The first topic of the thesis reveals a mini-invasive low-power measurement system for bladder pressure measurement. Not only can the mode of measurement be selected, the input range and amplification of instrumentation amplifier (IA) is also adjustable. The proposed system can measure the pressure in a bladder in a continuous mode. It also can monitor the pressure in a long-term mode with an automatic sleeping mechanism for power saving. The signal generated by the pressure sensor is sensed by an IA, which is then fed into the following ADC (analog-to-digital converter). The input range of the IA must be adjustable to keep the required linearity. The pressure range of the proposed system is found out to be 5 Psi with the maximum resolution of 1 cm-H2O, which covers the range of all of the known unusual bladder syndromes. The second topic is a self-disable sense technique for content addressable memory (CAM). The differential match-line sense circuit can be self-disabled to choke the charge current fed into the match line right after the comparison result is generated. Besides, the 13-T CAM cell provides the complete write, read, and comparison functions to refresh the data bit and verify its correctness before searching. The average energy consumption of the searching process is 1.872 fJ/bit/search according to thorough simulations.

In this thesis, a first order low pass square root domain filter (SRD filter) based on the novel operational transconductor amplifiers (OTAs) is presented. The SRD filter consists of a translinear filter and two OTAs. Because the conventional OTA has small input voltage swings, which violates the large signal operation of a SRD filter. We propose the novel OTA which is based on the large signal behaviors of MOSFETs, and the OTA also has large signal operation. We improve Cruz¡¦s SRD filter [22], reduce the number of the transconductors from 3 to 2, and replace Class-AB linear transconductors with the proposed OTAs. The MOSFET count of whole circuit can be reduced. Therefore, the OTAs have many advantages: wider input voltage swing, low supply voltage, low power consumption, and small chip area. The circuit has been fabricated with 0.35£gm CMOS technology. It operates with a supply voltage 1.5V and the bias current varies from 0.3£gA to 15£gA. Measurement results show that the cutoff frequency can be tuned from 1.1kHz to 35.2kHz when the external capacitance C is 1nF and the cutoff frequency can be tuned from 8.7kHz to 310.4kHz when the external capacitance C is 100pF. The total harmonic distortions are 0.93% and 0.91% when the external capacitances C are 1nF and 100pF, and the power consumption is 152.29£gW.

This thesis consists of two subjects of research: eliminating, by avoidance or removal, the effects of different types of interference on small signal recording, and a body-sensor transmitter application utilizing piezo sensors. The first topic demonstrates ECG signal and noise signal recording in the presence of various types of interference. A low-pass filter is proposed to remove power-line interference of ECG signals, and a switch between high-pass filters before amplification is proposed to avoid motion artifacts in the ECG signal. Finally, a low-cost noise recording system for educational uses that can record and analyze the noise of resistors and amplifiers in the LabVIEW program is proposed. The second topic concerns the application of a body-sensor transmitter. The sensor uses piezo film and combines the characteristics of piezo film with the characteristics of the human body and can exchange information by capacitor coupling. The signal used in the body-sensor transmitter is designed for a fixed frequency using narrow band-pass filters and is received by receivers via four methods as confirmation. Finally, the charge amplifier designed to detect signals is fabricated using a 0.35£gm 2P4M CMOS process.

In this thesis, a switched-current integrator with active amplifier feedback and dummy switch is proposed to increase the operation speed and reduce the non-ideal effects in traditional switched-current circuit. The active amplifier is designed in low gain and high bandwidth so that the oscillation can be avoided. We improve the operation speed and transmission error by the active amplifier feedback and reduce the CFT error by the dummy switch so that high resolution can be achieved. Then we apply the proposed integrator to the switched-current sigma-delta modulator. The sigma-delta modulator is simulated using TSMC 0.35£gm CMOS process with 3.3V power supply. We obtain 67dB PSNR, 66dB dynamic range(DR), and 40KHz bandwidth. The sampling frequency is 10.24MHz, the power supply is 3.3V and the power consumption is 19mW.