There is an emerging demand on techniques addressing the problem of efficiently archiving and (temporal) querying different versions of evolving semantic Web data. While systems archiving and/or temporal querying are still in their early days, we consider this a good time to discuss benchmarks for evaluating storage space efficiency for archives, retrieval functionality they serve, and the performance of various retrieval operations. To this end, we provide a blueprint on benchmarking archives of semantic data by defining a concise set of operators that cover the major aspects of querying of and interacting with such archives. Next, we introduce BEAR, which instantiates this blueprint to serve a concrete set of queries on the basis of real-world evolving data. Finally, we perform an empirical evaluation of current archiving techniques that is meant to serve as a first baseline of future developments on querying archives of evolving RDF data. (authors' abstract) / Series: Working Papers on Information Systems, Information Business and Operations

This document describes the work for the master’s thesis in Electrical Engineering carried out at Electrolux Laundry Systems. In this project the computers that control the laundry system have been compared in order to verify the performance of the whole system. Three real environment systems are analysed and two of these systems have been set up in the laboratory in order to solve the problem considered. The results show that the tested devices perform better than the device PC1, which is not fulfilling the expectations in the real environment system. Some conclusions and future work are presented.

Thesis advisor: Pierluigi Balduzzi / This dissertation consists of two essays in empirical asset pricing. Chapter I, "Skewness and Co-skewness in Bond Returns," explores skewness and co-skewness in discrete-horizon bond returns. Using data for 1976-2005, we find bond skewness is comparable to that in equities, varies with the holding period and varies over time. Speculative-grade bonds and collateralized securities have substantial negative skewness. The sign of the price of co-skewness risk in fixed income market is in general consistent with the theoretical prediction of the three-moment CAPM. Co-skewness against the market portfolio is priced differently in various bond sectors: taking a unit of co-skewness risk is rewarded with 0.43% and 2.47% per month for corporate bonds and collateralized securities, respectively. Co-skewness risk helps explain the cross section of expected bond returns when state variables such as inflation, real activity, or short term interest rates are included, or when conditioning information is exploited. Chapter II, "Modern Portfolio Management with Conditioning Information," studies models in which active portfolio managers optimize performance relative to a benchmark and utilize conditioning information unavailable to their clients. We provide explicit solutions for the optimal strategies with multiple risky assets, with or without a risk free asset, and also consider various constraints on portfolio risk or on portfolio weights. The equilibrium implications of the models are discussed. A currency portfolio example shows that the optimal solutions improve the measured performance by 53% out of sample, compared with portfolios ignoring conditioning information. / Thesis (PhD) — Boston College, 2009. / Submitted to: Boston College. Carroll School of Management. / Discipline: Finance.

Då ett index ändrar sin sammansättning kommunicerar leverantören information till marknaden om vilka bolag som väljs in och ut ur indexet. I ett senare skede verkställer leverantören förändringarna. I samband med annonseringen och revideringen har tidigare studier funnit att det förekommer priseffekter, på de bolag som omfattas av revideringen. Vissa studier menar att det är möjligt att generera abnormal avkastning genom att agera utefter de mönster som dessa priseffekter uppvisar. Syftet med denna studie är undersöka de kursrörelser som uppstår i samband med indexrevideringar och huruvida de kan utnyttjas av investerare för att generera abnormal avkastning. För att undersöka de kursrörelser som uppstår i samband med indexrevideringar genomförs en eventstudie. Studiens urval består av 160 bolag som ingår i 14 revideringar av OMX Stockholm Benchmark Index under perioden 2012 till 2018. Resultaten från denna studie tyder bland annat på att en investerare, till skillnad från andra studier på andra marknader, inte kan generera en abnormal avkastning under perioden mellan annonseringsdagen och bytesdagen. Dock finns tecken på att på att en investerare kan generera abnormal avkastning genom att agera i enlighet med mönster som uppkommer kring bytesdagen.

Com o aumento crescente das capacidades dos circuitos integrado e conseqüente complexidade das aplicações, em especial as embarcadas, um requisito tem se tornado fundamental no desenvolvimento desses sistemas: ferramentas de desenvolvimento cada vez mais acessíveis aos engenheiros, permitindo, por exemplo, que um programa escrito em linguagem C possa ser convertido diretamente em hardware. Os FPGAs (Field Programmable Gate Array), elemento fundamental na caracterização de computação reconfigurável, é um exemplo desse crescimento, tanto em capacidade do CI como disponibilidade de ferramentas. Esse projeto teve como objetivos: estudar algumas ferramentas de conversão C, C++ ou Java para hardware reconfigurável; estudar benchmarks a serem executadas nessas ferramentas para obter desempenho das mesmas, e ter o domínio dos conceitos na conversão de linguagens de alto nível para hardware reconfigurável. A plataforma utilizada no projeto foi a da empresa Xilinx XUP V2P / With the growing capacities of Integrated Circuits (IC) and the complexity of the applications, especially in embedded systems, there are now requisites for developing tools that convert algorithms C direct into the hardware. As a fundamental element to characterize Reconfigurable Computing, FPGA (Field Programmable Gate Array) is an example of those CIs, as well as the tools that have been developed. In this project we present different tools to convert C into the hardware. We also present benchmarks to be executed on those tools for performance analysis. Finally we conclude the project presenting results relating the experience to implement C direct into the hardware. The Xilinx XUP V2P platform was used in the project

Esta dissertação de mestrado introduz um conjunto de algoritmos baseados em grafos para a obtenção de circuitos VLSI com um número reduzido de transistores utilziando células simples. Esses algoritmos têm um foco principal na minimização do número de nodos em representações AIG e mapear essa estrutura otimizada utilizando células simples (NAND2 e NOR2) com um número mínimo de inversores. Devido à minimização de nodos, o AIG tem um alto compartilhamento lógico, o que pode derivar circuitos intermediários contendo células com fanouts infactíveis para os nodos tecnológicos atuais. De forma a resolver essas ocorrências, o circuito intermediário é submetido a um algoritmo para limitação de fanout. Os algoritmos propostos foram aplicados num conjunto de circuitos de benchmark e os resultados obtidos mostram a utilidade do método. Os circuitos resultantes tiveram, em média, 32% menos transistores do que as referências anteriores em números de transistores utilizando células simples. Adicionalmente, quando comparando esses resultados com trabalhos que utilizam células complexas, nossos números demonstraram que abordagens anteriores estão algumas vezes longe do número mínimo de transistores que pode ser obtido com o uso eficiente de uma biblioteca reduzida de células, composta por poucas células simples. Os circuitos baseados em células simples obtidos com a aplicação dos algoritmos proposto neste trabalho apresentam um menor número de transistores em muitos casos quando comparados aos resultados previamente publicados utilizando células complexas (CMOS estático e PTL). / This master’s thesis introduces a set of graph-based algorithms for obtaining reduced transistor count VLSI circuits using simple cells. These algorithms are mainly focused on minimizing node count in AIG representations and mapping this optimized AIG using simple cells (NAND2 and NOR2) with a minimal number of inverters. Due to the AIG node count minimization, the logic sharing is probably highly present in the optimized AIG, what may derive intermediate circuits containing cells with unfeasible fanout in current technology nodes. In order to fix these occurrences, this intermediate circuit is subjected to an algorithm for fanout limitation. The proposed algorithms were applied over a set of benchmark circuits and the obtained results have shown the usefulness of the method. The circuits generated by the methods proposed herein have, in average, 32% less transistor than the previous reference on transistor count using simple cells. Additionally, when comparing the presented results in terms of transistor count against works advocating for complex cells, our results have demonstrated that previous approaches are sometimes far from the minimum transistor count that can be obtained with the efficient use of a reduced cell library composed by only a few number of simple cells. The simple-cells-based circuits obtained after applying the algorithms proposed herein have presented a lower transistor count in many cases when compared to previously published results using complex (static CMOS and PTL) cells.

Um dado por si só não possui valor algum, a menos que ele seja interpretado, contextualizado e agregado com outros dados, para então possuir valor, tornando-o uma informação. Em algumas classes de aplicações o valor não está apenas na informação, mas também na velocidade com que essa informação é obtida. As negociações de alta frequência (NAF) são um bom exemplo onde a lucratividade é diretamente proporcional a latência (LOVELESS; STOIKOV; WAEBER, 2013). Com a evolução do hardware e de ferramentas de processamento de dados diversas aplicações que antes levavam horas para produzir resultados, hoje precisam produzir resultados em questão de minutos ou segundos (BARLOW, 2013). Este tipo de aplicação tem como característica, além da necessidade de processamento em tempo-real ou quase real, a ingestão contínua de grandes e ilimitadas quantidades de dados na forma de tuplas ou eventos. A crescente demanda por aplicações com esses requisitos levou a criação de sistemas que disponibilizam um modelo de programação que abstrai detalhes como escalonamento, tolerância a falhas, processamento e otimização de consultas. Estes sistemas são conhecidos como Stream Processing Systems (SPS), Data Stream Management Systems (DSMS) (CHAKRAVARTHY, 2009) ou Stream Processing Engines (SPE) (ABADI et al., 2005). Ultimamente estes sistemas adotaram uma arquitetura distribuída como forma de lidar com as quantidades cada vez maiores de dados (ZAHARIA et al., 2012). Entre estes sistemas estão S4, Storm, Spark Streaming, Flink Streaming e mais recentemente Samza e Apache Beam. Estes sistemas modelam o processamento de dados através de um grafo de fluxo com vértices representando os operadores e as arestas representando os data streams. Mas as similaridades não vão muito além disso, pois cada sistema possui suas particularidades com relação aos mecanismos de tolerância e recuperação a falhas, escalonamento e paralelismo de operadores, e padrões de comunicação. Neste senário seria útil possuir uma ferramenta para a comparação destes sistemas em diferentes workloads, para auxiliar na seleção da plataforma mais adequada para um trabalho específico. Este trabalho propõe um benchmark composto por aplicações de diferentes áreas, bem como um framework para o desenvolvimento e avaliação de SPSs distribuídos. / Recently a new application domain characterized by the continuous and low-latency processing of large volumes of data has been gaining attention. The growing number of applications of such genre has led to the creation of Stream Processing Systems (SPSs), systems that abstract the details of real-time applications from the developer. More recently, the ever increasing volumes of data to be processed gave rise to distributed SPSs. Currently there are in the market several distributed SPSs, however the existing benchmarks designed for the evaluation this kind of system covers only a few applications and workloads, while these systems have a much wider set of applications. In this work a benchmark for stream processing systems is proposed. Based on a survey of several papers with real-time and stream applications, the most used applications and areas were outlined, as well as the most used metrics in the performance evaluation of such applications. With these information the metrics of the benchmark were selected as well as a list of possible application to be part of the benchmark. Those passed through a workload characterization in order to select a diverse set of applications. To ease the evaluation of SPSs a framework was created with an API to generalize the application development and collect metrics, with the possibility of extending it to support other platforms in the future. To prove the usefulness of the benchmark, a subset of the applications were executed on Storm and Spark using the Azure Platform and the results have demonstrated the usefulness of the benchmark suite in comparing these systems.

Modern applications generate a massive amount of data that is challenging to process or analyse. Graph algorithms have emerged as a solution for the analysis of this data because they can represent the entities participating in the generation of large scale datasets in terms of vertices and their relationships in terms of edges. Graph analysis algorithms are used for finding patterns within these relationships, aiming to extract information to be further analysed. The breadth-first search (BFS) is one of the main graph search algorithms used for graph analysis and its optimisation has been widely researched using different parallel computers. However, the BFS parallelisation has been shown to be chal- lenging because of its inherent characteristics, including irregular memory access patterns, data dependencies and workload imbalance, that limit its scalability. This thesis investigates the optimisation of the BFS on the Xeon Phi, which is a modern parallel architecture provided with an advanced vector processor using a self-created development framework integrated with the Graph 500 benchmark. As a result, optimised parallel versions of two high-level algorithms for BFS were created using vectorisation, starting with the conventional top-down BFS algorithm and, building on this, leading to the hybrid BFS algorithm. The best implementations resulted in speedups of 1.37x and 1.33x, for a one million vertices graph, compared to the state-of-the-art, respectively. The hybrid BFS algorithm can be further used by other graph analysis algorithms and the lessons learned from vectorisation can be applied to other algorithms targeting the existing and future models of the Xeon Phi and other advanced vector architectures.

Este trabalho, de caráter exploratório-descritivo, versa sobre a gestão de risco, mostrando uma visão teórica da mitigação de riscos no ambiente corporativo. Inicialmente aborda os aspectos genéricos da variável risco e seu entorno, para, então, discorrer sobre o tema, mediante a apresentação de suas fases e dimensões, direcionando-se à governança e à gestão por processo de negócio. Esse referencial orienta-se à compreensão da visão sistêmica e da competitividade, à relevância de se explicitarem os processos e outras determinantes, como a cultura, os estímulos comportamentais e principais condutas empregadas no mercado futuro e de opções, pela seleção de derivativos. Os principais resultados remetem a excelência de metodologias, como fator-chave para o crescimento, por meio do uso de modelos consistentes, provenientes de instituições especializadas e da recomendação de profissionais, que dominam o assunto. O principal ganho verificado indica que o processo de gestão de risco deve ser incorporado à cultura organizacional, em sua totalidade, e que esse tipo de conhecimento se constrói por intermédio de ações conjuntas, instrumentos adequados, tecnologia e persistência à expertise requerida. / This work, of exploratory and descriptive character, deals with risk management, showing a theoretical view of risk mitigation in the corporate environment. Initially made an approach of generic aspects from risk variable and its surroundings, to then discuss the issue, by presenting its phases and dimensions, driving to the governance and management of business process. This reference guides to the understanding of the systemic vision and competitiveness, the relevance of explicit the processes and other determinants, such as culture, behavioral stimuli and main conduits employed in the market of futures and options, the selection of derivatives. The main results refer to excellence methodologies, like as a key-factor for growth through the consistent use of models, from specialized agencies and the recommendation of professionals who have mastered the subject. The main gain occurred indicates that the process of risk management should be incorporated into the organizational culture, in its entirety, and that such knowledge is built through joint actions, appropriate tools, technology and persistence to the expertise required.

The diploma thesis is focused on identification and partial quantification of tax reliefs of personal income tax in 2011. This diploma thesis is divided into 4 sections. The first one contains view of existing literature and research in the field of tax reliefs. The second one is theoretical and it is dedicated to the broad theory of tax reliefs and their operation in the countries OECD. The third one is theoretical-analytical and is focused on the view of definition among the particular countries and subsequent identification of tax reliefs in Australia and Canada. The main section of the diploma thesis is fourth part. This analytical part contains the identification and quantification of some provisions of tax reliefs of personal income tax in the Czech Republic.