The miniaturization of dc–dc switch-mode power supplies (SMPS) is of a key importance in volume-sensitive portable devices, such as cell phones, tablet computers, and digital cameras. In these systems, multiple SMPS are required to provide well regulated voltage and power to various electronic components such as the central processing unit (CPU) and random-access memory (RAM). The combined volume, weight, and surface area footprint of these SMPS is usually the largest component. Traditionally, SMPS volume reduction has been achieved through increased switching frequencies; however, for power-sensitive applications this is undesirable due to the increased switching losses. This thesis presents two alternative, power-efficient, SMPS miniaturization methods: one control and one topology based. The presented controller recovers from load transients with virtually minimum possible output voltage deviation, reducing the reactive component size. The controller utilizes a simple algorithm, requiring no knowledge of the converter parameters and virtually no processing power. The simplicity of the control concept enabled the design of an area and power efficient integrated circuit (IC) implementation. The entire IC is implemented in a CMOS 0.18µm process on a 0.26 mm2 silicon area, which is comparable to the state-of-the-art analog solutions. For the experimental system the deviation (output capacitor size) is about four times smaller than that of a fast PID compensator having a 1/10th of the switching frequency bandwidth. The second solution is a complementary converter topology that has a smaller output filter volume, improved dynamic response, and lower switching losses compared to the state-of-the-art solutions. To reduce the volume and switching losses, the input-to-output voltage difference is decreased with a capacitive attenuator that replaces the input filter capacitor and has approximately the same volume. Both the attenuator and the downstream buck converter share the same set of switches, minimizing conduction losses. A single multi-mode digital controller governs operation of both stages, seamlessly regulating the output and input center-tap voltages. Experiments with a 5–1.5-V, 2.5-A, 1-MHz prototype show that, compared to the conventional buck, the merged topology has 43% smaller inductor, 36% smaller output capacitor, up to 30% lower power losses, and a 25% faster transient response.

This thesis is concerned with the sampled-data control of non-linear continuous-time systems. Sampled-data systems are present in all computer controlled, hybrid or embedded systems. The design and computation of suitable digital controllers represent unavoidable tasks since both continuous and discrete-time components interact. The basic framework of this work takes part of a wide research activity performed by S. Monaco and D. Normand-Cyrot regarding non-linear sampled-data systems. The underlying idea is to design digital controllers that recover certain continuous-time properties that are usually degraded through sampling as it is the case when continuous-time controllers are implemented by means of zero-order holder devices (emulated control). This thesis brings contributions into three different directions. The first one regards theoretical developments: a new digital backstepping-like strategy design for strict-feedback systems is proposed. This method is compared with other strategies proposed in the literature. The second contribution is the development of a control designer and of a simulation toolbox (in Matlab) for non-linear sampled-data systems. This toolbox includes different digital design strategies such as: multi-rate control, input-output/Lyapunov matching, digital backstepping design, etc. The third contribution concerns several case studies conducted to highlight the performances of the sampled-data controller designs, computed by the means of the software toolbox. Experimental and simulation results are described for various real examples especially in the area of electrical and mechanical processes.

This thesis presents a distributed power-management architecture for concentrating photovoltaic (CPV) systems. Specifically, the Δ-conversion scheme with voltage equalization is analyzed and verified for the CPV system from Morgan Solar, Inc. This architecture uses inverting buck-boost converters, denoted Δ-converters, which equalize the voltages of neighbouring CPV cells in a series-connected string of cells and improve the systems tolerance to parameter variations. The power benefits of Δ-conversion and the Δ-converter current distributions are investigated using statistical simulations. The effectiveness of Δ-conversion in the presence of randomly distributed mismatches is demonstrated, and current cascading is identified as the main design challenge. The Δ-converter is modelled and compensated using Middlebrook's Extra Element Theorem. Analysis of measured data from a six-cell CPV system demonstrate the benefits of Δ-conversion under realistic scenarios. Experimental results from prototype systems show up to 31% power benefits in the presence of mismatches.

[Truncated abstract] This thesis studies current sensing techniques that are designed to meet the requirements for the next generation of power converters. Power converters are often standardised, so that they can be replaced with a model from another manufacturer without an expensive system redesign. For this reason, the power converter market is highly competitive and relies on cutting-edge technology, which increases power conversion efficiency and power density. High power density and conversion efficiency reduce the system cost, and thus make the power converter more attractive to the customer. Current sensing is a vital task in power converters, where the current information is required for monitoring and control purposes. In order to achieve the above-mentioned goals, existing current sensing techniques have to be improved in terms of cost, power loss and size. Simultaneously, current information needs to be increasingly available in digital form to enable digital control, and to allow the digital transmission of the current information to a centralised monitoring and control unit. All this requires the output signal of a particular current sensing technique to be acquired by an analogue-to-digital converter, and thus the output voltage of the current sensor has to be sufficiently large. This thesis thoroughly reviews contemporary current sensing techniques and identifies suitable techniques that have the potential to meet the performance requirements of the next-generation of power converters. After the review chapter, three novel current sensing techniques are proposed and investigated: 1) The usefulness of the resistive voltage drop across a copper trace, which carries the current to be measured, to detect electrical current is evaluated. Simulations and experiments confirm that this inherently lossless technique can measure high currents at reasonable measurement bandwidth, good accuracy and low cost if the sense wires are connected properly. 2) Based on the mutual inductance theory found during the investigation of the copper trace current sense method, a modification of the well-known lossless inductor current sense method is proposed and analysed. This modification involves the use of a coupled sense winding that significantly improves the frequency response. Hence, it becomes possible to accurately monitor the output current of a power converter with the benefits of being lossless, exhibiting good sensitivity and having small size. 3) A transformer based DC current sense method is developed especially for digitally controlled power converters. This method provides high accuracy, large bandwidth, electrical isolation and very low thermal drift. Overall, it achieves better performance than many contemporary available Hall Effect sensors. At the same time, the cost of this current sensor is significantly lower than that of Hall Effect current sensors. A patent application has been submitted. .... The current sensing techniques have been studied by theory, hardware experiments and simulations. In addition, the suitability of the detection techniques for mass production has been considered in order to access the ability to provide systems at low-cost.

This Thesis is concerned with the approximation of high order controllers or the controller reduction problem. We firstly consider approximating high-order controllers by low order controllers based on the closed-loop system approximation. By approximating the closed-loop system transfer function, we derive a new parametrized double-sided frequency weighted model reduction problem. The formulas for the input and output weights are derived using three closed-loop system configurations: (i) by placing a controller in cascade with the plant, (ii) by placing a controller in the feedback path, and (iii) by using the linear fractional transformation (LFT) representation. One of the weights will be a function of a free parameter which can be varied in the resultant frequency weighted model reduction problem. We show that by using standard frequency weighted model reduction techniques, the approximation error can be easily reduced by varying the free parameter to give more accurate low order controllers. A method for choosing the free parameter to get optimal results is being suggested. A number of practical examples are used to show the effectiveness of the proposed controller reduction method. We have then considered the relationships between the closed-loop system con gurations which can be expressed using a classical control block diagram or a modern control block diagram (LFT). Formulas are derived to convert a closed-loop system represented by a classical control block diagram to a closed-loop system represented by a modern control block diagram and vice versa.

Made available in DSpace on 2014-06-11T19:30:50Z (GMT). No. of bitstreams: 0 Previous issue date: 2008-12-15Bitstream added on 2014-06-13T19:40:17Z : No. of bitstreams: 1 soares_jo_dr_ilha.pdf: 2703269 bytes, checksum: f51d4821a6cb2c9c52cf4d25420d0c39 (MD5) / Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq) / O objetivo deste trabalho é a concepção de uma lógica de controle digital com modulação por histerese variável usando um dispositivo programável FPGA (Field Programmable Gate Array) e linguagem de descrição de hardware VHDL (Hardware Description Language), aplicada em um retificador trifásico híbrido para a obtenção do Fator de Potência (FP) de entrada quase unitário. O Retificador Trifásico Híbrido (RTH) é uma estrutura composta por um retificador a diodos de 6 pulsos e por três retificadores monofásicos SEPIC conectados em paralelo. O controle digital proposto é capaz de impor a forma de onda das correntes de entrada, obtendose Distorção Harmônica Total (DHT) reduzida e fator de potência (FP) quase unitário, sendo que nesta condição, os retificadores monofásicos SEPIC conduzirão no máximo 33% da potência ativa total. Além disso, o uso de FPGAs dará ao Retificador Híbrido Trifásico uma flexibilidade adicional na operação, podendo substituir vários sistemas de múltiplos pulsos convencionais e reduzir custos para o sistema de controle por eliminar a confecção de circuitos complexos de controle analógico, para os conversores chaveados. Neste trabalho, apresenta-se uma análise detalhada e metodologia de projeto para o Retificador Híbrido Trifásico (RTH) que possibilita relacionar o valor da DHT das correntes de entrada com os valores das potências média e aparente processadas pelas estruturas controlada e não-controlada, podendo-se prever o desempenho global do sistema. Serão apresentados detalhes sobre o funcionamento do código VHDL e da modulação por histerese variável empregada e, por fim, os resultados experimentais de um protótipo implementado para 3,0 kW. O código VHDL desenvolvido, associado à lógica de controle digital proposta, foi implementado através de um dispositivo FPGA da Xilinx – Spartan XC2S200E, módulo digilab-D2E... / The objective of this work is the development of a digital control logic with variable hysteresis modulation using a FPGA (Field Programmable Gate Array) device and VHDL (Hardware Description Language), applied at a hybrid three-phase rectifier in order to obtain an almost unitary input power factor (PF). The hybrid three-phase rectifier is a structure composed by parallel SEPIC controlled single-phase rectifiers connected to each leg of a standard 6-pulses uncontrolled diode rectifier. The proposed digital control is capable to impose input current waveforms, resulting in a reduced THD (Total Harmonic Distortion) and almost unitary input power factor, being that in this operation condition the parallel SEPIC single-phase rectifiers will process only 33.0 % of total active power. Moreover, the use of FPGA will provide to hybrid three-phase rectifier an additional flexbility in its operation, making possible the replacement of same conventional systems of multiple pulses and reducing costs for the control system, through the elimination of complex analogical circuitry used in the controlled converters. In this work is presented a detailed analysis and design methodology to hybrid threephase rectifier that establishes a relationship between the THD imposed to line input currents, with the average and apparent powers processed through controlled and uncontrolled structures, making possible to know previously the global system performance. It will be presented details about the operation of the VHDL code and variable hysteresis modulation proposed, and finally the experimental results from an implemented 3.0 kW prototype. The developed VHDL code, considering the proposed digital control logic, was implemented through a Xilinx’s FPGA device – Spartan XC2S200E, digilab-D2E module, whose generated control signals resulted in input currents with practically sinusoidal waveforms... (Complete abstract click electronic access below)

Made available in DSpace on 2016-12-12T20:27:38Z (GMT). No. of bitstreams: 1 Aldo Zanella Junior.pdf: 3746857 bytes, checksum: 7ff548689a89fd8090402ad4891a23c1 (MD5) Previous issue date: 2015-07-09 / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / This work introduces the report of performed studies in order to evaluate the applicability of generalized predictive control (GPC) to several plants. The main goal is to analyze the GPC performance in processes with different features, analyzing the influence of its tuning parameters. The study is justified by the fact that GPC presents itself as a generalized solution for several classes of processes, which are becoming increasingly complex and demanding for traditional controllers to handle. For the purpose to prove this proposal of GPC, it was performed several tests with plants of different orders and response characteristics, real and simulated, varying controller tuning parameters and measuring some quality indices. It was evaluated the influence of tuning parameters and it was made a report of conclusions that was reached. Through obtained results, it is shown that GPC satisfies the proposal and presents favorable results. / Esta dissertação traz o relato do estudo realizado a fim de avaliar a aplicabilidade do controlador preditivo generalizado (GPC) em plantas diversas. O objetivo principal é analisar o desempenho do GPC em processos com diferentes características, analisando a influência dos seus parâmetros de sintonia. O estudo se justifica pelo fato de que o GPC apresenta-se como uma solução generalizada para diversos tipos de processos, os quais estão se tornando cada vez mais complexos e com maiores exigências para o controlador. A fim de comprovar essa proposta do GPC, realizou-se inúmeros ensaios com plantas com respostas e ordem diferentes, reais e simuladas, variando-se os parâmetros de sintonia do controlador e medindo-se alguns parâmetros de qualidade. Avaliou-se a influência dos parâmetros de sintonia e fez-se um relato das conclusões a que se chegou. Através dos resultados obtidos, mostra-se que o GPC corresponde ao que se propõe para as plantas testadas e apresenta resultados favoráveis.

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / This work presents as contributions a design procedure for controllers applied to single-phase uninterruptible power supplies and the certification of the closed-loop stability and performance using linear matrix inequalities. The design procedure takes into account the IEC62040-3 standard to select the components of an internal model principle based controller that guarantees tracking of sinusoidal reference and rejection of disturbances from typical nonlinear loads. It also takes into account the suitability of the controller for implementation in fixed point digital signal processors, including constraints on data representation and transport delay. A discrete linear quadratic regulator is used to ensure to the closed-loop system satisfactory transient responses and steady-state performance. The proposed design procedure is applied to a prototype of the output stage of an uninterruptible power supply, with simulation and experimental results that totally comply with the requirements of the IEC62040-3 standard. Finally, the performance of closed-loop system is certified by means of linear matrix inequalities that allow to determine the capacity of rejection of disturbances under time-varying or time invariant parametric uncertainties, providing new information on limits of performance for this class of systems. / Este trabalho apresenta como contribuições um procedimento de projeto para controladores aplicados a fontes ininterruptas de energia monofásicas e a certificação da estabilidade e do desempenho em malha fechada utilizando desigualdades matriciais lineares. O procedimento de projeto leva em conta a norma IEC62040-3 para a escolha das componentes de um controlador baseado no princípio do modelo interno, que garante rastreamento da referência senoidal e rejeição de distúrbios provenientes de cargas não lineares típicas. Também leva em conta a adequação do controlador à implementação em processadores digitais de ponto fixo, incluindo restrições na representação dos dados e de atraso de transporte. Um regulador linear quadrático discreto é utilizado para garantir ao sistema em malha fechada respostas transitórias e desempenho em regime permanente satisfatórios. O procedimento de projeto proposto é aplicado a um protótipo de estágio de saída de uma fonte ininterrupta de energia, com resultados de simulação e experimentais que atendem completamente às exigências da norma IEC62040-3. Finalmente, o desempenho do sistema em malha fechada é certificado por meio de desigualdades matriciais lineares que permitem determinar a capacidade de rejeição de distúrbios sob incertezas paramétricas variantes no tempo ou invariantes no tempo, fornecendo novas informações sobre limites de desempenho para essa classe de sistemas.

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / This master s thesis proposes a three-phase transformerless double-conversion UPS with digital control system and reduced overall cost. The topology is composed of an input stage, a battery bank, an inverter, an auxiliary circuit and transfer switches. The input stage assumes the three-phase rectifier function with LCL filter in normal operation mode and is responsible for discharge the battery bank in backup mode. This configuration reduces the system cost since an available circuit is used to discharge the battery bank. In conventional double-conversion UPS topologies the input stage remains inactive during the backup mode and an additional circuit is employed for this purpose. The auxiliary circuit is formed by an inductor and a switching leg and is used as a battery charger during normal operation mode and is additionally used to balance the bus capacitors voltages in backup mode. In this configuration, the auxiliary circuit can be designed for only a fraction of the UPS rated power, also providing lower total system cost. Transfer switches change the configuration of the input stage and the auxiliary circuit according to the UPS operating mode. The detailed operation of the topology, modelling, digital control structure, and the results obtained by simulation are showed. Finally a 20 kVA prototype is implemented and experimental results are acquired for the validation of the employed design methodology as well as the proposed circuit functionality. / Esta dissertação de mestrado propõem uma topologia de fonte ininterrupta de energia (UPS - Uninterruptible Power Supplies) trifásica de dupla conversão sem transformador com custo reduzido e sistema de controle digital. A UPS proposta é composta por um estágio de entrada, um banco de baterias, um inversor, um circuito auxiliar e chaves de transferência. O estágio de entrada assume a função de retificador trifásico com filtro LCL em modo normal de operação da UPS e é responsável pela descarga do banco de baterias em modo bateria de operação. Esta configuração reduz o custo do sistema, pois permite que seja aproveitado um circuito disponível e dimensionado para a potência nominal da UPS para a descarga do banco de baterias. Em topologias convencionais de UPSs de dupla conversão o estágio de entrada permanece ocioso durante este modo de operação e um circuito adicional é empregado para este fim. O circuito auxiliar é formado por um indutor e um braço de interruptores e é utilizado como carregador de baterias em modo normal de operação e adicionalmente é utilizado para realizar o equilíbrio das tensões dos capacitores de barramento em modo bateria. Com esta configuração, o circuito auxiliar pode ser dimensionado para apenas uma fração da potência nominal da UPS, propiciando também a redução do custo total do sistema. As chaves de transferência alteram as configurações do estágio de entrada e do circuito auxiliar de acordo com o modo de operação da UPS. É apresentada a operação detalhada da topologia, a modelagem, a estrutura de controle digital utilizada e os resultados obtidos via simulação. Por fim, um protótipo de 20 kVA é implementado e resultados experimentais são adquiridos para a validação da metodologia de projeto empregada bem como da funcionalidade do circuito proposto.

Orientador: Carlos Alberto Canesin / Banca: Falcondes Jose Mendes de Seixas / Banca: Flávio Alessandro Serrão Gonçalves / Banca: Luiz Carlos de Freitas / Banca: João Batista Vieira Junior / Resumo: O objetivo deste trabalho é a concepção de uma lógica de controle digital com modulação por histerese variável usando um dispositivo programável FPGA (Field Programmable Gate Array) e linguagem de descrição de hardware VHDL (Hardware Description Language), aplicada em um retificador trifásico híbrido para a obtenção do Fator de Potência (FP) de entrada quase unitário. O Retificador Trifásico Híbrido (RTH) é uma estrutura composta por um retificador a diodos de 6 pulsos e por três retificadores monofásicos SEPIC conectados em paralelo. O controle digital proposto é capaz de impor a forma de onda das correntes de entrada, obtendose Distorção Harmônica Total (DHT) reduzida e fator de potência (FP) quase unitário, sendo que nesta condição, os retificadores monofásicos SEPIC conduzirão no máximo 33% da potência ativa total. Além disso, o uso de FPGAs dará ao Retificador Híbrido Trifásico uma flexibilidade adicional na operação, podendo substituir vários sistemas de múltiplos pulsos convencionais e reduzir custos para o sistema de controle por eliminar a confecção de circuitos complexos de controle analógico, para os conversores chaveados. Neste trabalho, apresenta-se uma análise detalhada e metodologia de projeto para o Retificador Híbrido Trifásico (RTH) que possibilita relacionar o valor da DHT das correntes de entrada com os valores das potências média e aparente processadas pelas estruturas controlada e não-controlada, podendo-se prever o desempenho global do sistema. Serão apresentados detalhes sobre o funcionamento do código VHDL e da modulação por histerese variável empregada e, por fim, os resultados experimentais de um protótipo implementado para 3,0 kW. O código VHDL desenvolvido, associado à lógica de controle digital proposta, foi implementado através de um dispositivo FPGA da Xilinx - Spartan XC2S200E, módulo digilab-D2E... (Resumo completo, clicar acesso eletrônico abaixo) / Abstract: The objective of this work is the development of a digital control logic with variable hysteresis modulation using a FPGA (Field Programmable Gate Array) device and VHDL (Hardware Description Language), applied at a hybrid three-phase rectifier in order to obtain an almost unitary input power factor (PF). The hybrid three-phase rectifier is a structure composed by parallel SEPIC controlled single-phase rectifiers connected to each leg of a standard 6-pulses uncontrolled diode rectifier. The proposed digital control is capable to impose input current waveforms, resulting in a reduced THD (Total Harmonic Distortion) and almost unitary input power factor, being that in this operation condition the parallel SEPIC single-phase rectifiers will process only 33.0 % of total active power. Moreover, the use of FPGA will provide to hybrid three-phase rectifier an additional flexbility in its operation, making possible the replacement of same conventional systems of multiple pulses and reducing costs for the control system, through the elimination of complex analogical circuitry used in the controlled converters. In this work is presented a detailed analysis and design methodology to hybrid threephase rectifier that establishes a relationship between the THD imposed to line input currents, with the average and apparent powers processed through controlled and uncontrolled structures, making possible to know previously the global system performance. It will be presented details about the operation of the VHDL code and variable hysteresis modulation proposed, and finally the experimental results from an implemented 3.0 kW prototype. The developed VHDL code, considering the proposed digital control logic, was implemented through a Xilinx's FPGA device - Spartan XC2S200E, digilab-D2E module, whose generated control signals resulted in input currents with practically sinusoidal waveforms... (Complete abstract click electronic access below) / Doutor