With the rapid development of microprocessor and semiconductor technology, industry continues to update the requirements for power supplies. For telecommunication and computing system applications, power supplies require increasing current level while the supply voltage keeps decreasing. For example, the Intel's CPU core voltage decreased from 2 volt in 1999 to 1 volt in 2005 while the supply current increased from 20A in 1999 to up to 100A in 2005. As a result, low-voltage high-current high efficiency dc-dc converters with high power-density are demanded for state-of-the-art applications and also the future applications. Half-bridge dc-dc converter with current-doubler rectification is regarded as a good topology that is suitable for high-current low-voltage applications. There are three control schemes for half-bridge dc-dc converters and in order to provide a valid unified analog model for optimal compensator design, the analog state-space modeling and small signal modeling are studied in the dissertation and unified state-space and analog small signal model are derived. In addition, the digital control gains a lot of attentions due to its flexibility and re-programmability. In this dissertation, a unified digital small signal model for half-bridge dc-dc converter with current doubler rectifier is also developed and the digital compensator based on the derived model is implemented and verified by the experiments with the TI DSP chip. In addition, although current doubler rectifier is widely used in industry, the key issue is the current sharing between two inductors. The current imbalance is well studied and solved in non-isolated multi-phase buck converters, yet few discusse this issue in the current doubler rectification topology within academia and industry. This dissertation analyze the current sharing issue in comparison with multi-phase buck and one modified current doubler rectifier topology is proposed to achieve passive current sharing. The performance is evaluated with half bridge dc-dc converter; good current sharing is achieved without additional circuitry. Due to increasing demands for high-efficiency high-power-density low-voltage high current topologies for future applications, the thermal management is challenging. Since the secondary-side conduction loss dominates the overall power loss in low-voltage high-current isolated dc-dc converters, a novel current tripler rectification topology is proposed. Theoretical analysis, comparison and experimental results verify that the proposed rectification technique has good thermal management and well-distributed power dissipation, simplified magnetic design and low copper loss for inductors and transformer. That is due to the fact that the load current is better distributed in three inductors and the rms current in transformer windings is reduced. Another challenge in telecommunication and computing applications is fast transient response of the converter to the increasing slew-rate of load current change. For instance, from Intel's roadmap, it can be observed that the current slew rate of the age regulator has dramatically increased from 25A/uS in 1999 to 400A/us in 2005. One of the solutions to achieve fast transient response is secondary-side control technique to eliminate the delay of optocoupler to increase the system bandwidth. Active-clamp half bridge dc-dc converter with secondary-side control is presented and one industry standard 16th prototype is built and tested; good efficiency and transient response are shown in the experimental section. However, one key issue for implementation of secondary-side control is start-up. A new zero-voltage-switching buck-flyback isolated dc-dc converter with synchronous rectification is proposed, and it is only suitable for start-up circuit for secondary-side controlled converter, but also for house-keeping power supplies and standalone power supplies requiring multi-outputs.

Recent research activities focused on improving the steady-state as well as the dynamic behavior of DC-DC converters for proper system performance, by proposing different design methods and control approaches with growing tendency to using digital implementation over analog practices. Because of the rapid advancement in semiconductors and microprocessor industry, digital control grew in popularity among PWM converters and is taking over analog techniques due to availability of fast speed microprocessors, flexibility and immunity to noise and environmental variations. Furthermore, increased interest in Field Programmable Gate Arrays (FPGA) makes it a convenient design platform for digitally controlled converters. The objective of this research is to propose new digital control schemes, aiming to improve the steady-state and transient responses of a high switching frequency FPGA-based digitally controlled DC-DC converters. The target is to achieve enhanced performance in terms of tight regulation with minimum power consumption and high efficiency at steady-state, as well as shorter settling time with optimal over- and undershoots during transients. The main task is to develop new and innovative digital PWM techniques in order to achieve: 1. Tight regulation at steady-state: by proposing high resolution DPWM architecture, based on Digital Clock Management (DCM) resources available on FPGA boards. The proposed architecture Window-Masked Segmented Digital Clock Manager-FPGA based Digital Pulse Width Modulator Technique, is designed to achieve high resolution operating at high switching frequencies with minimum power consumption. 2. Enhanced dynamic response: by applying a shift to the basic saw-tooth DPWM signal, in order to benefit from the best linearity and simplest architecture offered by the conventional counter-comparator DPWM. This proposed control scheme will help the compensator reach the steady-state value faster. Dynamically Shifted Ramp Digital Control Technique for Improved Transient Response in DC-DC Converters, is projected to enhance the transient response by dynamically controlling the ramp signal of the DPWM unit.

No description available.

No description available.

Power electronics applications in high power are normally large, expensive, spatially distributed systems. These systems are typically complex and have multiple functions. Due to these properties, the control algorithm and its implementation are challenging, and a different approach is needed to avoid customized solutions to every application while still having reliable sensor measurements and converter communication and control. This thesis proposes a synchronous digital control architecture that allows for the communication and control of devices via a fiber optic communication ring using digital technology. The proposed control architecture is a multidisciplinary approach consisting of concepts from several areas of electrical engineering. A review of the state of the art is presented in Chapter 2 in the areas of power electronics, fieldbus control networks, and digital design. A universal controller is proposed as a solution to the hardware independent control of these converters. Chapter 3 discusses how the controller was specified, designed, implemented, and tested. The power level specific hardware is implemented in modules referred to as hardware managers. A design for a hardware manager was previously implemented and tested. Based on these results and experiences, an improved hardware manager is specified in Chapter 4. A fault tolerant communication protocol is specified in Chapter 5. This protocol is an improvement on a previous version of the protocol, adding benefits of improved synchronization, multimaster support, fault tolerant structure with support for hot-swapping, live insertion and removals, a variable ring structure, and a new network based clock concept for greater flexibility and control. Chapter 6 provides a system demonstration, verifying the components work in configurations involving combinations of controllers and hardware managers to form applications. Chapter 7 is the conclusion. VHDL code is included for the controller, the hardware manager, and the protocol. Schematics and manufacturing specifications are included for the controller. / Master of Science

Digitally controlled switching DC-DC converters have recently emerged as an attractive alternative to conventional switching converters based on analog control techniques. This research focuses on eliminating the issues associated with the state of the art switching converters by proposing three novel control techniques: (1) a digitally controlled Buck-Boost converter uses a fully synthesized constant ON/OFF time-based fractional-N controller to regulate the output over a 3.3V-to-5.5V input voltage range and provides seamless transition from buck to buck-boost modes (2) a hysteretic buck converter that employs a highly digital hybrid voltage/current mode control to regulate output voltage and switching frequency independently (3) a 10MHz continuous time PID controller using time based signal processing which alleviates the speed limitations associated with conventional analog and digital. All the three techniques employ digitally assisted control techniques and require no external compensation thus making the controllers fully integrated and highly cost effective. / Graduation date: 2013 / Access restricted to the OSU Community at author's request from June 25, 2012 - June 25, 2014

This master thesis presents the development of a 100 W LED driver, suitable for outdoor and street lighting. In order to match the driver and LED features, special functionalities are added to the electronic system. To obtain a long lifetime, electrolytic capacitor are exchanged by film capacitor, with longer useful lifetime. However, this practice outcome in higher bus voltage ripple, which have to be compensated in the LED current control stage, named as power control stage. To achieve special functionalities, the proposed driver is designed to operate with universal input voltage and dimming capability, being the entire driver control implement in a digital way, increasing significantly the LED driver flexibility. After the literature review, which aimed to evaluate the characteristics of the LED driver topology structure, the two independent stage topology is selected. The buckboost converter operating in discontinuous conduction mode is employed on the power factor correction stage. The power control stage is composed by the DC/DC LLC resonant converter. Once the LED driver topology is defined, each converter is designed, following by the small signal modeling and the control system design. Experimental results of the driver operating with a reduced bus voltage capacitance (25 μF), are presented for a universal input voltage (85 – 265 VRMS) and different dimming levels (100% − 30%). A high power factor (> 0,94) and a medium to high efficiency (> 82%) is noticed in whole operation points, as well as, a reduced flicker (< 10%), being in accordance with the recent released IEEE Std 1789-2015 and IEC61000-3-2 Class C. / Este trabalho apresenta o desenvolvimento de um driver para o acionamento de um módulo de LEDs de 100 W, destinado a iluminação de exteriores ou iluminação pública. De forma a compatibilizar as características do LED com o driver, diferentes funcionalidades e condições de operação são adicionadas ao sistema eletrônico desenvolvido. Para alcançar longa vida útil, o driver desenvolvido substituiu os capacitores eletrolíticos por capacitores de filme. No entanto, essa prática resulta em maiores ondulações da tensão de barramento, as quais são compensadas pelo estágio de controle da corrente dos LEDs. De modo a aumentar as funcionalidades do driver, o mesmo opera com tensão de entrada universal e controle da intensidade luminosa, sendo o sistema de controle do driver implementado de forma digital, aumentando consideravelmente sua flexibilidade. Após revisão da literatura, a qual objetivou avaliar as características das estruturas e topologias empregadas em drivers para LEDs, seleciona-se a estrutura de dois estágios independentes. O conversor buck-boost operando no modo de condução descontínuo de corrente é empregado no estágio de correção do fator de potência. Para o estágio de controle da corrente dos LEDs, utiliza-se o conversor CC/CC meia ponte ressonante LLC. Definida a estrutura topológica, bem como os conversores utilizados, o projeto dos elementos é desenvolvido, seguido da modelagem dinâmica e do projeto do sistema de controle de cada estágio. Resultados experimentais do driver com reduzida capacitância de barramento (25 μF) mostram a sua operação com tensão de entrada universal (85 – 265 VRMS) e controle de intensidade luminosa (100% − 30%). Verificou-se um alto fator de potência (> 0,94) em toda a faixa de operação, rendimento média-alto (> 82%), bem como reduzida modulação de intensidade luminosa (< 10%), estando em conformidade com a IEEE Std 1789-2015 e a IEC61000-3-2 Classe C.

Resumo: Este trabalho apresenta uma nova proposta para sistema de refrigeração com controle dinâmico de temperatura, operando com estrutura de compressor aberto, acionado por motor de indução trifásico com velocidade variável, e estágio de entrada retificador com correção ativa do fator de potência. O estágio de entrada é composto por um retificador Boost monofásico com elevado fator de potência, com duas células entrelaçadas, operando no modo de condução crítica, empregando técnica de comutação não dissipativa e controlado por dispositivo FPGA, associado a um estágio de saída inversor de dois níveis convencional trifásico à IGBT, o qual é controlado por um Processador Digital de Sinais (DSP - Digital Signal Processor). A técnica de comutação não dissipativa para o estágio de entrada é baseada em células ZCS (Zero-current-switching). As principais características do retificador incluem a redução da ondulação da corrente de entrada, redução da ondulação da tensão de saída retificada, utilização de componentes com reduzidos esforços, reduzido volume do filtro de entrada para Interferências Eletromagnéticas (EMI - Electromagnetic Interference), elevado Fator de Potência (FP) e reduzida Distorção Harmônica Total (DHT) da corrente de entrada, atendendo os limites da norma IEC61000-3-2. O controle digital para o estágio de saída inversor foi desenvolvido usando duas diferentes técnicas, incluindo a técnica convencional controle escalar Volts/Hertz (V/Hz) e o controle Vetorial com Orientação pelo Fluxo do estator, com o propósito de verificar a aplicabilidade e a performance dos controles digitais propostos, para o controle contínuo da temperatura, aplicados a um protótipo de sistema de refrigeração. / Abstract: This work presents a new proposal for refrigeration systems with dynamic control of temperature, working with structure of open compressor, driving a three-phase induction motor with variable speed, and input rectifier with active power factor correction. The proposed system is composed of a single-phase high-power-factor boost rectifier, with two cells in interleaved connection, operating in critical conduction mode, and employing a softswitching technique, controlled by a Field Programmable Gate Array (FPGA), associated with a conventional three-phase IGBT bridge inverter (VSI - Voltage Source Inverter), controlled by a Digital Signal Processor (DSP). The soft-switching technique for the input stage is based on zero-current-switching (ZCS) cells. The rectifier’s features include reduction in input current ripple, reduction in output voltage ripple, use of low stress devices, low volume for the EMI input filter, high input power factor (PF), and low total harmonic distortion (THD) in the input current, in compliance with the IEC61000-3-2 standards. The digital controller for the output stage inverter has been developed using two different techniques, the conventional Voltage-Frequency control (scalar V/Hz control), and a simplified stator oriented vector control, in order to verify the feasibility and performance of the proposed digital controls, for continuous temperature control, applied at a refrigerator prototype. / Orientador: Carlos Alberto Canesin / Coorientador: Flávio Alessandro Serrão Gonçalves / Banca: Fabio Toshiaki Wakabayashi / Banca: João Onofre Pereira Pinto / Mestre

Neste trabalho é apresentado um estudo de controladores aplicados a retificadores boost pré reguladores de alto fator de potência. A estratégia convencional, mais utilizada, é o controle por valores médios instantâneos que apresenta uma malha de corrente rápida e uma malha de tensão lenta. A frequência de corte desta última malha é baixa devido a ondulação de tensão de saída no dobro da frequência da rede que deve existir para apresentar uma corrente de entrada com baixa distorção harmônica. Esses controles apresentam um sobressinal elevado e transição lenta durante transitórios de carga, levando a elevação da tensão dos capacitores de saída. A técnica apresentada é um controlador digital com feedforward de potência de saída associado a uma malha de realimentação direta, também conhecido como autocontrole. Essa estratégia possibilita melhores resultados nos transitórios de carga possibilitando redução do capacitor de saída com reduzido sobressinal no transitório de carga. / In this work a study applied in controlled boost rectifiers with high power factor is presented. A most widely used conventional control strategy is the instant average current control, this kind of control have a fast current loop and a slow voltage loop.The cutoff frequency of the voltage loop is low because the output voltage ripple must be twice the frequency of the input network, that need to exist to provide an input current with low harmonic distortion. These controllers feature a high overshoot and a slow transition during the transient load what leads a high voltage in the output capacitors. The developed technique is a digital controller that operate with a feedforward output power associated with one cycle control. This strategy provides better results in the load transient, reducing the overshoot and alloying a reduction of the output capacitor.

Neste trabalho é apresentado um estudo de controladores aplicados a retificadores boost pré reguladores de alto fator de potência. A estratégia convencional, mais utilizada, é o controle por valores médios instantâneos que apresenta uma malha de corrente rápida e uma malha de tensão lenta. A frequência de corte desta última malha é baixa devido a ondulação de tensão de saída no dobro da frequência da rede que deve existir para apresentar uma corrente de entrada com baixa distorção harmônica. Esses controles apresentam um sobressinal elevado e transição lenta durante transitórios de carga, levando a elevação da tensão dos capacitores de saída. A técnica apresentada é um controlador digital com feedforward de potência de saída associado a uma malha de realimentação direta, também conhecido como autocontrole. Essa estratégia possibilita melhores resultados nos transitórios de carga possibilitando redução do capacitor de saída com reduzido sobressinal no transitório de carga. / In this work a study applied in controlled boost rectifiers with high power factor is presented. A most widely used conventional control strategy is the instant average current control, this kind of control have a fast current loop and a slow voltage loop.The cutoff frequency of the voltage loop is low because the output voltage ripple must be twice the frequency of the input network, that need to exist to provide an input current with low harmonic distortion. These controllers feature a high overshoot and a slow transition during the transient load what leads a high voltage in the output capacitors. The developed technique is a digital controller that operate with a feedforward output power associated with one cycle control. This strategy provides better results in the load transient, reducing the overshoot and alloying a reduction of the output capacitor.