<p>A channel board was designed for a DRFM circuit. The DRFM is implemented in a Virtex-4 FPGA from Xilinx. In the future a similar channel board is intended to be used for target echo generation in ELSI which is an electronic warfare simulator at Saab Bofors Dynamics in Linköping.</p><p>Besides the DRFM circuit the channel board consists of analog-to-digital converters, digital-to-analog converters, Ethernet plug-in board with a microcontroller, voltage regulators, FPGA configuration memory, voltage amplifiers, current amplifiers, oscillator, buffers/drivers and bus transceivers. The sample rate is 200 MHz and LVDS signalling standard is used between the DRFM circuit and the converters.</p><p>The channel board has a JTAG interface which enables in-system programming of the FPGA. This implies that the DRFM can easily be redesigned. An external computer can manage the channel board via Ethernet. Software was developed for the microcontroller on the channel board and for the external computer. The function of the channel board is heavily dependent on the DRFM circuit.</p><p>The channel board design resulted in the assembly of a prototype circuit board. Measurements were performed in a lab and the channel board was approved to be integrated in ELSI for further tests.</p>

A channel board was designed for a DRFM circuit. The DRFM is implemented in a Virtex-4 FPGA from Xilinx. In the future a similar channel board is intended to be used for target echo generation in ELSI which is an electronic warfare simulator at Saab Bofors Dynamics in Linköping. Besides the DRFM circuit the channel board consists of analog-to-digital converters, digital-to-analog converters, Ethernet plug-in board with a microcontroller, voltage regulators, FPGA configuration memory, voltage amplifiers, current amplifiers, oscillator, buffers/drivers and bus transceivers. The sample rate is 200 MHz and LVDS signalling standard is used between the DRFM circuit and the converters. The channel board has a JTAG interface which enables in-system programming of the FPGA. This implies that the DRFM can easily be redesigned. An external computer can manage the channel board via Ethernet. Software was developed for the microcontroller on the channel board and for the external computer. The function of the channel board is heavily dependent on the DRFM circuit. The channel board design resulted in the assembly of a prototype circuit board. Measurements were performed in a lab and the channel board was approved to be integrated in ELSI for further tests.

The purpose of this reasearch was to develop a respiratory monitoring system using a reflective object sensor based belt to measure the thoracic expansion of a neonatal for future application at the medical center of the Universidad Evangelica Boliviana (UEB). This medical center, being founded by the UEB University, is dedicated to help and serve the poor and currently has no respiratory monitoring system. The methodology used was first to build and test the respiratory sensor belt and test the relationship between the blet expansion and the voltage generated. The, to incorporate the respiratory sensor belt in a system that would allow individual testing as well as group testing in a wireless network. The system was simulated using an expandable plastic container that was expanded and extracted periodically, registering the results in a MATLAB software. The system gave successful results and generated the frequency results of each cycle, average frequency and deviation frequency. The system demonstrated to be reliable and to have repeatable results.

Wireless capsule endoscopy (WCE) is a state-of-the-art technology to receive images of human intestine for medical diagnostics. In WCE, the patient ingests a specially designed electronic capsule which has imaging and wireless transmission capabilities inside it. While the capsule travels through the gastrointestinal (GI) tract, it captures images and sends them wirelessly to an outside data logger unit. The data logger stores the image data and then they are transferred to a personal computer (PC) where the images are reconstructed and displayed for diagnosis. The key design challenge in WCE is to reduce the area and power consumption of the capsule while maintaining acceptable image reconstruction. In this research, the unique properties of WCE images are identified by analyzing hundreds of endoscopic images and video frames, and then these properties are used to develop novel and low complexity compression algorithms tailored for capsule endoscopy. The proposed image compressor consists of a new YEF color space converter, lossless prediction coder, customizable chrominance sub-sampler and an efficient Golomb-Rice encoder. The scheme has both lossy and lossless modes and is further customized to work with two lighting modes – conventional white light imaging (WLI) and emerging narrow band imaging (NBI). The average compression ratio achieved using the proposed lossy compression algorithm is 80.4% for WBI and 79.2% for NBI with high reconstruction quality index for both bands. Two surveys have been conducted which show that the reconstructed images have high acceptability among medical imaging doctors and gastroenterologists. The imaging algorithms have been realized in hardware description language (HDL) and their functionalities have been verified in field programmable gate array (FPGA) board. Later it was implemented in a 0.18 μm complementary metal oxide semiconductor (CMOS) technology and the chip was fabricated. Due to the low complexity of the core compressor, it consumes only 43 µW of power and 0.032 mm2 of area. The compressor is designed to work with commercial low-power image sensor that outputs image pixels in raster scan fashion, eliminating the need of significant input buffer memory. To demonstrate the advantage, a prototype of the complete WCE system including an FPGA based electronic capsule, a microcontroller based data logger unit and a Windows based image reconstruction software have been developed. The capsule contains the proposed low complexity image compressor and can generate both lossy and lossless compressed bit-stream. The capsule prototype also supports both white light imaging (WLI) and narrow band imaging (NBI) imaging modes and communicates with the data logger in full duplex fashion, which enables configuring the image size and imaging mode in real time during the examination. The developed data logger is portable and has a high data rate wireless connectivity including Bluetooth, graphical display for real time image viewing with state-of-the-art touch screen technology. The data are logged in micro SD cards and can be transferred to PC or Smartphone using card reader, USB interface, or Bluetooth wireless link. The workstation software can decompress and show the reconstructed images. The images can be navigated, marked, zoomed and can be played as video. Finally, ex-vivo testing of the WCE system has been done in pig's intestine to validate its performance.

De tout temps, l'Homme s'est vu contraint de protéger les fruits de sa créativité et les domaines concernant sa sécurité. Ses informations sont souvent sensibles, dans les relations politiques et commerciales notamment. Aussi, la nécessité de les protéger en les rendant opaques au regard d'adversaires ou de concurrents est vite survenue. Depuis l'Antiquité, les procédés de masquages et enfin de cryptages furent nombreux. Les techniques de protection, depuis l'époque industrielle n'ont fait que croître pour voir apparaître, durant la seconde guerre mondiale, l'archétype des machines électromécaniques (telle l'Enigma), aux performances réputées inviolables. De nos jours, les nouveaux circuits de protection embarquent des procédés aux algorithmes hyper performants. Malgré toutes ces protections, les produits restent la cible privilégiée des " pirates " qui cherchent à casser par tous les moyens les structures de sécurisation, en vue d'utilisations frauduleuses. Ces " hackers " disposent d'une multitude de techniques d'attaques, l'une d'elles utilise un procédé par injections de fautes à l'aide d'un faisceau laser. Dès le début de ce manuscrit (Chapitre I), l'état de l'art de l'injection de fautes sera développé, en se focalisant sur celles faite à l'aide d'un faisceau laser. Ceci aidera à bien appréhender ces procédés intrusifs et ainsi protéger au mieux les microcontrôleurs sécurisés contre ces types d'attaques. Il est nécessaire de bien comprendre les phénomènes physiques mis en jeu lors de l'interaction entre une onde de lumière cohérente, tels les lasers et le matériau physico-chimique qu'est le silicium. De la compréhension de ces phénomènes, une modélisation électrique des portes CMOS sous illumination laser a été mise en oeuvre pour prévoir leurs comportements (chapitre II). De bonnes corrélations ont pu être obtenues entre mesures et simulations électrique. Ces résultats peuvent permettre de tester la sensibilité au laser de portes CMOS au travers de cartographies de simulation. De cette meilleure compréhension des phénomènes et de ce simulateur mis en place, de nombreuses contre-mesures ont été imaginées. Les nouvelles techniques développées, présentées dans ce manuscrit, donnent déjà des pistes pour accroître la robustesse des circuits CMOS contre des attaques laser. D'ores et déjà, ce travail a permis la mise en oeuvre de détecteurs lasers embarqués sur les puces récentes, renforçant ainsi sensiblement la sécurité des produits contre une attaque de type laser.

In this thesis, a high precision motion and position control system has been developed and applied to a high voltage sphere gap control and measurement system. The system is able to support up to 3-axes position and motion control. The control system includes a microcontroller card, three DC servo motor driver cards and a data storage unit. To provide communication between computer and motion control system, the Universal Serial Bus (USB) port is used. The microcontroller card is equipped with an USB interface and a PIC (Peripheral Interface Controllers) microcontroller. This microcontroller controls the dedicated motion control processors (LM629), on servo motor driver cards and read/write operations of data storage unit, which consists of a Multi Media Card.

Η παρούσα διπλωματική εργασία πραγματεύεται τη μελέτη και κατασκευή μιας διάταξης που παρακολουθεί συνεχώς τη θέση του ήλιου στον ουρανό και στρέφει αντίστοιχα ένα φωτοβολταϊκό πάνελ κατά τέτοιο τρόπο ώστε να μεγιστοποιείται η ένταση της ηλιακής ακτινοβολίας που προσπίπτει σε αυτό και επομένως και η ενεργειακή του απόδοση (solar tracker). Προκειμένου να πραγματοποιηθεί η εφαρμογή, το ίδιο το φωτοβολταϊκό πάνελ χρησιμοποιήθηκε ως ανιχνευτής της θέσης του ήλιου στον ουρανό απλουστεύοντας έτσι την κατασκευή και μειώνοντας το κόστος της καθώς δεν χρειάστηκαν επιπλέον αισθητήρες. Συγκεκριμένα, ανά τακτά χρονικά διαστήματα δειγματοληπτούνταν η τιμή της τάσης στα άκρα του φωτοβολταϊκού πάνελ από τον μικροελεγκτή msp430F169 της εταιρείας texas instruments, αποθηκεύονταν στους καταχωρητές του και αφού μετατρεπόταν το σήμα από αναλογικό σε ψηφιακό συγκρινόταν με τις προηγούμενες τιμές. Ανάλογα με το αποτέλεσμα της σύγκρισης, ο μικροελεγκτής έδινε εντολή στον κινητήρα που κατεύθυνε το φωτοβολταϊκό πάνελ να κινηθεί στην αντίστοιχη κατεύθυνση. Η διαδικασία επαναλαμβανόταν μέχρις ότου βρεθεί το σημείο εκείνο όπου η τάση στα άκρα του γίνεται μέγιστη. Το σύστημα που κατασκευάσαμε περιλαμβάνει κίνηση γύρω από έναν άξονα. Συγκεκριμένα παρακολουθεί την αζιμουθιακή κίνηση του ήλιου ξεκινώντας από την ανατολή (Earth) και καταλήγοντας στη δύση (West). / The present thesis deals with the study and construction of a solar tracker that constantly detects the sun position to the sky and directs correspondingly a photovoltaic panel in order to maximize the intensity of solar radiation prostrating to it and as a result, its energy performance as well. In order the application to be realized, the same photovoltaic panel was used as detector of the sun position to the sky, simplifying the construction and reducing its cost, as no further sensors were required. Particularly, the point-to-point voltage value of the photovoltaic panel was regularly sampled by the microcontroller msp430F169 of the Texas Instruments Company, it was saved to the register, and after the signal was being converted from analog to digital, it was being compared to the previous value. Depending on the result of the comparison, the microcontroller ordered the motor directing the photovoltaic panel to move across the corresponding direction. The process was being repeated until a point was found were the point-to-point voltage value was the maximum. The system created includes motion around one axis. Particularly, it observes the azimuthal solar motion starting from East and ending to West

Este trabalho apresenta a proposta de um instrumento para utilização nos ensaios previstos nas Normas Brasileiras para certificação das instalações elétricas de baixa tensão. Descreve-se o projeto e a implementação do instrumento desenvolvido, bem como a metodologia para a execução dos testes de conformidade, de acordo com as Normas Brasileiras aplicáveis, utilizando os recursos disponíveis na instrumentação proposta. Um conjunto de testes para exemplificação de uso e validação dos testes é também apresentado. / This work presents an instrumentation system to perform tests and certification of low voltage electrical networks on residential and industrial buildings in accordance to Brazilian Norms. It intends to propose a methodology for tests executions using available resources on the developed instrumentation system. To show how the proposed system works several tests were done regarding to attend Brazilian technical standards.

Este trabalho propõe a geração de uma arquitetura dedicada a aplicações específicas, baseadas no microcontrolador MCS8051. Por ser utilizado na solução de problemas em indústrias locais, este processador foi escolhido para servir como base em um sistema dedicado. O 8051 dedicado gerado deverá permitir a integração completa do sistema, proporcionando um aumento do valor agregado e, conseqüentemente, a diminuição do custo. Busca-se com a otimização da arquitetura obter um conjunto de instruções reduzido, construído com as instruções mais utilizadas em cada aplicação. O objetivo principal da otimização do conjunto de instruções está relacionado ao fato de que os circuitos decodificadores e geradores de microcódigo da parte de controle ocupam uma área significativa do processador. Uma otimização no sentido de reduzir-se o conjunto de instruções, portanto, resulta numa economia de área, o que vem de encontro com a idéia da integração completa do sistema com o processador. Um processador dedicado a aplicações específicas (ASIP) irá possuir um custo maior do que a sua versão original, devido as otimizações realizadas. Para compensar este custo, uma alternativa a seguir é a integração completa do sistema. Um Sistema Integrado para Aplicações Específicas (SIAE) torna-se desejável, pois aumentando o valor agregado do circuito possibilita-se a redução do custo pela eliminação de conexões da placa, do encapsulamento de outros circuitos, entre outros motivos. Todavia, para que um SIAE possa ser construído com um custo aceitável, é necessário que seja construído em uma área que não exceda muito a área original do processador. Tenta-se fazer isto neste trabalho, através da implementação de aplicações com poucas instruções diferentes. Por ser uma arquitetura comercial, o 8051 possui um grande parque de software desenvolvido e resolvendo problemas. Isto pode ser considerado uma vantagem pois, software básicos como por exemplo, compiladores, já estão desenvolvidos. Outra vantagem é o grande número de engenheiros treinados na sua utilização. Desse modo, torna-se necessária a criação de uma compatibilidade de software, para preservar o que já está desenvolvido. Uma vez que a programação em nível de linguagem montadora tende a constituir-se em uma tarefa cansativa e sujeita a erros, é desejável que se tenha uma compatibilidade em alto nível, ou seja, através de um compilador. Para criar a compatibilidade de SW necessária é realizada a otimização de um compilador C desenvolvido para o 8051. A escolha pela linguagem C deve-se ao fato de sua grande utilização. O compilador C otimizado procura utilizar um conjunto de instruções reduzido para obter a economia de área. Quando uma instrução necessita ser utilizada e não está presente no conjunto de instruções desejado, o compilador tenta substituí-la por outra(s). Um conjunto de instruções é utilizado para cada aplicação, sendo constituído pelas instruções mais utilizadas por esta. Para determinar as instruções mais utilizadas de cada aplicação é realizada uma análise estática sobre um código em linguagem montadora previamente compilado. As instruções implementadas serão sempre parte do conjunto de instruções original do 8051, de modo que novas instruções não serão criadas.Um programa em linguagem montadora gerado com um conjunto de instruções reduzido (RISC) normalmente terá um número maior de instruções do que o seu 10 equivalente com o conjunto de instruções completo (CISC). Isto ocorre porque possivelmente algumas substituições de uma instrução por outras, terão que ser realizadas. Como as instruções que serão utilizadas nas substituições pertencem ao conjunto de instruções original, o programa gerado com o compilador otimizado poderá executar em um tempo maior do que se fosse compilado com o código CISC. Para compensar esse atraso foi implementado um pipeline de instruções para o 8051. Este trabalho apresenta resultados da Síntese Lógica em Standard Cell e FPGA da arquitetura otimizada. Além disso, resultados de programas em linguagem montadora gerados com o compilador otimizado, são também apresentados. / This work discusses a processor for specific applications architecture, based on the MCS8051 microcontroller. This processor is used as a solution for many local industry applications, being the base of dedicated systems. The dedicated 8051 generated should allow complete integration of the system, and with the added value to the chip, reduced costs. The architecture optimization will produce as result a reduced instruction set, made by the often used instructions for each application. The main instruction set optimization goal refers to the instrucions decoders and microcode generators in the control part, because a large area in the processor is needed to implement them. Thus, a reduced instruction set will allow area savings, making possible the complete system integration in a chip. An ASIP architecture will have a higher cost than the original one. An alternative to solve this problem is add value to the chip, creating an Application Specific Integrated System (ASIS). An ASIS can be made with a acceptable cost, if it’s possible to integrate other circuits to the chip without area increase. This can be done in the area saved by using fewer implemented instructions. Because the 8051 is a commercial architecture, there is a large amount of software developed for it. This can be considered an advantage because basic softwares like compilers are available, being not necessary to create them. Another advantage refers to the large number of engineers trained to use the 8051. To preserve the already developed applications it’s necessary to mantain software compatibility. Assembler level programming is very boring an error prone task, being desirable to have software compatibility at higher levels through the use of high level languages. To create the necessary SW compatibility, a C compiler developed for 8051 was optimized. The chose for C language refers to its large utilization. The optimized C compiler tries to use a reduced instruction set, formed with the most important instructions for each application, in order ro save area. When an instruction needs to be used in an application, and it’s not present in the instruction set, the compiler tries to replace it with other instructions. The compiler will not use instructions not present in the original 8051 instruction set. So, new instrucions will be not created. To create an instruction set formed with the most important instructions for each application, a static analysis is made on a precompiled assembler source. An assembler source generated with a reduced instruction set (RISC) will probably have more instructions than the same assembler generated with a full instruction set (CISC). This can be explained because of the replacements instruction. If one instruction is replaced by other two, and these are from the original instruction set, probably the time needed to execute them would be higher. In order to deal with this problem, an instruction pipeline was implemented to the 8051. This work presents Standard Cells and FPGA results of Logic Synthesis of the optimized architecture. Also, assembly programs generated by the optimized compiler are presented.

The Masters thesis describes the control of heating system in family houses where exists requests for supervising and measuring of sources, energy storages and delivery parts of network. Description includes detail for source education support, overviews to development tools and programming language for microcontrollers. Heating system is built for two sources of energy and every source is steered alone. Source codes are designed into PIC? single-chip processors PIC? 18F4520 and PIC? 16F628A developed by Microchip company. These are deployed in unified boards called embedded board chosen for their accessibility from point of view low and high voltage interfaces. Part application of powerful elements control describes principle of operation and their usage in networks. For on-line control of central equipment is preferred usage of powerful components with servo-mechanism and for simpler usage is good to use passive components. Temperature sensor read current value in cross points of network where are media mixed or saved. Processors provides except own control jobs information interface for users too. Used SW is well arranged, faithful and includes routine for source code optimizing. The example of controlled system is actuators in family house heating with high and low temperature circuits which are controlled by industrial systems as current gas coopers.