As the world moves towards eliminating lead from consumer products, the microelectronics industry has put effort into developing lead-free solder paste. The major drawback of lead-free solder is the problems caused by its high reflow temperature. Variable frequency microwave (VFM) processing has been shown to allow some materials to be processed at lower temperatures. Issues addressed in this study include using VFM to reduce the solder reflow temperature, comparing the heating rate of different size solder particles, and comparing the reliability of VFM reflowed solder versus conventionally reflowed solder. Results comparing the effect of particle size on the heating rate of solder showed that the differences were negligible. This is due in part to the particle sizes overlapping. Many lead-free solder pastes reflow around 250℃. Results indicate that when using the VFM, lead-free solder paste will reflow at 220℃. The reliability of solder that was reflowed using the VFM at the reduced temperature was found to be comparable to solder reflowed in a conventional manner. Based on these findings, VFM processing can eliminate the major obstacles to making lead-free solder paste a more attractive option for use in the microelectronics industry.

To enable fast and reliable processors, advances must be made in the interconnections on the printed circuit board and in the interconnections from the chip to the printed circuit board. Processing techniques have been demonstrated to fabricate a copper-clad encapsulated air dielectric layer to enable low loss off-chip electrical signal lines using sacrificial polymers and the three dimensional patterning capabilities of imprint lithography. The inclusion of an air gap can eliminate the dielectric loss allowing the signal to propagate over longer lengths. Additionally, the low dielectric constant of air lowers the loss contributions from the conductor and increases the signal propagation velocity reducing delay. The metal shielding could minimize the crosstalk noise and radiation losses that are significant at high frequencies. The three dimensional patterning capabilities of imprint lithography fabricated curved structures and rounded terminations which can reduce reflections at discontinuities. Furthermore, imprint lithography also created planarized surfaces which simplified the buildup process. Since imprint lithography, only uses temperature and pressure to make a pattern it is an inexpensive and simple process advancement. The metal-clad encapsulated air dielectric structures were fabricated in a comparable number of registration steps to traditional transmission lines. Implementation of all copper chip to substrate interconnects would provide high conductivity electrical connections, resistance to electromigration while avoiding formation of brittle intermetallics. High aspect ratio polymer molds for copper electroplating interconnects could enable improved integrated circuit electrical performance. The properties of a new aqueous base develop, negative-tone photosensitive polynorbornene polymer have been characterized to develop mechanically compliant all copper connections between the chip and printed circuit board. High aspect ratio features of 7:1 (height:width) were produced in 70 ìm thick films in a single coat with straight side-wall profiles and high fidelity. The polymer films studied had a contrast of 11.6 and a low absorption coefficient. To evaluate the polymer's suitability to microelectronics applications, epoxy cross-linking reactions were studied as a function of processing condition through Fourier transform infrared spectroscopy, nano-indentation, and dielectric measurements. The fully cross-linked films had an elastic modulus of 2.9 GPa and hardness of 0.18 GPa which can improve the mechanical compliance of the copper interconnections. A photo-imprint lithography process was developed to improve the photo-patterning of the polynorbornene polymer for high aspect ratio hollow structures. A shallow photo-imprint stamp was developed to physically displace material in the polymer core. Since the imprint stamp displaces material in the area of the feature, the effective film thickness is reduced compared to the bulk film. The reduction in film height reduced the effects of scattering in the core and also facilitated transport of developer within the core. The photo-imprint lithography process resulted in high aspect ratio hollow core pillars that exceeded optical resolution capabilities for comparable feature sizes.

This thesis employs computational and experimental methods to explore hotspot cooling and high heat flux removal from a 3-D stacked chip using thermoelectric and microfluidic devices. Stacked chips are expected to improve microelectronics performance, but present severe thermal management challenges. The thesis provides an assessment of both thermoelectric and microfluidic technologies and provides guidance for their implementation in the 3-D stacked chips. A detailed 3-D thermal model of a stacked electronic package with two dies and four ultrathin integrated TECs is developed to investigate the efficacy of TECs in hotspot cooling for 3-D technology. The numerical analysis suggests that TECs can be used for on demand cooling of hotspots in 3-D stacked chip architecture. A strong vertical coupling is observed between the top and bottom TECs and it is found that the bottom TECs can detrimentally heat the top hotspots. As a result, TECs need to be carefully placed inside the package to avoid such undesired heating. Thermal contact resistances between dies, inside the TEC module, and between the TEC and heat spreader are shown to significantly affect TEC performance. TECs are most effective for cooling localized hotspots, but microchannels are advantageous for cooling large background heat fluxes. In the present work, the results of heat transfer and pressure drop experiments in the microchannels with water as the working fluid are presented and compared to the previous microchannel experiments and CFD simulations. Heat removal rates of greater than 100 W/cm2 are demonstrated with these microchannels, with a pressure drop of 75 kPa or less. A novel empirical correlation modeling method is proposed, which uses finite element modeling to model conduction in the channel walls and substrate, coupled with an empirical correlation to determine the convection coefficient. This empirical correlation modeling method is compared to resistor network and CFD modeling. The proposed modeling method produced more accurate results than resistor network modeling, while solving 60% faster than a conjugate heat transfer model using CFD. The results of this work demonstrate that microchannels have the ability to remove high heat fluxes from microelectronic packages using water as a working fluid. Additionally, TECs can locally cool hotspots, but must be carefully placed to avoid undesired heating. Future work should focus on overcoming practical challenges including fabrication, cost, and reliability which are preventing these technologies from being fully leveraged.

Microelectronics has enjoyed great success in the past century. As the technology node progresses, the complementary metal-oxide-semiconductor scaling has already reached a wall, and serious challenges in high-bandwidth interconnects and fast-speed signal processing arise. The incorporation of photonics to microelectronics provides potential solutions. The theme of this thesis is focused on the novel applications of travelling-wave microresonators such as microdisks and microrings for the on-chip optical interconnects and signal processing. Challenges arising from these applications including theoretical and experimental ones are addressed. On the theoretical aspect, a modified version of coupled mode theory is offered for the TM-polarization in high index contrast material systems. Through numerical comparisons, it is shown that our modified coupled mode theory is more accurate than all the existing ones. The coupling-induced phase responses are also studied, which is of critical importance to coupled-resonator structures. Different coupling structures are studied by a customized numerical code, revealing that the phase response of symmetric couplers with the symmetry about the wave propagating direction can be simply estimated while the one of asymmetric couplers is more complicated. Mode splitting and scattering loss, which are two important features commonly observed in the spectrum of high-Q microresonators, are also investigated. Our review of the existing analytical approaches shows that they have only achieved partial success. Especially, different models have been proposed for several distinct regimes and cannot be reconciled. In this thesis, a unified approach is developed for the general case to achieve a complete understanding of these two effects. On the experimental aspect, we first develop a new fabrication recipe with a focus on the accurate dimensional control and low-loss performance. HSQ is employed as the electron-beam resist, and the lithography and plasma etching steps are both optimized to achieve vertical and smooth sidewalls. A third-order temperature-insensitive coupled-resonator filter is designed and demonstrated in the silicon-on-insulator (SOI) platform, which serves as a critical building block element in terabit/s on-chip networks. Two design challenges, i.e., a broadband flat-band response and a temperature-insensitive design, are coherently addressed by employing the redundant bandwidth of the filter channel caused by the dispersion as thermal guard band. As a result, the filter can accommodate 21 WDM channels with a data rate up to 100 gigabit/s per wavelength channel, while providing a sufficient thermal guard band to tolerate more than ±15°C temperature fluctuations in the on-chip environment. In this thesis, high-Q microdisk resonators are also proposed to be used as low-loss delay lines for narrowband filters. Pulley coupling scheme is used to selectively couple to one of the radial modes of the microdisk and also to achieve a strong coupling. A first-order tunable narrowband filter based on the microdisk-based delay line is experimentally demonstrated in an SOI platform, which shows a tunable bandwidth from 4.1 GHz to 0.47 GHz with an overall size of 0.05 mm². Finally, to address the challenges for the resonator-based delay lines encountered in the SOI platform, we propose to vertically integrate silicon nitride to the SOI platform, which can potentially have significantly lower propagation loss and higher power handling capability. High-Q silicon nitride microresonators are demonstrated; especially, microresonators with a 16 million intrinsic Q and a moderate size of 240 µm radius are realized, which is one order of magnitude improvement compared to what can be achieved in the SOI platform using the same fabrication technology. We have also successfully grown silicon nitride on top of SOI and a good coupling has been achieved between the silicon nitride and the silicon layers.

In this thesis I will present an approach and apparatus for detecting and precisely characterizing any dose-dependent changes in the functional behaviour of a data converter in a neutron radiation environment. Depending on the data converter such changes could include shifts in the gain, offset, noise, or linearity of the device output. The approach leverages the neutron flux produced by an Americium-Beryllium radioisotope neutron source, and is meant to emulate the neutron environment near a Cm-244 source, as found in the sensor head of the APXS instrument. This method uses a relatively low dose rate (configurable by proximity to the source) which allows for long-term monitoring and characterization of parametric changes in device behaviour. It has the additional benefit of not requiring a reactor or accelerator, and can therefore run unattended when necessary. The prototype system, which is designed to allow the data converter to be operating during irradiation, uses LVDS signalling to drive and extract data from a minimal test board which is placed in proximity to the neutron source, and a Virtex-4 FPGA board to provide clock and power, and to perform signal processing. By separating the majority of the test equipment from the neutron environment, any radiation effects will be isolated to the DUT and a minimal set of supporting devices. The prototype design is presented here, along with initial characterization results and first test results on a commercial, off-the-shelf data converter. / Canadian Space Agency, Ontario Centres of Excellence, MacDonald, Dettwiler, and Associates

The purpose of this research was to investigate the factors that enhance conductive anodic filament (CAF) formation in printed wiring boards. The variables studied were (1) flux formulation, (2) conductor spacing, (3) operating voltage, and (4) temperature. A Weibull distribution of failure times due to CAF was observed. A novel test circuit was designed and implemented that allowed the mean time to failure to be determined for boards processed with three different fluxes, at 0.5 mm and 0.75 mm conductor spacings and at 150V and 200V. The boards were aged at 85%RH and a temperature of 75°C, 85°C or 95°C. It was found that the flux formulation affected the rate of CAF formation. A modified linear aliphatic polyether flux with a chloride activator had a significantly different activation energy than control printed wiring boards or those boards processed with a poly(ethylene/propylene) glycol flux or a poly(ethylene/propylene) glycol flux with a bromide activator. The addition of bromine to a poly(ethylene/propylene) glycol flux decreased the rate of CAF formation as compared to poly(ethylene/propylene) glycol without a halide activator. The inter-relation between voltage and conductor spacing was quantified as a L4/V2 relationship for the plated through hole test pattern used in this study. 325V/mm was found to be a critical voltage gradient for the formation of CAF. The maximum temperature of the reflow profile also greatly enhances CAF formation and decreases the mean time to failure. Microscopic analysis showed distinct differences in CAF morphology between the various processed boards. Control boards had small halo-like CAF formations around a separated fiber / epoxy interface. CAF that formed on boards processed with poly(ethylene/propylene) glycol or poly(ethylene/propylene) glycol with a bromine activator had a stratified appearance that penetrated well into the epoxy. Boards that were processed with the modified linear aliphatic polyether with chlorine activator had a striated morphology that also penetrated into the epoxy. All CAFs were consistently copper and chlorine containing despite the use of a bromine containing flux. Electron diffraction revealed that a CAF observed in this study was synthetic atacamite. Stainless steel (i.e., iron, nickel, and chromium) residues were also observed as a result of drill bit breakage during PTH formation.

No description available.

Neste trabalho é desenvolvido de forma inédita no Brasil um processo simples de fabricação de transistores FD SOI nMOSFET (Fully-Depleted Silicon-On-Insulator) com porta de silício policristalino, para servir como base para futuros desenvolvimentos e, também, com finalidade de educação em microeletrônica. É proposta uma sequência de etapas de fabricação necessárias para a obtenção do dispositivo FD SOI nMOSFET, usando apenas 3 etapas de fotogravação e usando o óxido enterrado, intrínseco à tecnologia SOI, como região de campo, objetivando a obtenção do processo mais simples possível e eficiente. São apresentados os procedimentos detalhados de todas as etapas de fabricação executadas. Para obtenção da tensão de limiar de 1V foram fabricadas amostras com 2 doses diferentes de implantação iônica, 1,0x1013cm-2 e 1,2x1013cm-2. Estas doses resultaram em tensões de limiar (VTH) de 0,72V e 1,08V; respectivamente. Como esperado, a mobilidade independente de campo (0) é maior na amostra com dose menor, sendo de 620cm²/Vs e, para a dose maior, 460cm²/Vs. A inclinação de sublimiar é calculada através da obtenção experimental do fator de acoplamento capacitivo () 0,22; para as duas doses, e resulta em 73mV/déc. O ganho intrínseco de tensão (AV) mostrou-se maior na amostra com maior dose em função da menor condutância de saída, sendo 28dB contra 26dB para a dose menor, no transistor com L=40m e W=12m. Desta forma foi possível implementar uma sequência simples de fabricação de transistores SOI, com resultados elétricos relevantes e com apenas 3 etapas de fotogravação, fato importante para viabilizar seu uso em formação de recursos humanos para microeletrônica. / In this work is developed in an unprecedented way in Brazil a simple process of manufacturing transistors FD SOI nMOSFET (Fully-Depleted Silicon-On-Insulator) with gate polysilicon, to serve as the basis for future developments and also with the purpose of education in microelectronics. A sequence of manufacturing steps necessary for obtaining FD SOI nMOSFET device is proposed, using only three photolithographic steps and using the buried oxide, intrinsic to SOI technology such as field region, aiming to get the simplest possible and efficient process. All the detailed manufacturing steps performed procedures are presented. To obtain the threshold voltage of 1V samples with 2 different doses of ion implantation (1.0x1013cm-2 and 1.2 x1013cm-2) were fabricated. These doses resulted in threshold voltages (VTH) of 0.72 V and 1.08 V, respectively. As expected, mobility independent of field (0) is higher in the sample with the lowest dose, 620cm²/Vs, and for the higher dose, 460cm²/Vs. The subthreshold slope is calculated by obtaining experimental capacitive coupling factor () 0.22, for both doses and results in 73mV/déc. The intrinsic voltage gain (AV) was higher in the sample with a higher dose due to lower output conductance, 28dB against 26dB to the lowest dose, to the transistor with L = W = 40m and 12m. This made it possible to implement a simple sequence of manufacturing SOI transistors with relevant electrical results and with only 3 steps photolithographic important fact to enable their use in training human resources for microelectronics.

An Underwater Digital Signal Processor (UDSP) multichip module (MCM) was designed and fabricated according to specifications outlined by the Naval Surface Warfare Center (NSWC), Dahlgren Division. Specifications indicated that low temperature cofired ceramic (L TCC) technology be used to fabricate the MCM with surface dimensions of 2"x2". The top surface of the module was to be designed to enclose mounted components and bare dice, and the bottom surface was to be equipped with a 144 pin grid array (PGA). The LTCC technology selected for this application incorporated DuPont's 951 Green Tape™ and compatible materials and pastes. A mixed metal system using inner silver system and outer surface gold system was used. Harris Corporation's FINESSE MCMTM, a computer-aided design (CAD) tool, was used to design the surface components and produce the circuit layout. FREESTYLE MCM™, an autorouter, was used to accomplish the routing of the signal layers. The design information provided by FINESSE MCM™ and FREESTYLE MCM™ was utilized to produce the artwork necessary for fabrication. Fabrication of the module was accomplished in part using thick film processes to produce the conducting areas on each layer. The layers were stacked in a press, laminated, and fired. Conducting areas were screen printed on the top surface of the module for wire bonding and on the bottom surface of the module for pin attachment. The main objectives of this thesis work were to convert silicon UDSP MCM to ceramic using LTCC, learn a new tool in CAD design that incorporates an autorouter, apply the tool to design a MCM-C module, and to develop criteria to evaluate the MCM. Future research work includes conducting line continuity testing, materials evaluation to determine reactions at interfaces and via filling, and resistance and electrical crosstalk measurements on the module. / Master of Science

La miniaturisation des technologies Silicium optimise la surface occupée par les supports de télécommunication mobile. La motivation de cette thèse porte sur la conception d'un amplificateur de puissance en technologie CMOS 65 nm qui permet de répondre au standard UMTS W-CDMA. Ce standard exige une grande linéarité et une forte puissance de sortie afin d'assurer une émission à haut débit sur une longue distance. Cette étude porte sur la compatibilité entre la technologie utilisée et les exigences de ce standard."