Efficient power conversion is essential to face the continuously increasing energy consumption of our society. GaN based vertical power field effect transistors provide excellent performance figures for power-conversion switches, due to their capability of handling high voltages and current densities with very low area consumption. This work focuses on a vertical trench gate metal oxide semiconductor field effect transistor (MOSFET) with conceptional advantages in a device fabrication preceded GaN epitaxy and enhancement mode characteristics. The functional layer stack comprises from the bottom an n+/n- drift/p body/n+ source GaN layer sequence. Special attention is paid to the Mg doping of the p-GaN body layer, which is a complex topic by itself. Hydrogen passivation of magnesium plays an essential role, since only the active (hydrogen-free) Mg concentration determines the threshold voltage of the MOSFET and the blocking capability of the body diode. Fabrication specific challenges of the concept are related to the complex integration, formation of ohmic contacts to the functional layers, the specific implementation and processing scheme of the gate trench module and the lateral edge termination. The maximum electric field, which was achieved in the pn- junction of the body diode of the MOSFET is estimated to be around 2.1 MV/cm. From double-sweep transfer measurements with relatively small hysteresis, steep subthreshold slope and a threshold voltage of 3 - 4 V a reasonably good Al2O3/GaN interface quality is indicated. In the conductive state a channel mobility of around 80 - 100 cm2/Vs is estimated. This obtained value is comparable to device with additional overgrowth of the channel. Further enhancement of the OFF-state and ON-state characteristics is expected for optimization of the device termination and the high-k/GaN interface of the vertical trench gate, respectively. From the obtained results and dependencies key figures of an area efficient and competitive device design with thick drift layer is extrapolated. Finally, an outlook is given and advancement possibilities as well as technological limits are discussed.:1 Motivation and boundary conditions 1.1 A comparison of competitive semiconductor materials 1.2 Vertical GaN device concepts 1.3 Target application for power switches 2 The vertical GaN MOSFET concept 2.1 Incomplete ionization of dopants 2.2 The pseudo-vertical approach 2.3 Considerations for the device OFF-state 2.3.1 The pn-junction in reverse operation 2.3.2 The gate trench MIS-structure in OFF-state 2.3.3 Dimensional constraints and field plates 2.4 Static ON-state and switching considerations 2.4.1 The pn-junction in forward operation 2.4.2 Resistance contributions 2.4.3 Device model and channel mobility 2.4.4 Threshold voltage and subthreshold slope 2.4.5 Interface and dielectric trap states in wide band semiconductors 2.4.6 The body bias effect 3 Fabrication and characterisation 3.1 Growth methods for GaN substrates and layers 3.2 Substrates and the desired starting material 3.2.1 Physical and micro-structural characterisation 3.2.2 Dislocations and impurities 3.3 Pseudo- and true-vertical MOSFET fabrication 3.3.1 Processing routes 3.3.2 Inductively-coupled plasma etching 3.3.3 Process flow modification 3.4 Electrical characterisation, structures and process control 3.4.1 Current voltage characterisation 3.4.2 C(V) measurements and charge carrier profiling 3.4.3 Cooperative characterisation structures 4 Properties of the functional layers 4.1 Morphology of the MOVPE grown layers 4.2 Hydrogen out-diffusion treatment 4.3 Morphology of the n+-source layer grown by MBE 4.4 N-type doping of the functional layers 4.5 P-type GaN by magnesium doping 4.6 Structural properties after the etching and gate module formation 4.7 Electrical layer characterization 4.7.1 Gate dielectric and interface evaluation 5 Pseudo- and true vertical device operation 5.1 Influences of the metal-line sheet resistance 5.2 Formation and characterisation of ohmic contacts 5.2.1 Ohmic contacts to n-type GaN 5.2.2 Ohmic contacts to p-GaN 5.3 The pn- body diode 5.4 MOSFET operation 5.4.1 ON-state and turn-ON operation 5.4.2 The body bias effect on the threshold voltage 5.4.3 Device OFF-state 6 Summary and conclusion 6.1 Device performance 6.2 Current limits of the vertical device technology 6.3 Possibilities for advancements Bibliography A Appendix A.1 Deduction: Forward diffusion current of the pn-diode A.2 Deduction: Operation regions in the EKV model Figures Tables Abbreviations Symbols Postamble and Acknowledgement

Cette thèse concerne l’étude des procédés de fabrication des grilles HKMG des technologies FDSOI 14 et 28 nm sur les performances électriques des transistors MOS. Elle a porté spécifiquement sur l'aspect fiabilité et la maîtrise du travail de sortie effectif (WFeff), au travers de la diffusion des additifs comme le lanthane (La) et l’aluminium (Al). Ce travail combine des techniques de caractérisation électriques et physico-chimiques et leur développement. L'effet de l'incorporation de ces additifs sur la fiabilité et la durée de vie du dispositif a été étudié. Le lanthane dégrade les performances de claquage TDDB et de dérives suite aux tests aux tensions négatives. L’introduction d’aluminium améliore le claquage TDDB, mais dégrade les dérives aux tensions positives. Ces comportements ont été reliés à des mécanismes physiques. Par ailleurs, la diffusion de ces additifs dans l’empilement de grille a été étudiée pour différents matériaux high-k en fonction de la température et de la durée de recuit de diffusion. Les doses d’additifs ont pu être ainsi mesurées, comparées et corrélées au décalage de travail de sortie effectif de grille. On a également étudié, les influences des paramètres du procédé de dépôt de grille TiN sur leur microstructure et les propriétés électriques du dispositif, identifiant certaines conditions à même de réduire la taille de grain ou la dispersion d’orientation cristalline. Toutefois, les modulations obtenues sur le travail de sortie effectif de grille dépendent plus du ratio Ti/N, suggérant un changement du dipôle à l'interface SiO2 / high-k. Enfin, une technique éprouvée de mesure de spectroscopie à rayon X sous tension a pu être mise en place grâce des dispositifs spécifiques et une méthodologie adaptée. Elle permet de mesurer les positions relatives des bandes d’énergie à l'intérieur de l’empilement de grille. Cette technique a démontré que le décalage du travail de sortie effectif induits par des additifs (La or Al) ou par des variations d'épaisseur de grille métallique TiN provient de modifications du dipôle à l'interface SiO2/ high-k. / This Ph.D. thesis is focused on the impact of the 14 and 28 nm FDSOI technologies HKMG stack processes on the electrical performance of MOS transistors. It concerns specifically the reliability aspect and the engineering of effective workfunction (WFeff ), through diffusion of lanthanum (La) and aluminum (Al) additives. This work combines electrical and physicochemical characterization techniques, and their development. The impact of La and Al incorporation, in the MOS gate stack, on reliability and device lifetime has been studied. La addition has a significant negative impact on device lifetime related to both NBTI and TDDB degradations. Addition of Al has a significant negative impact on lifetime related to PBTI, but on the contrary improves the lifetime for TDDB degradation. These impacts on device lifetime have been well correlated to the material changes inside the gate oxides. Moreover, diffusion of these additives into the HKMG stack with annealing temperature and time has been studied on different high-k materials. The diffused dose has been compared with the resulting shift in effective workfunction (WFeff), evidencing clear correlation. In addition, impact of TiN metal gate RF-PVD parameters on its crystal size and orientation, and device electrical properties has been studied. XRD technique has been used to obtain the crystal size and orientation information. These properties are significantly modulated by TiN process, with a low grain size and a unique crystal orientation obtained in some conditions. However, the WFeff modulations are rather correlated to the Ti/N ratio change, suggesting a change in the dipole at SiO2/high-k interface. Lastly, using specific test structures and a new test methodology, a robust and accurate XPS under bias technique has been developed to determine the relative band energy positions inside the HKMG stack of MOS devices. Using this technique, we demonstrated that WFeff shift induced by La and Al or by variations in gate thickness originates due to modifications of the dipole at SiO2/high-k interface.

Le titanate de baryum et de strontium (BaSrTiO3) est un matériau diélectrique de synthèse à forte permittivité possédant la propriété d'être accordable lorsqu'il est soumis à un champ électrique. Ceci est lié à sa structure cristalline à maille perovskite. Son intégration dans des dispositifs capacitifs est donc prometteuse pour l'industrie de la microélectronique. Il est déposé en couches minces par pulvérisation cathodique à partir de cibles pressées à froid au sein du laboratoire. L'étude de la croissance du matériau, dopé ou non, et de ses propriétés électriques à 100 khz ont permis d'envisager une montée en fréquence. Les évolutions de la permittivité diélectrique complexe et de l'accordabilité du matériau ont ainsi pu être étudiées sur un dispositif spécifique dans une gamme de fréquences allant de 1 à 60 ghz. L'utilisation d'un logiciel de simulation numérique par éléments finis (ELFI) dans le cadre de l'étude à haute fréquence permet de remonter aux caractéristiques propres du matériau, et ainsi d'interpréter plus finement les résultats issus de l'étude en basse fréquence. L'ensemble des connaissances acquises permet finalement de développer des dispositifs à capacité variable qui sont actuellement en cours d'élaboration au sein du laboratoire. / The barium and strontium titanate (BST) is a human made dielectric material with a high dielectric constant which is tunable once submitted to an electric field. This is due to its crystalline structure based on a perovkite mesh. Its integration into capacitive devices is thus fully promising for microelectronic industry. The material is deposited by RF magnetron sputtering from cold pressed targets made in the laboratory. Studying the growth of the material, doped or not, and its electrical properties at 100 kHz has allowed increasing frequency. The variations of the complex permittivity and tunability have thus been studied on a range of frequencies from 1 to 60 GHz. Using the numerical simulation software Elfi enables one to get a good estimation of the intrinsic properties of BST and a sharper explanation of the results obtained at low frequencies. This knowledge finally allows engineering in varactor devices, which is now in progress.

Nanokristalle werden beispielsweise für eine Anwendung in Solarzellen, Lichtemittern und nichtflüchtigen Datenspeichern diskutiert. Damit diese Anwendungen funktionieren können, ist eine genaue Kontrolle der Kristallitgröße sowie der Flächendichte und Lage der Kristallite in der Matrix wichtig. Zudem sollte die Matrix amorph sein, da amorphe Matrixmaterialien die Nanokristall-Oberfläche besser passivieren und beständiger gegen Leckströme sind. In dieser Arbeit werden Ge-Nanokristalle in die Hoch-Epsilon-Dielektrika ZrO2 und TaZrOx eingebettet. Im System Ge/ZrO2 kristallisieren die Ge-Cluster und die ZrO2-Matrix bei der gleichen Temperatur. Aufgrund der kristallinen Matrix weicht die Form der Ge-Nanokristalle von einer Kugel ab, worunter unter anderem die Größenkontrolle leidet. Die Beimischung von Ta2O5 stabilisiert die amorphe Phase des ZrO2 und verhindert dadurch die gemeinsame Kristallisation. Dadurch wird es im System Ge/TaZrOx möglich, kugelförmige Ge-Nanokristalle im Größenbereich von 3 nm bis 6 nm positionskontrolliert in eine amorphe Matrix einzubetten. Für die Untersuchung einer möglichen Anwendung des Materialsystems wurden Speicherzellen eines nichtflüchtigen Datenspeichers auf Basis von Ge-Nanokristallen hergestellt. Dabei zeigte sich, dass das System Ge/TaZrOx überdurchschnittlich viele Ladungen speichert und daher für diese Anwendung vielversprechend ist. Zudem stabilisiert die Beimischung von Ta2O5 eine extrem seltene orthorhombische Modifikation des ZrO2. Für ferroelektrische Datenspeicher könnte diese Phase eine aussichtsreiche Alternative zum HfO2 sein.

Dans les systèmes actuels de communication, qu’ils soient terrestre ou spatial, qu’ils soient mobile ou fixe, il y a un réel intérêt à développer des front-ends radiofréquences et hyperfréquences miniatures et performants. Ceci s’applique en particulier aux dispositifs de filtrage où l’encombrement et les facteurs de qualité sont clairement antagonistes. Pour les bandes de fréquences basses aux alentours du GHz, les longueurs d’onde restent encore importantes, rendant difficiles les efforts de miniaturisation. D’autre part il faut aussi s’assurer que ces filtres viendront s’interconnecter aisément avec les autres composants du système, notamment les actifs.Pour toutes ces raisons, le développement de structures de filtres multicouches utilisant des substrats à haute permittivité (εr = 68) selon une approche LTCC apparait comme une alternative intéressante. Elle peut en effet conduire à une réduction significative de l'empreinte (footprint) sans pour autant trop nuire aux performances électriques.Dans le cadre de ce travail, deux structures de filtres multicouches ont été développées pour répondre à des spécifications proposées en bandes L et S, par un équipementier du spatial. Ces filtres ont pour caractéristiques principales un haut niveau de rejection et des faibles pertes dans la bande passante. Pour atteindre les spécifications, un filtre SIW empilé verticalement et un filtre à stubs en court-circuit en configuration triplaque ont été étudiés. Le filtre SIW se distingue par un facteur de qualité élevé, ce qui entraîne des faibles pertes d’insertion et une bonne platitude. La solution à stub permet quant à elle de réduire l’encombrement mais au prix d’un impact sur les performances électriques. Dans les deux cas on tire parti de la souplesse offerte par la technologie LTCC, puisqu’elle offre finalement un degré de liberté supplémentaire, par rapport à une approche planaire classique. Si dans le cas SIW, c’est surtout l’architecture topologique qui a été étudiée finement pour pouvoir agencer et coupler douze cavités, dans le cas du filtre à stub une synthèse mettant à profit tous les degrés de liberté offerts a été spécifiquement développée.Compte tenu de la complexité des filtres, notamment à cause de l’ordre élevé et de la mise en oeuvre de murs « électriques » à partir d’arrangements de via spécifiques, une attention particulière doit être apportée lors des phases de simulation et d’optimisation. De plus la très forte permittivité du substrat ne permet pas d’utiliser de ligne 50 Ohms. Enfin les transitions constituent un point dur de l’exercice surtout dans le cas SIW.Cette thèse co-financée par le CNES (Centre National d'Etudes Spatiales) et Thales Alenia Space, était accompagnée par un projet R&T financé par le CNES. Le fondeur allemand Via Electronic avait en charge la fabrication des filtres. / In current communication systems, whether terrestrial or spatial, whether fixed or mobile, there is a real interest in developing high performance miniature RF front-ends. This is applied in particular to filter devices, in which the size and the quality factors are clearly in conflict. For low frequency bands around the GHz, the wavelengths remain significant, making it difficult the miniaturization efforts. On the other hand, we must also ensure that these filters will be easily interconnected with other other system components, including active devices.For all these reasons, the development of multilayer filter structures using high permittivity substrates (Er = 68) in an LTCC approach is consolidated as an interesting alternative. It may lead to a significant footprint reduction without decreasing the electrical performances.As part of this work, two multilayer filter structures have been developed to meet the given specifications in L and S bands, given by a space manufacturer. These filters have as main features a high rejection level and low losses in the passband. To meet the specifications, a vertically stacked SIW filter and a short-circuited stubs filter in a stripline configuration were studied. The SIW filter is characterized by a high quality factor, which results in low insertion loss and good flatness. The stubs filter allows in contrast to reduce the footprint but at the price of impacting the electrical performance. In both cases we take advantage of the flexibility offered by the LTCC technology as it finally provides an additional freedom degree compared to a conventional planar approach. For the SIW filter, the topological architecture was studied and designed in detail, to be able to arrange and synthetize couplings between twelve cavities. In a similar way, for the stub filter a synthesis that takes profit of all the offered freedom degrees was developed.Given the filters complexity, especially due to the high order and the implementation of “electrical walls" based on specific vias patterns, a close attention must be paid during the simulation and optimization phase. In addition, the high permittivity substrate does not allow to conceive 50-Ohms lines. Finally, access transitions constitute a challenging task, especially for the SIW case.This thesis was co-funded by CNES (Centre National d'Etudes Spatiales) and Thales Alenia Space, and was accompanied by an R&T project funded by CNES. The German foundry Via Electronic was responsible for the filters fabrication.

Les mémoires flash non volatiles - utilisées dans les ordinateurs, téléphones portables ou clés USB - peuvent être constituées de nanocristaux semiconducteurs (SC) insérées dans une matrice isolante. Elles nécessitent l'élaboration d'hétérostructures de type "oxyde/SC/oxyde/Si(00l)" et la maîtrise de chaque interface. Dans ce cadre, nous avons étudié les mécanismes de croissance initiale du Si et du Ge (SC) sur des substrats d'oxyde cristallins LaA1O3(001) à forte permittivité (high-k). Les propriétés chimiques et structurales ont été déterminées in-situ par photoémission X (XPS et XPD) et par diffraction d'électrons (RHEED et LEED) puis ex-situ par microscopies en champ proche (AFM) et en transmission (HRTEM). Le substrat LaAlO3(001) propre présente une reconstruction de surface c(2x2) attribuée à des lacunes d'O en surface. Les croissances de Si et Ge ont été réalisées par épitaxie par jet moléculaire (MBE), soit à température ambiante suivies de recuits, soit à haute température. L'épitaxie requiert des températures de dépôt supérieures à 550°C. Le mode de croissance est de type Volmer Weber caractérisé par la formation d'îlots cristallins de dimensions nanométriques et de forte densité. Ces îlots sont relaxés et présentent une interface abrupte avec le substrat. Quant aux îlots de Ge, ils ont majoritairement des orientations aléatoires avec néanmoins une relation d'épitaxie privilégiée, la même que celle du Si.

L'introduction de diélectriques de forte permittivité dit « High-Κ » peut faire apparaître des comportements jusqu'ici négligeables. C'est le cas du phénomène de relaxation diélectrique. Ce mémoire traite de l'étude de ce phénomène dans les capacités Métal-Isolant-Métal intégrés en microélectronique. Au travers de plusieurs diélectriques amorphes et d'un diélectrique ferroélectrique, deux comportements sont identifiés, le comportement de « flat loss » et celui de polarisation d'électrode. Comme la relaxation diélectrique peut dégrader les performances de certains circuits, une modélisation a été proposée grâce à la réalisation d'un circuit de mesure de l'effet mémoire. Puis l'étude détaillée du comportement du diélectrique Ta2O5, aussi bien en terme de stabilité de courant qu'en terme de variation de permittivité dans les basses fréquences, permettra de mettre en évidence la migration de lacunes d'oxygène dans le diélectrique. Finalement, deux solutions sont proposées afin de réduire le phénomène de relaxation diélectrique tout en obtenant de bonnes performances électriques. La première consiste à déposer des stacks diélectrique basés sur les performances du Ta2O5. La seconde propose l'intégration d'un nouveau diélectrique, l'oxyde de Zirconium.

In-based III-V compound semiconductors have higher electron mobilities than either Si or Ge and direct band gaps. These properties could enable the fabrication of low power, high-speed n-channel metal oxide semiconductor field effect transistors (MOSFETs) and optoelectronics combining MOS technology with photonics. Since thermal and native oxides formed on III-V surfaces exhibit large current leakage and high densities of trap states, a key to incorporating these materials into advanced devices is the development of processing steps that form stable interfaces with dielectric layers. In this thesis, a processing flow consisting of native oxide removal using HF chemistries and deposition of high dielectric permittivity films using atomic layer deposition was investigated. Understanding the reaction mechanisms of these processes could provide the means of controlling composition and structure, yielding a desired electronic behavior. Quantitative X-ray photoelectron spectroscopy analysis of surfaces was coupled with electrical measurements on MOS capacitors of the interface quality in order to understand the nature of high-k/III-V interface defects and their repair. Ex situ liquid phase HF etching removed InSb, InAs, and InGaAs(100) native oxides and produced an Sb- or As-enriched surface, which oxidized when exposed to air. A 5 to 22 °A thick As- and Sb-rich residual oxide was left on the surface after etching and < 5 min of air exposure. The results showed that group V enrichment originated from the reduction of group V oxides by protons in the solution and the preferential reaction of HF with the group III atom of the substrate. A sub-atmospheric in situ gas phase HF/H2O process removed native oxide from InSb, InAs, and InGaAs(100) surfaces, producing an In or Ga fluoride-rich sacrificial layer. A 50 to 90% oxide removal was achieved and a 10 to 25 °A-thick overlayer consisting of mainly In and Ga fluorides was produced. The composition and morphology of the sacrificial layer were controlled by the partial pressure of H2O as well as the ratio of HF to H2O used. Water played a critical role in the process by directly participating in the etching reaction and promoting the desorption of fluoride etching products. Accumulation of thick fluoride layer at high HF to water partial pressure ratios prevented adsorption and diffusion of etchant to the buried residual oxide. When oxide was removed, HF preferentially reacted with In or Ga atoms from the substrate, enriching the surface with group III fluorides and producing approximately one monolayer of elemental group V atoms at the interface. Interface reactions occurred during atomic layer deposition of Al2O3, in which trimethylaluminum (TMA) removed surface oxides and fluorides. Chemically sharp InSb/Al2O3 and InGaAs/Al2O3 interfaces were achieved for gas phase HF-etched InSb and liquid phase HF-etched InGaAs. A ligand transfer mechanism promotes nucleation of Al2O3 and removal of III-V atoms from the sacrificial oxide and fluoride layers as volatile trimethyl indium, gallium, arsenic, and antimony. These reactions have been explained by the relative bond strength of surface and precursor metal atoms with O and F. Interaction of a InSb(100) surface with TiCl4 as a model for metal halide ALD precursors showed that similar ligand transfer reactions occured. Adsorbed chlorine from the dissociative adsorption of TiCl4 on the InSb surface at elevated temperature, however, preferentially etched In atoms from the substrate and produced a roughened surface. The quality of InGaAs/Al2O3 interfaces prepared by solvent cleaning and liquid phase HF were assesed electrically using capacitance-voltage and conductance measurements. Surface recombination velocity (SRV) values were extracted from the measurements to represent the net effect of interface defects, which includes defect density and capture cross section. The InGaAs/Al2O3 interface prepared by solvent cleaning consisted of interfacial native oxides while that etched in liquid phase HF consisted of submonolayer arsenic oxide. The two chemically contrasting interfaces, however, gave similar SRV values of 34.4±3.7 and 28.9±13.4 cm/s for native oxide and liquid phase HF prepared samples, respectively. This suggests that the presence or absence of oxides was not the only determining factor. Post Al2O3 deposition annealing in forming gas and NH3 ambient significantly improved the electrical quality for both surfaces, as shown by SRV values between 1 to 4 cm/s which is comparable to that of an ideal H-terminated Si surface. XPS analysis showed that the contribution from elemental As and Ga2O3 at the interface of both surfaces increased after annealing in forming gas and NH3, likely due to thermal or hydrogen-induced reaction between interfacial As oxide and Ga atoms in the substrate. There was no correlation between the atomic coverages of interfacial elemental As and oxides to the SRV values. High activity defects at III-V/Al2O3 interfaces are associated with interfacial dangling bonds which were passivated thermally and chemically by annealing in forming gas and NH3.

Transparent oxide semiconducting films have continued to receive considerable attention, from a fundamental and application-based point of view, primarily because of their useful fundamental properties. Of particular interest is zinc oxide (ZnO), an n-type semiconductor that exhibits excellent optical, electrical, catalytic and gas-sensing properties, and has many applications in various fields. In this work, thin film transistor (TFT) arrays based on ZnO have been prepared by reactive radio frequency (RF) magnetron sputtering. Prior to the TFT fabrication, ZnO layers were sputtered on to glass and silicon substrates, and the deposition parameters optimised for electrical resistivities suitable for TFT applications. The sputtering process was carried out at room temperature with no intentional heating. The aim of this work is to prepare ZnO thin films with stable semiconducting electrical properties to be used as the active channel in TFTs; and to understand the role of intrinsic point defects in device performance and stability. The effect of oxygen (O2) adsorption on TFT device characteristics is also investigated. The structural quality of the material (defect type and concentration), electrical and optical properties (transmission/absorption) of semiconductor materials are usually closely correlated. Using the Vienna ab-initio simulation package (VASP), it is predicted that O2 adsorption may influence film transport properties only within a few atomic layers beneath the adsorption site. These findings were exploited to deposit thin films that are relatively stable in atmospheric ambient with improved TFT applications. TFTs incorporating the optimised layer were fabricated and demonstrated very impressive performance metrics, with effective channel mobilities as high as 30 cm2/V-1s-1, on-off current ratios of 107 and sub-threshold slopes of 0.9 – 3.2 V/dec. These were found to be dependent on film thickness (~15 – 60 nm) and the underlying dielectric (silicon dioxide (SiO2), gadolinium oxide (Gd2O3), yttrium oxide (Y2O3) and hafnium oxide (HfO2)). In this work, prior to sputtering the ZnO layer (using a ZnO target of 99.999 % purity), the sputtering chamber was evacuated to a base pressure ~4 x 10-6 Torr. Oxygen (O2) and argon (Ar) gas (with O2/Ar ratio of varying proportions) were then pumped into the chamber and the deposition process optimised by varying the RF power between 25 and 500 W and the O2/Ar ratio between 0.010 to 0.375. A two-level factorial design technique was implemented to test specific parameter combinations (i.e. RF power and O2/Ar ratio) and then statistical analysis was utilised to map out the responses. The ZnO films were sputtered on glass and silicon substrates for transparency and resistivity measurements, and TFT fabrication respectively. For TFT device fabrication, ZnO films were deposited onto thermally-grown silicon dioxide (SiO2) or a high-k dielectric layer (HfO2, Gd2O3 and Y2O3) deposited by a metal-organic chemical deposition (MOCVD) process. Also, by using ab initio simulation as implemented in the “Vienna ab initio simulation package (VASP)”, the role of oxygen adsorption on the electrical stability of ZnO thin film is also investigated. The results indicate that O2 adsorption on ZnO layers could modify both the electronic density of states in the vicinity of the Fermi level and the band gap of the film. This study is complemented by studying the effects of low temperature annealing in air on the properties of ZnO films. It is speculated that O2 adsorption/desorption at low temperatures (150 – 350 0C) induces variations in the electrical resistance, band gap and Urbach energy of the film, consistent with the trends predicted from DFT results.

High-k/metal gate stacks have been introduced in CMOS technology during the last decade in order to sustain continued device scaling and ever-improving circuit performance. Starting from the 45 nm technology node, the stringent requirements in terms of equivalent oxide thickness and gate current density have rendered the replacement of the conventional SiON/poly-Si stack unavoidable. Although Hf-based technology has become the de facto industry standard for high-k/metal gate MOSFETs, problematic long-term scalability has motivated the research of novel materials and solutions to fulfill the target performances expected of gate stacks in future technology nodes. In this work, integration of a high-k interfacial layer has been identified as the most promising approach to improve gate dielectric scalability, since this technology presents the advantage of potential compatibility with both current Hf-based and plausible future higher-k materials. Thulium silicate has been selected as candidate material for integration as interfacial layer, thanks to its unique properties which enabled the development of a straightforward integration process achieving well-controlled and repeatable growth in the sub-nm thickness regime, a contribution of 0.25+-0.15 nm to the total EOT, and high quality of the interface with Si. Compatibility with industry-standard CMOS integration flows has been kept as a top priority in the development of the new technology. To this aim, a novel ALD process has been developed and characterized, and a manufacturable process flow for integration of thulium silicate in a generic gate stack has been designed. The thulium silicate interfacial layer technology has been verified to be compatible with standard integration flows, and fabrication of high-k/metal gate MOSFETs with excellent electrical characteristics has been demonstrated. The possibility to achieve high performance devices by integration of thulium silicate in current Hf-based technology has been specifically demonstrated, and the TmSiO/HfO2 dielectric stack has been shown to be compatible with the industrial requirements of operation in the sub-nm EOT range (down to 0.6 nm), reliable device operation over a 10 year expected lifetime, and compatibility with common threshold voltage control techniques. The thulium silicate interfacial layer technology has been especially demonstrated to be superior to conventional chemical oxidation in terms of channel mobility at sub-nm EOT, since the TmSiO/HfO2 dielectric stack achieved ~20% higher electron and hole mobility compared to state-of-the-art SiOx/HfO2 devices at the same EOT. Such performance enhancement can provide a strong advantage in the EOT-mobility trade-off which is commonly observed in scaled gate stacks, and has been linked by temperature and stress analyses to the higher physical thickness of the high-k interfacial layer, which results in attenuated remote phonon scattering compared to a SiOx interfacial layer achieving the same EOT. / <p>QC 20140512</p>