Modeling and analysing materials with theoretical tools is of great use when finding new systems for applications, for example, semiconductors with point defects can be used for quantum applications, like single photon emitters. One important aspect to consider symmetry, which can yield useful information about the properties of a system. To perform symmetry analysis, a code was developed that takes the orbitals of atomic structures, as calculated with Density Functional Theory simulations, as input. Specifically, the orbitals of molecules, and defects in solids are in focus. The symmetry analysis code calculates overlap of orbitals and their symmetry transformed counterpart, maps these overlaps to characters, finds the irreducible representations, and also finds which optical transitions are allowed. The code was tested on CH4 and SF6 molecules, and the divacancy defect in 4H-SiC. The symmetry analysis is performed easily and produces results that coincide well with other theoretical results. Furthermore, symmetry matrices can be approximated to be integer matrices, and the wave functions can be approximated with less accurate plane wave expansions by reducing the cutoff energy, and thus reducing the number of plane waves. These approximations shorten the calculation time and do not compromise the accuracy of the overlap. The code automates the symmetry analysis and is intended to be used in a high-throughput manner. / <p>2021-10-12          </p><p>The student thesis was first published online. </p><p>2022-02-25          </p><p>The student thesis was updated with an errata list which is downloadable from the permanent link.</p>

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Ce travail est consacré à l’étude de l’incorporation volontaire des dopants dans des films de carbure de silicium épitaxiés par la technique de dépôt chimique en phase vapeur. Le rôle des principaux paramètres de croissance (température, flux de dopant, vitesse de dépôt, pression dans le réacteur et le rapport C/Si) sur l’incorporation d’azote et d’aluminium a été étudié en détail. Les travaux menés jusqu’ici ont largement exploré les caractéristiques de l’incorporation de dopants, en particulier l’incorporation d’azote et ont montré des résultats parfois très dépendants de l’équipement de croissance utilisé. Afin d’explorer cette influence, une étude expérimentale exhaustive sur l’incorporation de N et Al a été réalisée sur des couches homoépitaxiées 4H-SiC sur la face carbone et sur la face silicium de substrats 4H-SiC dans nos réacteurs CVD. Cette étude a été complétée par une analyse des propriétés structurales, optiques et électriques de couches 4H-SiC dopé Al. Aussi, la fabrication de diodes pn a été expérimentée sur les couches épitaxiées dans nos réacteurs. Nous avons pu observer différentes tendances expérimentales selon la nature du dopant, l’orientation cristalline du substrat et l’environnement chimique durant la croissance. Nous en déduisons que le mécanisme derrière les tendances observées est largement influencé par des facteurs comme les conditions de croissance (c'est-à-dire la température de croissance et/ou la pression) et la couverture de carbone à la surface de la croissance, surtout sur la face C / This work is dedicated to the investigation of intentional dopant incorporation in silicon carbide epilayers grown by chemical vapor deposition technique. The role of main process conditions (growth temperature, dopant supply, deposition rate, growth pressure and C/Si ratio) on both, Nitrogen and Aluminum incorporation was studied in details. Previous works have widely explored the characteristics of dopant incorporation, especially the nitrogen incorporation addressing a potential influence of growth equipment for the observed incorporation trends. An exhaustive experimental study of N and Al incorporation was performed for homoepitaxial 4H-SiC layers grown on Si- and C-faces of 4H-SiC substrates in our CVD setups to explore such influence. It was completed by the assessment of the structural, optical and electrical properties of the Al doped 4H-SiC films. Furthermore, the fabrication of pn diodes was tested on the grown layers. We have observed different experimental tendencies depending on dopant nature, crystal orientation and chemical environment. We conclude from these observations that the mechanism behind the experimentally obtained tendencies is widely influenced by factors such as process conditions (i.e. growth temperature and/or pressure) and the carbon coverage at the grown surface, especially on C-face

Kyoto University (京都大学) / 0048 / 新制・課程博士 / 博士(工学) / 甲第17581号 / 工博第3740号 / 新制||工||1570(附属図書館) / 30347 / 京都大学大学院工学研究科電子工学専攻 / (主査)教授 木本 恒暢, 教授 藤田 静雄, 准教授 浅野 卓 / 学位規則第4条第1項該当

4H-SiC-based bipolar junction transistors (BJTs) are attractive devices for high-voltage and high-temperature operations due to their high current capability, low specific on-resistance, and process simplicity. To extend the potential of SiC BJTs to power electronic industrial applications, it is essential to realize high-efficient devices with high-current and low-loss by a reliable and wafer-scale fabrication process. In this thesis, we focus on the improvement of the 4H-SiC BJT performance, including the device optimization and process development. To optimize the 4H-SiC BJT design, a comprehensive study in terms of cell geometries, device scaling, and device layout is performed. The hexagon-cell geometry shows 42% higher current density and 21% lower specific on-resistance at a given maximum current gain compared to the interdigitated finger design. Also, a layout design, called intertwined, is used for 100% usage of the conducting area. A higher current is achieved by saving the inactive portion of the conducting area. Different multi-step etched edge termination techniques with an efficiency of &gt;92% are realized. Regarding the process development, an improved surface passivation is used to reduce the surface recombination and improve the maximum current gain of 4H-SiC BJTs. Moreover, wafer-scale lift-off-free processes for the n- and p-Ohmic contact technologies to 4H-SiC are successfully developed. Both Ohmic metal technologies are based on a self-aligned Ni-silicide (Ni-SALICIDE) process. Regarding the device characterization, a maximum current gain of 40, a specific on-resistance of 20 mΩ·cm2, and a maximum breakdown voltage of 5.85 kV for the 4H-SiC BJTs are measured. By employing the enhanced surface passivation, a maximum current gain of 139 and a specific on-resistance of 579 mΩ·cm2 at the current density of 89 A/cm2 for the 15-kV class BJTs are obtained. Moreover, low-voltage 4H-SiC lateral BJTs and Darlington pair with output current of 1−15 A for high-temperature operations up to 500 °C were fabricated. This thesis focuses on the improvement of the 4H-SiC BJT performance in terms of the device optimization and process development for high-voltage and high-temperature applications. The epilayer design and the device structure and topology are optimized to realize high-efficient BJTs. Also, wafer-scale fabrication process steps are developed to enable realization of high-current devices for the real applications. / <p>QC 20170810</p>

<div>Power semiconductor devices play an important role in many areas, including household</div><div>appliances, electric vehicles, high speed trains, electric power stations, and renewable energy</div><div>conversion. In the modern era, silicon based devices have dominated the semiconductor</div><div>market, including power electronics, because of their low cost and high performance. The</div><div>applications of devices rated 600 V - 6.5 kV are still dominated by silicon devices, but they</div><div>are nearly reaching fundamental material limits. New wide band gap materials such as silicon</div><div>carbide (SiC) offer significant performance improvements due to superior material properties</div><div>for such applications in and beyond this voltage range. 4H-SiC is a strong candidate</div><div>among other wide band gap materials because of its high critical electric field, high thermal</div><div>conductivity, compatibility with silicon processing techniques, and the availability of high</div><div>quality conductive substrates.</div><div>Vertical DMOSFETs and insulated gate bipolar transistors (IGBT) are key devices for</div><div>high voltage applications. High blocking voltages require thick drift regions with very light</div><div>doping, leading to specific on-resistance (R_ON,SP ) that increases with the square of blocking</div><div>voltage (V_BR). In theory, superjunction drift regions could provide a solution because of a</div><div>linear dependence of R_ON,SP on V_BR when charge balance between the pillars is achieved</div><div>through extremely tight process control. In this thesis, we have concluded that superjunction</div><div>devices inevitably have at least some level of charge imbalance which leads to a quadratic</div><div>relationship between V_BR and R_ON,SP . We then proposed an optimization methodology to</div><div>achieve improved performance in the presence of this inevitable imbalance.</div><div>On the other hand, an IGBT combines the benefits of a conductivity modulated drift</div><div>region for significantly reduced specific on-resistance with the voltage controlled input of a</div><div>MOSFET. Silicon carbide n-channel IGBTs would have lower conduction losses than equivalent</div><div>DMOSFETs beyond 6.5 kV, but traditionally have not been feasible below 15 kV. This</div><div>is due to the fact that the n+ substrate must be removed to access the p+ collector of the</div><div>IGBT, and devices below 15 kV have drift layers too thin to be mechanically self-supporting.</div><div>In this thesis, we have demonstrated the world’s first functional 10 kV class n-IGBT with</div><div>a waffle substrate through simulation, process development, fabrication and characterization.</div><div><div>The waffle substrate would provide the required mechanical support for this class of devices.</div><div>The fabricated IGBT has exhibited a differential R_ON,SP of 160 mohm</div><div>.cm², less than half of</div><div>what would be expected without conductivity modulation. An extensive fabrication process</div><div>development for integrating a waffle substrate into an active IGBT structure is described</div><div>in this thesis. This process enables an entirely new class of moderate voltage SiC IGBTs,</div><div>opening up new applications for SiC power devices.</div></div>

En raison de l'attrait croissant pour les applications haute tension, haute tempé-rature et haute fréquence, le carbure de silicium (SiC) continue d'attirer l'attention du monde entier comme l'un des candidats les plus compétitifs pour remplacer le sili-cium dans le champ électrique de puissance. Entre-temps, il est important de carac-tériser les défauts des semi-conducteurs et d'évaluer leur influence sur les dispositifs de puissance puisqu'ils sont directement liés à la durée de vie du véhicule porteur. De plus, la fiabilité, qui est également affectée par les défauts, devient une question incontournable dans le domaine de l'électricité de puissance.Les défauts, y compris les défauts ponctuels et les défauts prolongés, peuvent introduire des niveaux d'énergie supplémentaires dans la bande passante du SiC en raison de divers métaux comme le Ti, le Fe ou le réseau imparfait lui-même. En tant que méthode de caractérisation des défauts largement utilisée, la spectroscopie à transitoires en profondeur (DLTS) est supérieure pour déterminer l'énergie d'activa-tion Ea , la section efficace de capture Sigma et la concentration des défauts Nt ainsi que le profil des défauts dans la région d'épuisement grâce à ses divers modes de test et son analyse numérique avancée. La détermination de la hauteur de la barrière Schottky (HBS) prête à confusion depuis longtemps. Outre les mesures expérimentales selon les caractéristiques I-V ou C-V, différents modèles ont été proposés, de la distribution gaussienne du HBS au modèle de fluctuation potentielle. Il s'est avéré que ces modèles sont reliés à l'aide d'une hauteur de barrière à bande plate Phi_BF . Le tracé de Richardson basé sur Phi_BF ainsi que le modèle de fluctuation potentielle deviennent un outil puissant pour la caractérisation HBS. Les HBSs avec différents contacts métalliques ont été caractéri-sés, et les diodes à barrières multiples sont vérifiées par différents modèles. Les défauts des électrons dans le SiC ont été étudiés avec des diodes Schottky et PiN, tandis que les défauts des trous ont été étudiés dans des conditions d'injec-tion forte sur des diodes PiN. 9 niveaux d'électrons et 4 niveaux de trous sont com-munément trouvés dans SiC-4H. Une relation linéaire entre le Ea extrait et le log(sigma) indique l'existence de la température intrinsèque de chaque défaut. Cependant, au-cune différence évidente n'a été constatée en ce qui concerne l'inhomogénéité de la barrière à l'oxyde d'éther ou le métal de contact. De plus, les pièges à électrons près de la surface et les charges positives fixes dans la couche d'oxyde ont été étudiés sur des MOSFET de puissance SiC par polarisation de porte à haute température (HTGB) et dose ionisante totale (TID) provoquées par irradiation. Un modèle HTGB-assist-TID a été établi afin d'ex-plain l'effet de synergie. / Due to the increasing appeal to the high voltage, high temperature and high fre-quency applications, Silicon Carbide (SiC) is continuing attracting world’s attention as one of the most competitive candidate for replacing silicon in power electric field. Meanwhile, it is important to characterize the defects in semiconductors and to in-vestigate their influences on power devices since they are directly linked to the car-rier lifetime. Moreover, reliability that is also affected by defects becomes an una-voidable issue now in power electrics. Defects, including point defects and extended defects, can introduce additional energy levels in the bandgap of SiC due to various metallic impurities such as Ti, Fe or intrinsic defects (vacancies, interstitial…) of the cristalline lattice itself. As one of the widely used defect characterization method, Deep Level Transient Spectroscopy (DLTS) is superior in determining the activation energy Ea , capture cross section sigma and defect concentration Nt as well as the defect profile in the depletion region thanks to its diverse testing modes and advanced numerical analysis. Determination of Schottky Barrier Height (SBH) has been confusing for long time. Apart from experimental measurement according to I-V or C-V characteristics, various models from Gaussian distribution of SBH to potential fluctuation model have been put forward. Now it was found that these models are connected with the help of flat-band barrier height Phi_BF . The Richardson plot based on Phi_BF along with the potential fluctuation model becomes a powerful tool for SBH characterization. SBHs with different metal contacts were characterized, and the diodes with multi-barrier are verified by different models. Electron traps in SiC were studied in Schottky and PiN diodes, while hole traps were investigated under strong injection conditions in PiN diodes. 9 electron traps and 4 hole traps have been found in our samples of 4H-SiC. A linear relationship between the extracted Ea and log(sigma) indicates the existence of the intrinsic temper-ature of each defects. However, no obvious difference has been found related to ei-ther barrier inhomogeneity or contact metal. Furthermore, the electron traps near in-terface and fixed positive charges in the oxide layer were investigated on SiC power MOSFETs by High Temperature Gate Bias (HTGB) and Total Ionizing Dose (TID) caused by irradiation. An HTGB-assist-TID model was established in order to ex-plain the synergetic effect.