Cette thèse s'intéresse à la rhéologie de deux des principaux minéraux du manteau supérieur terrestre : l'olivine et l'orthopyroxène. Dans un premier temps, des agrégats polycristallins à grains fins (entre 100 nm et 5 &m) d'olivine et de pyroxène ont été synthétisés par frittage flash (Spark Plasma Sintering) ainsi que par frittage sous vide. Ces échantillons ont ensuite été déformés à des pressions comprises entre 2 et 6 GPa dans des presses de typeD-DIA, installées sur des lignes de lumière des synchrotrons NSLS et ESRF afin d'avoir une mesure in situ de la contrainte différentielle et de la déformation. L'effet de la pression sur la plasticité basse température de l'olivine a été étudié à température ambiante (ligne ID06 du synchrotron ESRF, Grenoble). Les mécanismes de déformation à haute température de l'olivine et de l'orthopyroxène ont également été étudiés, pour des températures comprises entre 900 et 1200°C (ligne X17B2 du synchrotron NSLS, New York). Les données mécaniques ainsi que l'analyse des microstructures par EBSD, suggèrent une déformation par fluage diffusion. Des lois rhéologiques incluant l'effet de la pression, de la température, de la contrainte et de la taille de grain ont été déterminées pour les deux minéraux. A ces conditions, le pyroxène est moins visqueux que l'olivine. Enfin, des échantillons biphasés, avec un rapport volumique Ol/Px de 70/30 et 80/20, ont été déformés. La contrainte différentielle calculée dans chacune des deux phases suggère la contribution d'un second mécanisme de déformation en plus du fluage diffusion, en accord avec les observations microstructurales. / This thesis presents our work on the rheology of two of the main minerals of the upper mantle: olivine and orthopyroxene. First, fined-grained polycrystalline aggregates (with grain sizes between 100 nm and 5 &m) of olivine and pyroxene were synthesized by Spark Plasma Sintering (SPS) and vacuumsintering. The samples were then deformed at pressures between 2 and 6 GPa in D-DIA presses installed on synchrotrons X-ray beamlines at NSLS and ESRF so thatmeasurements of the differential stress and strain could be obtained in situ. The influence of pressure on low-temperature plasticity of olivine was studied at room temperature (ID06 beamline, ESRF synchrotron, Grenoble). High-temperature deformation mechanisms of olivine and orthopyroxene were also studied between 900 and 1200°C (X17B2 beamline, NSLS synchrotron, New York). Mechanical results and microstructural analysis by EBSD suggest a deformation by diffusion creep. Rheological laws including the effect of pressure, temperature, differential stress and grain size were determined for each mineral. Under these conditions, orthopyroxene appears less viscous than olivine. Finally, two-phase aggregates (Ol/Px volume ration of 80/20 and 70/30) were also deformed. Differential stress, estimated in each phase, indicates the contribution of a second deformation mechanism, in agreement with microstructural observations.

Parametric acoustic arrays are ultrasonic-based loudspeakers that produce highly directive audio. The audio must first be preprocessed and modulated into an ultrasonic carrier before being emitted into the air, where it will self-demodulate in the far field. The resulting audio wave is proportional to the double time-derivative of the square of the modulation envelope. This thesis presents a fully analog processor which encodes the audio into two Pulse Width Modulated (PWM) signals in quadrature phase and sums them together to produce a Single Sideband (SSB) spectrum around the fundamental frequency of the PWM signals. The two signals are modulated between 8% and 24% duty cycle to maintain a quasi-linear relationship between the duty cycle and the output signal level. This also allows the signals to sum without overlapping each other, maintaining a two-level output. The system drives a network of narrowband transducers with a center frequency equal to the PWM fundamental. Because the transducers are voltage driven, they have a bandpass frequency response which behaves as a first-order integrator on the SSB signal, eliminating the need for two integrators in the processor. Results show that the “SSB-PWM” output wave has a consistent 20-30dB difference in magnitude between the upper sideband and lower sideband. In simulation, a single tone test shows higher total harmonic distortion for lower frequencies and higher modulation depth. A two-tone test creates a 2nd order intermodulation term that increases with the frequencies of the input signals.

Master’s thesis deals with design and practical realisation of electronic circuits, which are needed for assembling of DRM signal transmitter for ham short waves bands. There is presented DRM standard as well as there are described the differencies between DRM for radio broadcast and for ham using. There is described design of input audio circuits, modulator, mixer, local generator, amplifier and filters. Principle of used SSB modulator is based on phase method, often called Tayloe modulator. This principle is analysed in detail including mathematical description, which was derived. It is possible to control the transmitter by program running at computer, communication takes place via USB. There is described establishment of communication in this work too.

In this study we present a high-performance computing architecture and hardware acceleration strategy for a heterogeneous multi-gigabit computing system. The system architecture integrates a BeeGFS distributed file system, capable of achieving 80 Gbps of sustained write throughput across five nodes, essential for managing the high data volumes generated by a 25 high performance computer (HPC) compute cluster. To ensure operational efficiency and scalability, the tasks performed on the Linux compute cluster consisting of 30 nodes are automated using Ansible, facilitating seamless deployment, management, and updates. We present compilation strategies for a hardware accelerated Polyphase Filter Bank (PFB) channelization routine optimized for Xilinx Ultrascale+ FPGAs, capable of simultaneously processing 2048 channels per 12 input streams. This setup shows the efficiency of High Level Sysnthesis of FPGA-based signal processing in handling demanding data analysis tasks. We also present the implementation and verification of a 1.6 Gsps Direct Memory Access (DMA) transfer from DDR4 memory to a modern Radio Frequency System on Chip (RFSoC) digital to analog converter. The combination of a high-throughput file system, streamlined automation, and advanced signal processing capabilities shows these system's ability to meet the needs of complex, real-time data analysis and processing applications, advancing the field of computational research.

Advances in wireless technology have recently led to the potential for higher data rates and greater functionality. Wireless home and business networks and 3G and 4G cellular phone systems are promising technologies striving for market acceptance, requiring low-cost, low-power, and compact solutions. One approach to meet these demands is system-on-a-chip (SoC) integration, where RF/analog and digital circuitry reside on the same chip, creating a mixed-signal environment. Concurrently, there is tremendous incentive to utilize Si-based technologies to leverage existing fabrication and design infrastructure and the corresponding economies of scale. While the SoC approach is attractive, it presents major challenges for circuit designers, particularly in the design of monolithic voltage controlled oscillators (VCOs). VCOs are important components in the up or downconversion of RF signals in wireless transceivers. VCOs must have very low phase noise and spurious emissions, and be extremely power efficient to meet system requirements. To meet these specifications, VCOs require high-quality factor (Q) tank circuits and reduction of noise from active devices; however, the lack of high-quality monolithic inductors, along with low noise transistors in traditional Si technologies, has been a limiting factor. This thesis presents the design, characterization, and comparison of three monolithic 3-4 GHz VCOs and an integrated 5-6 GHz VCO with tunable polyphase outputs. Each VCO is designed around a differential -G_{M} core with an LC tank circuit. The circuits exploit two Si-based device technologies: Silicon Germanium (SiGe) Heterojunction Bipolar Transistors (HBTs) for a cross-coupled collectors circuit and Graded-Channel MOS (GC-MOS) transistors for a complementary (CMOS) implementation. The circuits were fabricated using the Motorola 0.4 μm CDR1 SiGe BiCMOS process, which consists of four interconnected metal layers and a thick copper (10 μm) metal bump layer for improved inductive components. The VCO implementations are targeted to meet the stringent phase noise specifications for the GSM/EGSM 3G cellular standard. The specifications state that the VCO output cannot exceed -162 dBc/Hz sideband noise at 20 MHz offset from the carrier. Simultaneously, oscillators must be designed to address other system level effects, such as feed-through of the local oscillator (LO). LO feed-through directly results in self-mixing in direct conversion receivers, which gives rise to unwanted corrupting DC offsets. Therefore, a system-level strategy is employed to avoid such issues. For example, multiplying the oscillator frequency by two or four times can help avoid self-mixing during downconversion by moving the LO out of the bandwidth of the RF front-end. Meanwhile, direct conversion or low-IF (intermediate frequency) receiver architectures utilize in-phase and quadrature (I/Q) downconversion signal recovery and image rejection. Any imbalance between the I and Q channels can result in an increase in bit-error-rate (BER) and/or decrease in the image rejection ratio (IRR). To compensate for such an imbalance, an integrated tunable polyphase filter is implemented with a VCO. Control voltages between the differential I and Q channels can be individually controlled to help compensate for I/Q mismatches. This thesis includes an introduction to design flow and layout strategies for oscillator implementations. A detailed comparison of the advantages and disadvantages of the SiGe HBTs and GC-MOS device in 3-4 GHz VCOs is presented. In addition, an overview of full-wave electromagnetic characterization of differential dual inductors is given. The oscillators are characterized for tuning range, output power, and phase noise. Finally, new measurement techniques for the 5-6 GHz VCO with a tunable polyphase filter are explored. A comparison between the time and frequency approaches is also offered. / Master of Science

The stacked polyphase bridges (SPB) converter topology is investigated in the presentthesis as a fault-tolerant choice for permanent-magnet synchronous reluctance (PMSyn-Rel) motor control. Integrated motor drive systems are studied as they offer great benefitsfor propulsion applications. Moreover, the importance of a modular topology, like theSPB, for an electric powertrain is discussed. The latter consists of a number of seriesconnected, 3-phase 2-level inverter submodules that supply separate sets of windings ina multi-star motor. The specifications of building a four-board SPB setup are examined,while the challenges of an active voltage balancing controller are analyzed. The designprocess is explained step-by-step and the final printed circuit boards (PCBs) are presented.Furthermore, the significance of low electromagnetic interference design for a converterthat requires high speed communication is highlighted. Finally, the prototype is testedthoroughly and the expected fault-tolerant capabilities are validated on a PMSynRel motor. / I detta examensarbete unders¨ok SPB-omriktartopologin (stacked polyphase bridges converter)i termer av ett feltolerant elektriskt drivsystem f¨or en permamentmagnetassisteradsynkron reluktansmaskin (PMSynRel). SPB-omriktaren best°ar av ett antal seriekoppladetrefasomriktare av tv°aniv°atyp som, var och en, f¨orser effekt till en trefaslindningtillh¨orande en modul¨ar elmaskin av multifastyp. Specifikation, design och konstruktion aven SPB-omriktare med fyra seriekopplade moduler studeras. Designproceduren presenterasi en steg-f¨or-steg-process och de tillverkade kretskorten presenteras utf¨orligt. Kommunikationenmellan de olika kretskorten unders¨oks med s¨arskild tonvikt p°a l°ag elektromagnetiskinterferens vilket ¨ar n¨odv¨andigt om h¨og kommunikationshastighet skall kunnauppn°as. Den f¨ardigst¨allda prototypen har utv¨arderats experimentellt och kapaciteten f¨orfeltolerans har demonstrerats vid drift av en PMSynRel-maskin utrustad med en multifaslindning.

No description available.

No description available.

Fixed Broadband Wireless Access (FBWA) is a technology aimed at providing high-speed wireless Internet access, over a wide area, from devices such as personal computers and laptops. FBWA channels are defined in the range of 1-20 MHz which makes the RF front end (RFE) design extremely challenging. In its pursuit to standardize the Broadband Wireless Access (BWA) technologies, IEEE working group 802.16 for Broadband Wireless Access has released the fixed BWA standard IEEE 802.16 – 2004 in 2004. This standard is further backed by a consortium, of leading wireless vendors, chip manufacturers and service providers, officially known as Wireless Interoperability for Microwave Access (WiMAX). In general, any wireless base station (BS), supporting a number of contiguous Frequency Division Multiplexed (FDM) channels has to incorporate an RF front end (RFE) for each RF channel. The precise job of the RFE is to filter the desired channel from a group of RF channels, digitize it and present it to the subsequent baseband system at the proper sampling rate. The system essentially has a bandpass filter (BPF) tuned to the channel of interest followed by a multiplier which brings the channel to a suitable intermediate frequency (IF). The IF output is digitized by an ADC and then brought to the baseband by an appropriate digital multiplier. The baseband samples, thus generated, are at the ADC sampling rate which is significantly higher than the target sampling rate, which is defined by the wireless protocol in use. As a result a sampling rate conversion (SRC) is performed on these baseband samples to bring the channel back to the target sampling rate. Since the input sampling rate need not be an integer multiple of the target sampling rate, Fractional SRC (FSRC) is required in most of the cases. Instead of using a separate ADC and IF section for each individual channels, most systems use a common IF section, followed by a wideband ADC, which operates over a wide frequency band containing a group of contiguous FDM channels. In this case a channelizer is employed to digitally extract the individual channels from the digital IF samples. We formally call this system a receiver channelizer. Such an implementation presents considerable challenge in terms of the computational requirement and of course the cost of the BS. The computational complexity further goes up for FBWA system where channel bandwidth is in the order of several MHz. Though such a system has been analyzed for narrow band wireless systems like GSM, to the best of our knowledge no analysis seems to have been carried out for a wideband system such as WiMAX. In this work, we focus on design of a receiver channelizer for WiMAX BS, which can simultaneously extract a group of contiguous FDM RF channels supported by the BS. The main goal is to obtain a simple, low cost channelizer architecture, which can be implemented in an FPGA. There are a number of techniques available in the literature, from Direct Digital Conversion to Polyphase FFT Filter Banks (PFFB), which can do the job of channelization. But each of them operates with certain constraints and, as a result, suits best to a particular application. Further all of these techniques are generic in nature, in the sense that their structure is independent of any particular standard. With regard to computational requirement of these techniques, PFFB is the best, with respect to the number of complex multiplications required for its implementation. But it needs two very stringent conditions to be satisfied, viz. the number of channels to be extracted is equal to the decimation factor and the sampling rate is a power of 2 times baseband bandwidth. Clearly these conditions may not be satisfied by different wireless communication standards, and in fact, this is not satisfied by the WiMAX standard. This gives us the motivation to analyze the receiver channelizer for WiMAX BS and to find an efficient and low cost architecture of the same. We demonstrate that even though the conditions required by PFFB are not satisfied by the WiMAX standard, we can modify the overall architecture to include the PFFB structure. This is achieved by dividing the receiver channelizer into two blocks. The first block uses the PFFB structure to separate the desired number of channels from the input samples. This process also achieves an integer SRC by a factor that is equal to the number of channels being extracted. This block generates baseband outputs whose sampling rates are related to their target sampling rate by a fractional multiplication factor. In order to bring the channels to their target sampling rate, each output from the PFFB block is fed to a FSRC block, whose job is to use an efficient FSRC algorithm to generate the samples at the target sampling rate. We show that the computational complexity, as compared to the direct implementation, is reduced by a factor, which is approximately equal to the square of the number of channels. After mathematically formulating the receiver channelizer for WiMAX BS, we perform the simulation of the system using a software tool. There are two basic motives behind the simulation of the system which has a mathematical model. Firstly, the software simulation will give an idea whether the designed system is physically realizable. Secondly, this will help in designing the logic for different blocks of the system. Once these individual blocks are simulated and tested, they can be smoothly ported onto an FPGA. For simulation purpose, we parameterize the receiver channelizer in such a way that it can be reconfigured for different ADC sampling rates and IF frequencies, by changing the input clock rate. The system is also reconfigurable in terms of the supported channel bandwidth. This is achieved by storing all the filter coefficients pertaining to each channel type, and loading the required coefficients into the computational engine. Using this methodology we simulate the system for three different IF frequencies (and the corresponding ADC sampling rates) and three different channel types, thus leading to nine different system configurations. The simulation results are in agreement with the mathematical model of the system. Further, we also discuss some important implementation issues for the reconfigurable receiver channelizer. We estimate the memory requirement for implementing the system in an FPGA. The implementation delay is estimated in terms of number of samples. The thesis is organized in five chapters. Chapter 1 gives a brief introduction about the WiMAX system and different existing channelization architecture followed by the outline of the proposed receiver channelizer. In chapter 2, we analyze the proposed receiver channelizer for WiMAX BS and evaluate its computational requirements. Chapter 3 outlines the procedure to generate the WiMAX test signal and specification of the all the filters used in the system. It also lists the simulation parameters and records the results of the simulation. Chapter 4 presents the details of a possible FPGA implementation. We present the concluding remarks and future research directions in the final chapter.

Le travail présenté ici s'inscrit dans la perspective du développement de modules électroniques à très faible coût et à très faible consommation pour les réseaux de capteurs sans fils (WSN). Il traite de la conception et du test d'une chaîne de réception RF compatible avec la norme IEEE 802.15.4 pour la bande ISM 2.4GHz. L'interface RF objet de notre étude inclue toutes les fonctions depuis l'antenne jusqu'au 1er étage du filtre analogique en bande de base, à partir duquel le gain devient suffisant pour masquer le bruit introduit par le reste de la chaîne de réception. Ce mémoire articulé autour de quatre chapitres, décrit toutes les étapes depuis la définition des spécifications de la chaîne de réception jusqu'à la présentation de ses performances, en passant par l'étude de son architecture et la conception de ses différents étages. Suite à l'étude de l'impact des interféreurs IEEE 802.15.4 et IEEE 802.11b présents dans la bande ISM 2.4GHz, une architecture utilisant une fréquence intermédiaire de 6MHz a été retenue. En outre, pour pouvoir répondre aux spécifications fixées, cette architecture est composée de plusieurs étages innovants ou originaux tels qu'un balun intégré trois accès, un amplificateur faible bruit sans inductance, un mélangeur passif piloté par un signal local (OL) à très faible rapport cyclique ainsi qu'un filtre bande de base optimisé en bruit et en linéarité. Intégré dans une technologie CMOS 90nm, ce récepteur occupe une surface de 0.07mm², ou 0.23mm² en incluant le balun intégré, qui représente une réduction de 70% par rapport à l'état de l'art des puces compatibles avec le standard IEEE 802.15.4. En prenant en compte la consommation dynamique de toute la chaîne de mise en forme du signal OL, la tête de réception précédemment décrite consomme seulement 4mA sous une tension d'alimentation de 1.35V. Enfin, en incluant le balun intégré, le gain est de 35dBv/dBm, le facteur de bruit de 7.5dB, l'IIP3 de -10dBm et la réjection d'image supérie ure à 32dB. Ces performances placent ce récepteur parmi les récepteurs RF les plus performants pour cette application. Les nombreux principes mis en Suvre sont par ailleurs transposables à d'autres bandes de fréquences et à d'autres standards de communication.