In this thesis different aspects of general low power design and LNA-design have been studied. A new architecture for an ultra low power LNA is proposed and simple simulation results are presented. Simulations show that there should be possible to design a 2.4 GHz LNA that works sufficiently at 200 µA. The proposed architecture achieved a voltage gain over 20 dB from 2.32 to 2.5 GHz, a noise figure of 4.65 dB, IIP3 of -15.45 dBm and a input match of -9.5 dB. There is still a lot of work do and many simulations to perform before one can inconclusively conclude that the proposed architecture is a feasible solution, although the results generated in this thesis seem promising.

<p>Direct Digital Frequency Synthesi<em>s </em>(DDFS) is a method of producing an analog waveform by</p><p>generating a time-varying signal in digital form, succeeded by digital-to-analog reconstruction.</p><p>At behavioral level the bit products with specified weights are used to generate the sine wave. In representation of a sine wave both positive and negative weights are generated. Since negative weights are not desired in design, the negative weights are transformed to positive weights. To reduce the number of current sources and control signals, bit product signals of those current sources which cannot be switched on simultaneously and have equal weights are shared. After sharing weights, the control signals are reduced to from 59 to 43 and current sources from 207 to 145.</p><p>Different control words are used by the DDFS system in order to generate different frequencies. The control word is successively added to the previous value in a 20-bit accumulator. Nine most significant bits out of these twenty bits are used for the DAC.</p><p>Since the Current Steering DAC architecture is suitable for high speed and high resolution purposes, so a 9-bit nonlinear current steering DAC is used to convert the output of bit products to the analog sine wave. Seven bits are used to generate one quarter of the sine wave. Eighth and ninth bits are used to generate the full sine wave.</p><p>HCMOS 9 (130 nm) ST Microelectronics process is used by employing high speed NMOS and PMOS transistors. The bit products (control signals) are computed by using complementary static CMOS logic which then act as control signals for the current sources after passing through D-flip flops. Practical design issues of current sources and parts of digital logic were studied and implemented using the Cadence full-custom design environment.</p>

<p>As the rapid development of the wireless communication system and mobile video devices, the integrated chip with low power consuming and high conversion efficiency is widely needed. ADC and DAC are playing an important role in these applications.</p><p>The aim of this thesis is to verify a post-correction method which is used for improving the performance of ADC. First of all, this report introduces the development and present status of ADC, and expatiate its important parameters from two different classes (static performance and dynamic performance). Based on the fundamental principle, the report then focuses on the dynamic integral non-linearity modeling of ADC. Refer to this model, one post-correction method is described and verified.</p><p>Upon the face of post-correction, this method is to modify the output signals which have been converted from analog to digital format by adding a correction term. Improvement made by the post-correction needs to be checked out. Thus the performance analysis mainly relay on the measures of total harmonic distortion and signal to noise and distortion ratio is also included in this thesis.</p>

This thesis presents a novel algorithmic A/D converter to be used in a biosensor. The converter is capable of a conversion rate of 1.5 bits/phase and hence the required conversion time is reduced. The proposed architecture is analyzed for non-ideal effects and compared with existing algorithmic A/D architectures. The converter needs only one op-amp, 4 comparators and 3 capacitors. Power reduction techniques are discussed with respect to the biosensor and the ADC. The ADC is designed for fabrication in a CMOS 0.18μm process. / Graduation date: 2004

Pipelined analog to digital converters (ADCs) are very important building blocks in many electronic systems such as high quality video systems, high performance digital communication systems and high speed data acquisition systems. The rapid development of these applications is driving the design of pipeline ADCs towards higher speed, higher dynamic range, lower power consumption and lower power supply voltage with the CMOS technology scaling. This trend poses great challenges to conventional pipelined ADC designs which rely on high-gain operational amplifiers (opamps) and well matched capacitors to achieve high accuracy. In this thesis, two novel accuracy improvement techniques to overcome the accuracy limit set by analog building blocks (opamps and capacitors) in the context of low-voltage and high-speed pipelined ADC design are presented. One is the time-shifted correlated double sampling (CDS) technique which addresses the finite opamp gain effect and the other is the radix-based background digital calibration technique which can take care of both finite opamp gain and capacitor mismatch. These methods are simple, easy to implement and power efficient. The effectiveness of the proposed techniques is demonstrated in simulation as well as in experiment. Two prototype ADCs have been designed and fabricated in 0.18μm CMOS technology as the experimental verification of the proposed techniques. The first ADC is a 1.8V 10-bit pipeline ADC which incorporated the time-shifted CDS technique to boost the effective gain of the amplifiers. Much better gain-bandwidth tradeoff in amplifier design is achieved with this gain boosting. Measurement results show total power consumption of 67mW at 1.8V when operating at 100MSPS. The SNR, SNDR and SFDR are 55dB, 54dB and 65dB respectively given a 1MHz input signal. The second one is a 0.9V 12-bit two-stage cyclic ADC which employed a novel correlation-based background calibration to enhance the linearity. The linearity limit set by the capacitor mismatches, finite opamp gain effects is exceeded. After calibration, the SFDR is improved by about 33dB and exceeds 80dB. The power consumption is 12mW from 0.9V supply when operating at 2MSPS. / Graduation date: 2004

A differential current-mode track-and-hold (T/H) amplifier is used to sample an analog input signal. A new closed-loop current-mode architecture has been developed that overcomes the stability problems associated with closed-loop architectures. The T/H circuit has been fabricated in a 0.35-��m quad-metal, double-poly CMOS process. The measured total harmonic distortion (THD) is -81dB and -65dB with an input signal frequency of 100KHz and 10MHz, respectively. This is the best performance reported to date for a CMOS implementation. / Graduation date: 2003

This thesis describes compensation techniques for cascaded delta-sigma A/D converters (ADCs) and high-performance switched-capacitor (SC) circuits. Various correlated-double-sampling (CDS) techniques are presented to reduce the effects of the nonidealities, such as clock feedthrough, charge injection, opamp input-referred noise and offset, and finite opamp gain, in SC circuits. A CDS technique for the compensation of opamp input-referred offset and clock-feedthrough effect is examined and improved to achieve continuous operation. Experimental results show that after the compensation, the SC integrator's output signal swing is greatly increased. The effects of the analog circuitry nonidealities in delta-sigma ADCs are also analyzed. The analysis shows that the nonidealities in cascaded delta-sigma ADCs cause noise leakage, which limits the overall performance of the cascaded modulators. In order to reduce the noise leakage, a novel adaptive compensation technique is proposed. To verify the effectiveness of the proposed compensation techniques, a prototype 2-0 cascaded modulator was designed. Its first stage, a second-order delta-sigma modulator with test signal input circuit, was designed and fabricated in 1.2 ��m CMOS technology. The measurement results show that the noise leakage is reduced effectively by the compensation, and the performance of the cascaded delta-sigma modulator is greatly improved. / Graduation date: 1999

The advance of digital IC technology has been very fast, as shown by rapid development of DSP, digital communication and digital VLSI. Within electronic signal processing, analog-to-digital conversion is a key function, which converts the analog signal into digital form for further processing. Recently, low-voltage and low-power have become also an important factors in IC development. This thesis investigates some novel techniques for the design of low-power high-performance A/D converters in CMOS technology, and the non-ideal switched-capacitor effects of (SC) circuits. A new successive-approximation A/D converter is proposed with a novel error cancellation scheme. This A/D converter needs only a simple opamp, a comparator, and a few switches and capacitors. It can achieve high resolution with relative low power consumption. A new ratio-independent cyclic A/D converter is also proposed with techniques to compensate for the non-ideal effects. The implementation include a new differential sampling that is used to achieve ratio-independent multiple-by-two operation. Extensive simulations were performed to demonstrate the excellent performance of these data converters. / Graduation date: 1999

Multi-level decision feedback equalization (MDFE) is a sampled signal processing technique for data recovery from magnetic recording channels which use the 2/3(1,7) run length limited code. The key adaptive feedback loops in MDFE are those which perform the timing recovery, gain recovery, dc offset detection, and adaptive equalization of the feedback equalizer. The algorithms used by these adaptive loops are derived from the channel error which is the deviation of the equalized signal from its ideal value. It is advantageous to convert this error signal to a digital value using a flash analog-to-digital converter (flash ADC) to simplify the implementation of the adaptive loops. In this thesis, a scheme to place the thresholds of the flash ADC is presented. The threshold placement has been optimized based on the steady-state probability density function (pdf) of the signal to be quantized. The resolution constraints imposed by this quantization scheme on the adaptive loops has been characterized. As the steady-state assumption for the signal to be quantized is not valid during the transient state of the adaptive loops, the loop transients with this quantization scheme have been analyzed through simulations. The conditions under which the channel can recover from a set of start-up errors and converge successfully into steady-state have been specified. The steady-state channel performance with the noise introduced by the iterative nature of the adaptive loops along with this quantization scheme has also been verified. / Graduation date: 1997

Delta-sigma modulators are currently a very popular technique for making high-resolution analog-to-digital and digital-to-analog converters. These oversampled data converters have several advantages over conventional Nyquist-rate converters, including an insensitivity to many analog component imperfections, a simpler antialiasing filter and reduced accuracy requirements in the sample and hold. Though the initial uses of delta-sigma modulators were in the audio field, the development of bandpass modulators opened up the application range to radar systems, digital communication systems and instruments which convert IF, or even RF, analog signals directly to digital form. This thesis presents a method used to analyze and synthesize continuous-time delta-sigma modulators for given specifications. A fourth-order prototype continuous-time bandpass delta-sigma modulator employing g[subscript m]-LC resonator structure is demonstrated on a PCB board and measurement results corroborate the theory. To allow the construction of very high performance delta-sigma modulators, this thesis presents an architecture for a multibit DAC constructed from unit elements which shapes element mismatches. Theoretical analysis and simulation shows that this architecture greatly increases the noise attenuation in the band-of-interest and facilitates the use of multibit quantization in delta-sigma modulators. The methods presented in this thesis will allow high-frequency wideband bandpass delta-sigma modulators to be constructed. / Graduation date: 1996