<p> In this thesis, a high-speed inverse Walsh transform apparatus was designed and built which sums over the sixteen most dominant coefficients in the time base period. The transform includes a maximum of 64 terms. The Walsh function generator used works with a clock rate up to 10 MHz to produce 64 different sequency terms with accurate timing and hazard free operation. A synchronizing pulse is produced by the circuit to determine the beginning of the Walsh transform period. The final adder stage limits the speed of the apparatus to a 1 MHz square wave. An application of the instrument was made to reconstruct one line of an actual video signal.</p> / Thesis / Master of Engineering (MEngr)

<p>Bit-serial multiplication with a fixed coefficient is commonly used in integrated circuits, such as digital filters and FFTs. These multiplications can be implemented using basic components such as adders, subtractors and D flip-flops. Multiplication with the same coefficient can be implemented in many ways, using different structures. Other studies in this area have focused on how to minimize the number of adders/subtractors, and often assumed that the cost for D flip-flops is neglectable. That simplification has been proved to be far too great, and further not at all necessary. In digital devices low power consumption is always desirable. How to attain this in bit-serial multipliers is a complex problem. </p><p>The aim of this thesis was to find a strategy on how to implement bit-serial multipliers with as low cost as possible. An important step was achieved by deriving formulas that can be used to calculate the carry switch probability in the adders/subtractors. It has also been established that it is possible to design a power model that can be applied to all possible structures of bit- serial multipliers.</p>

<p>Fast addition is essential in many DSP algorithms. Various structures have been introduced to speed up the time critical carry propagation. For high throughput applications, however, it may be necessary to introduce pipelining. In this report the power consumption of four different adder structures, with varying word length and different number of pipeline cuts, is compared. </p><p>Out of the four adder structures compared, the Kogge-Stone parallel prefix adder proves to be the best choice most of the time. The Brent-Kung parallel prefix adder is also a good choice, but the maximal throughput does not reach as high as the maximal throughput of the Kogge-Stone parallel prefix adder.</p>

<p>A fast and energy-efficient multiplier is always needed in electronics industry especially DSP, image processing and arithmetic units in microprocessors. Multiplier is such an important element which contributes substantially to the total power consumption of the system. On VLSI level, the area also becomes quite important as more area means more system cost. Speed is another key parameter while designing a multiplier for a specific application.</p><p>These three parameters i.e. power, area and speed are always traded off. Speaking of DSP processors, area and speed of MAC unit are the most important factors. But sometimes, increasing speed also increases the power consumption, so there is an upper bound of speed for a given power criteria. Considering the battery operated portable multimedia devices, low power and fast designs of multipliers are more important than area.</p><p>The design of a low power, high speed and area efficient multiplier is thus the goal of my thesis work. The projected plan is to instantiate a good design and modify it for low power and speed and prepare its layout using 90nm technology in Cadence®. For that purpose study has been performed on a number of research papers presented in section 7 and selected one of the architecture presented by Jung-Yup Kang and Jean-Luc Gaudiot. They presented a unique technique for power reduction in Wallace tree multipliers. They have proposed a method to calculate 2’s complement of multiplicand for final Partial Product Row (PPR) if using MBE technique. This method has been used in the design for speed enhancement and power reduction.</p><p>The ultimate purpose is to come up with such an architecture which is energy and area efficient than a conventional multiplier at the same performance level. This report describes the design and evaluation of new energy-efficient 32-bit multiplier architecture by comparing its power, performance and chip area to those of a conventional 32-bit multiplier. The report throws light on the basic principles and methods of binary multiplication process and also the power consumption issues related to multipliers. The new algorithm, which reduces the last negative signal in the partial product row is discussed to develop the new architecture. A power performance comparison is shown. The simulation results show that the new architecture is 46 % energy-efficient than a conventional multiplier at the same performance level. The number of transistors used is 34% less and also it consumes 25% less chip area in 90nm CMOS technology.</p>

Bit-serial multiplication with a fixed coefficient is commonly used in integrated circuits, such as digital filters and FFTs. These multiplications can be implemented using basic components such as adders, subtractors and D flip-flops. Multiplication with the same coefficient can be implemented in many ways, using different structures. Other studies in this area have focused on how to minimize the number of adders/subtractors, and often assumed that the cost for D flip-flops is neglectable. That simplification has been proved to be far too great, and further not at all necessary. In digital devices low power consumption is always desirable. How to attain this in bit-serial multipliers is a complex problem. The aim of this thesis was to find a strategy on how to implement bit-serial multipliers with as low cost as possible. An important step was achieved by deriving formulas that can be used to calculate the carry switch probability in the adders/subtractors. It has also been established that it is possible to design a power model that can be applied to all possible structures of bit- serial multipliers.

Fast addition is essential in many DSP algorithms. Various structures have been introduced to speed up the time critical carry propagation. For high throughput applications, however, it may be necessary to introduce pipelining. In this report the power consumption of four different adder structures, with varying word length and different number of pipeline cuts, is compared. Out of the four adder structures compared, the Kogge-Stone parallel prefix adder proves to be the best choice most of the time. The Brent-Kung parallel prefix adder is also a good choice, but the maximal throughput does not reach as high as the maximal throughput of the Kogge-Stone parallel prefix adder.

A fast and energy-efficient multiplier is always needed in electronics industry especially DSP, image processing and arithmetic units in microprocessors. Multiplier is such an important element which contributes substantially to the total power consumption of the system. On VLSI level, the area also becomes quite important as more area means more system cost. Speed is another key parameter while designing a multiplier for a specific application. These three parameters i.e. power, area and speed are always traded off. Speaking of DSP processors, area and speed of MAC unit are the most important factors. But sometimes, increasing speed also increases the power consumption, so there is an upper bound of speed for a given power criteria. Considering the battery operated portable multimedia devices, low power and fast designs of multipliers are more important than area. The design of a low power, high speed and area efficient multiplier is thus the goal of my thesis work. The projected plan is to instantiate a good design and modify it for low power and speed and prepare its layout using 90nm technology in Cadence®. For that purpose study has been performed on a number of research papers presented in section 7 and selected one of the architecture presented by Jung-Yup Kang and Jean-Luc Gaudiot. They presented a unique technique for power reduction in Wallace tree multipliers. They have proposed a method to calculate 2’s complement of multiplicand for final Partial Product Row (PPR) if using MBE technique. This method has been used in the design for speed enhancement and power reduction. The ultimate purpose is to come up with such an architecture which is energy and area efficient than a conventional multiplier at the same performance level. This report describes the design and evaluation of new energy-efficient 32-bit multiplier architecture by comparing its power, performance and chip area to those of a conventional 32-bit multiplier. The report throws light on the basic principles and methods of binary multiplication process and also the power consumption issues related to multipliers. The new algorithm, which reduces the last negative signal in the partial product row is discussed to develop the new architecture. A power performance comparison is shown. The simulation results show that the new architecture is 46 % energy-efficient than a conventional multiplier at the same performance level. The number of transistors used is 34% less and also it consumes 25% less chip area in 90nm CMOS technology.

Most general purpose processors (GPP) and application specific processors (ASP) use the floating-point arithmetic due to its wide and precise number system. However, the floating-point operations require complex processes such as alignment, normalization and rounding. To reduce the overhead, fused floating-point arithmetic units are introduced. In this dissertation, improved architectures for three fused floating-point arithmetic units are proposed: 1) Fused floating-point add-subtract unit, 2) Fused floating-point two-term dot product unit, and 3) Fused floating-point three-term adder. Also, the three fused floating-point units are implemented for both single and double precision and evaluated in terms of the area, power consumption, latency and throughput. To improve the performance of the fused floating-point add-subtract unit, a new alignment scheme, fast rounding, two dual-path algorithms and pipelining are applied. The improved fused floating-point two-term dot product unit applies several optimizations: a new alignment scheme, early normalization and fast rounding, four-input leading zero anticipation (LZA), dual-path algorithm and pipelining. The proposed fused floating-point three-term adder applies a new exponent compare and significand alignment scheme, double reduction, early normalization and fast rounding, three-input LZA and pipelining to improve the performance. / text

Climate change is one of the most challenging crises in sustainable development agenda. Tackling the problem requires the global transition towards renewable and sustainable energies. The uptake of these new technologies is often supported by policies and technological know-how that is developed by early adopters, and later spread and transferred to other places. Although renewable technology transfer and diffusion have long been studied, the question of how supporting policies flow from one country to another, and how they are adapted to the local contexts are merely investigated. This paper sheds some light on the process, mechanisms, and dynamics of policy transfer, and investigate the influences of national contextual characters on the adoption of policy from other countries, using Thailand's feed-in tariff policy as an example. The study applies an adapted version of ‘Dolowitz and Marsh model (1996, 2000, 2012)’ as the guiding policy transfer framework to analyse the information gathered through literature study and fieldwork, and to present the results and findings. The study discovers that policy transfer is not a straightforward process with a clear transfer timeline and boundary, but rather a dynamic and complex process that involves interactions with many factors, internal and external, and are continuously shaping the process and outcomes of the transfer. Moreover, the case study proves that Dolowitz and Marsh model is a useful and effective framework to understand and depict the process. However, if to treat policy transfer as an independent variable affecting the process outcomes, it would need to combine other frameworks, for instance, Marsh and McConnell Model (2010), to give an in-depth and comprehensive analysis to measure the success of policy transfer and policymaking. / Förnybar energi är en av de viktigaste lösningarna för att ta itu med klimatförändringarna. Utnyttjandet av denna nya teknik stöds alltid av politik, som vanligtvis utvecklas av ett land och överförs till andra länder. Denna avhandling använder ramen för policyöverföring för att analysera hur feed-in tariffpolitik från Europa spred sig och överförs till Thailand. Fallet belyser processen, mekanismerna och dynamiken för att illustrera hur politik som utvecklats av ett land inspirerade andra länder med deras beslutsfattande.

Το Σύστημα Αριθμητικής Υπολοίπου (Residue Number System - RNS), είναι ένα σύστημα αριθμητικής το οποίο παρουσιάζει σημαντικά πλεονεκτήματα στην ταχύτητα με την οποία μπορούν να γίνουν οι αριθμητικές πράξεις. Στα RNS οι αριθμοί αναπαρίστανται σαν ένα σύνολο από υπόλοιπα. Οι εφαρμογές του RNS εκτείνονται σε ένα ευρύ φάσμα της επιστήμης και της τεχνολογίας οπότε έχει δοθεί μεγάλο βάρος στην ανάπτυξη αριθμητικών συστημάτων υψηλής απόδοσης. Τέτοιες αριθμητικές μονάδες είναι αθροιστές, πολλαπλασιαστές, κυκλώματα υπολογισμού ρίζας και γεννήτριες υπολοίπου (Residue Generator – RG). Τα RNS συστήματα πολύ συχνά χρησιμοποιούν βάσεις με τρία διαφορετικά moduli της μορφής {2^n-1,2^n,2^n+1}. Αυτό οφείλεται στο γεγονός ότι έχουν κατασκευαστεί πολύ αποδοτικά συνδυαστικά κυκλώματα κωδικοποίησης και αποκωδικοποίησης από και προς το δυαδικό σύστημα. Επομένως, ο σχεδιασμός πολύ αποδοτικών αριθμητικών συστημάτων modulo 2^n-1, modulo 2^n, modulo 2^n+1 είναι ζωτικής σημασίας για τις εφαρμογές που χρησιμοποιούν το RNS. Από αυτές τις βάσεις αυτή που απαιτεί τα πιο απαιτητικά κυκλώματα είναι αυτή που έχει σαν moduli το 2^n+1 μια που μόνο αυτή δίνει αριθμούς με n+1 bits. Στη modulo 2^n+1 αριθμητική οι αριθμοί εμφανίζονται συνήθως σε δύο αναπαραστάσεις. Στην αναπαράσταση με βάρη και στη diminished-1 αναπαράσταση. Οι δύο αυτές αναπαραστάσεις έχουν κάποια χαρακτηριστικά που τις διαφοροποιούν και που τις κάνουν κατάλληλες για διαφορετικές εφαρμογές. Στην διπλωματική αυτή θα παρουσιάσουμε μια τεχνική η οποία συνδυάζει τα πλεονεκτήματα των δύο αναπαραστάσεων προσφέροντας έτσι κυκλώματα με μικρότερη επιφάνεια που συνήθως όμως έχουν καλύτερη απόδοση. Αυτή η τεχνική θα εφαρμοστεί σε modulo 2^n+1 αθροιστές πολλαπλών εντέλων (Multi-Operand Modulo Adder – MOMA), σε modulo 2^n+1 αθροιστές και σε RG ενώ θα γίνει μελέτη της απόδοσης τους σε σχέση με τις πιο διαδεδομένες μέχρι τώρα αντίστοιχες αρχιτεκτονικές. / The Residue Number Systen (RNS) is an arithmetic system with many advantages in the speed of arithmetic components. In RNS the numbers are represented as a set of residues. The RNS applications are various so there is a great effort in developing arithmetic components with very high performance. Those arithmetic components are adders, multipliers, residue generators etc. In RNS there are commonly used bases of the form {2^n-1, 2^n, 2^n+1} that is because there has been developed very efficient encoding and decoding from and to the binary system. So the design of very efficient arithmetic components in modulo 2^n-1, modulo 2^n, modulo 2^n+1 is very crucial for RNS applications. From these three modulis the 2^n+1 is the most critical to implement because it is the only one that needs n+1-bits. In modulo 2^n+1 arithmetic the numbers are represented in two forms. In the weighted representation and in the diminished-1 representation. These two representations have some differences that make them suitable for different applications. On this thesis work we introduce a technique that combines the advantages of the two representations. This technique when applied in arithmetic components produces circuits that are smaller and very often faster. We use this techniques to design multi operand modulo 2^n+1 adders (MOMA), fast modulo 2^n+1 adders and residue generators (RG).