Referências de tensão integradas sempre foram um bloco fundamental de qualquer sistema eletrônico e um importante tópico de pesquisa que tem sido estudado extensivamente nos últimos 50 anos. Uma tensão de referência é um circuito que provê uma tensão estável com baixa sensibilidade a variações em temperatura, alimentação, carga, características do processo de fabricação e tensões mecânicas de encapsulamento. Elas são normalmente implementadas através da soma ponderada de dois fenômenos físicos diferentes, com comportamentos em temperatura opostos. Normalmente, a tensão térmica, relacionada à constante de Boltzmann e à carga do elétron, fornece uma dependência positiva com temperatura, enquanto que a tensão base-emissor VBE de um transistor bipolar ou a tensão de limiar de um MOSFET fornece o termo complementar. Um bloco auxiliar é às vezes utilizado para fornecer as correntes de polarização do circuito, e outros blocos adicionais implementam a soma ponderada. A evolução da tecnologia de processos é o principal fator para aplicações em baixa tensão, enquanto que a emergência de dispositivos portáteis operados a bateria, circuitos biomédicos implantáveis e dispostivos de captura de energia do ambiente restringem cada circuito a consumir o mínimo possivel. Portanto, alimentações abaixo de 1 V e consumos na ordem de nanoWatts se tornaram características fundamentais de tais circuitos. Contudo, existem diversos desafios ao projetar referências de tensão de alta exatidão em processos CMOS modernos sob essas condições. As topologias tradicionais não são adequadas pois elas provêm uma referência de tensão acima de 1 V, e requerem resistências da ordem de G para atingir tão baixo consumo de potência, ocupando assim uma grande área de silício. Avanços recentes atingiram tais níveis de consumo de potência, porém com limitada exatidão, custosos procedimentos de calibração e grande área ocupada em silício. Nesta dissertação apresentam-se duas novas topologias de circuitos: uma tensão de junção bipolar com compensação de curvatura que não utiliza resistores e é auto-polarizada; e um circuito de referência bandgap sem resistores que opera abaixo de 1 V (também chamado de sub-bandgap). Ambos circuitos operam com consumo na ordem de nanoWatts e ocupam pequenas áreas de silício. Resultados de simulação para dois processos diferentes, 180 nm e 130 nm, e resultados experimentais de uma rodada de fabricação em 130 nm apresentam melhorias sobre tais limitações, mantendo as características desejadas de não conter resistores, ultra baixo consumo, baixa tensão de alimentação e áreas muito pequenas. / Integrated voltage references have always been a fundamental block of any electronic system, and an important research topic that has been extensively studied in the past 50 years. A voltage reference is a circuit that provides a stable voltage with low sensitivity to variations in temperature, supply, load, process characteristics and packaging stresses. They are usually implemented through the weighted sum of two independent physical phenomena with opposite temperature dependencies. Usually the thermal voltage, related to the Boltzmann’s constant and the electron charge, provides a positive temperature dependence, while the silicon bandgap voltage or a MOSFET’s threshold voltage provide the complementary term. An auxiliary biasing block is sometimes necessary to provide the necessary currents for the circuit to work, and additional blocks implement the weighted sum. The scaling of process technologies is the main driving factor for low voltage operation, while the emergence of portable battery-operated, implantable biomedical and energy harvesting devices mandate that every circuit consume as little power as possible. Therefore, sub-1 V supplies and nanoWatt power have become key characteristics for these kind of circuits, but there are several challenges when designing high accuracy voltage references in modern CMOS technologies under these conditions. The traditional topologies are not suitable because they provide a reference voltage above 1 V, and to achieve such power consumption levels would require G resistances, that occupy a huge silicon area. Recent advances have achieved these levels of power consumption but with limited accuracy, expensive calibration procedures and large silicon area.

Light from the sun is an attractive source of energy for its renewability, supply, scalability, and cost. Silicon solar cells are the dominant technology of choice for harnessing solar energy in the form of electricity, but the designs are approaching their practical efficiency limits. New multijunction designs which use the tunable properties of the more expensive III-V semiconductors have historically been relegated to space applications where absolute power conversion efficiency, resilience to radiation, and weight are more important considerations than cost. Some of the more recent developments in the field of semiconductor materials are the so-called III-nitride materials which mainly use either indium, aluminum or gallium in combination with nitrogen. Indium gallium nitride (InGaN) is one of these III-nitride semiconductor alloys that can be tailored to span the vast majority of the solar spectrum. While InGaN growth traditionally requires expensive substrate materials such as sapphire, three-dimensional nanowire growth modes enable high quality lattice mismatched growth of InGaN directly on silicon without a metamorphic buffer layer. The absorption and electronic properties of InGaN can also be tuned by incorporating it into quantum confined regions in a GaN host material. This opens up a route towards cost-effective, high efficiency devices such as light emitted diodes and solar cells which can operate over a large range of wavelengths. The combination of the two material systems of InGaN/GaN and silicon can marry the low cost of silicon wafers with the desirable optoelectronic properties of III-nitride semiconductors. This thesis investigates the potential for highly nanostructured InGaN/GaN based devices using quantum-dot-in-nanowire designs as novel solar cells which can enable intermediate band absorption effects and multiple junctions within a single nanowire to absorb more of the solar spectrum and operating more efficiently. Such semiconductor nanostructures can in principle reach power conversion efficiencies of over 40\% on silicon, with a cost closer to conventional silicon solar cells as opposed to methods which use non-silicon substrates. In the primary strategy, the nanowires contain InGaN quantum dots which act as photon absorption/carrier generation centres to sequentially excite photons within the large band gap semiconductor. By using this intermediate band of states, large operating voltages between contacts can be maintained without sacrificing the collection of long wavelength solar photons. In this work, we characterize the properties of such nanowires and experimentally demonstrate sub-bandgap current generation in a large area InGaN/GaN dot-in-nanowire solar cell. Experimental characterization of InGaN / GaN quantum dots in nanowires as both LEDs and solar cells is performed to determine the nanowire material parameters to understand how they relate to the nanowire device performance. Multiple microscopy techniques are performed to determine the nanowire morphology and contact effectiveness. Optical characterization of bare and fabricated nanowires is used to determine the anti-reflection properties of nanowire arrays. Photoluminescence and electroluminescence spectroscopy are performed. Illuminated current-voltage characteristics and quantum efficiencies are determined. Specular and diffuse reflectivities are measured as a function of wavelength. Technology computer-aided design (TCAD) software is used to simulate the performance of the overall nanowire device. The contribution from quantum dots or quantum wells is simulated by solving for the carrier wavefunctions and density of states with the quantum structures. The discretized density of states from the quantum dots is modelled and used in a complete drift-diffusion device simulation to reproduce electroluminescence results. The carrier transport properties are modified to demonstrate effects on the overall device performance. An alternate design is also proposed which uses an InGaN nanowire subcell on top of a silicon bottom subcell. The dual-junction design allows a broader absorption of the solar spectrum, increasing the operating voltage through monolithically grown series-connected, current-matched subcells. The performance of such a cell is simulated through drift-diffusion simulations of a dual-junction InGaN/Si solar cell. The effects of switching to a nanowire subcell based on the nanowires studied in this thesis is discussed.

abstract: Flexibility, reconfigurability and wearability technologies for antenna designs are presented, investigated and merged in this work. Prior to the design of these radiating elements, a study is conducted on several flexible substrates and how to fabricate flexible devices. Furthermore, the integration of active devices into the flexible substrates is also investigated. A new approach of designing inkjet-printed flexible reconfigurable antennas, based on the concept of printed slot elements, is proposed. An alternate technique to reconfigure the folded slot antenna is also reported. The proposed radiator works for both Wireless Local Area Network (WLAN) and Worldwide Interoperability for Microwave Access (WiMAX) applications. The flexible reconfigurable antenna is also redesigned to resonate at both (2.4/5.2 GHz) for WLAN devices and its Multiple-Input Multiple-Output (MIMO) configuration is reported. Two orthogonal elements are used to form the MIMO antenna system for better isolation. The wearability of the proposed flexible reconfigurable radiator is also discussed. Since wearable antennas operate close to the human body, which is considered as a lossy tissue, an isolation between the radiating elements and human body is required to improve the radiation characteristics and to reduce the Specific Absorption Rate (SAR). The proposed antenna is redesigned on an Artificial Magnetic Conductor (AMC) surface that also functions as a ground plane to isolate the radiator from the human body. To examine its performance as a body-worn device, it is measured at different positions on the human body. Furthermore, simulations show that the SAR level is reduced when using the AMC surface. The proposed wearable antenna works for both Wireless Body Area Network (WBAN) and WiMAX body-worn wireless devices. Electromagnetic bandgap (EBG) structures are used to suppress surface wave propagation in printed antennas. However, due to the presence of vias, not all of them can be utilized in flexible radiators. Thus, a Perforated High Impedance Surface (PHIS) is proposed which suppresses the surface waves without the need of vias, and it also serves as a ground plane for flexible antennas. The surface wave suppression and the antenna applications of the proposed PHIS surface are discussed. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2017

Referências de tensão integradas sempre foram um bloco fundamental de qualquer sistema eletrônico e um importante tópico de pesquisa que tem sido estudado extensivamente nos últimos 50 anos. Uma tensão de referência é um circuito que provê uma tensão estável com baixa sensibilidade a variações em temperatura, alimentação, carga, características do processo de fabricação e tensões mecânicas de encapsulamento. Elas são normalmente implementadas através da soma ponderada de dois fenômenos físicos diferentes, com comportamentos em temperatura opostos. Normalmente, a tensão térmica, relacionada à constante de Boltzmann e à carga do elétron, fornece uma dependência positiva com temperatura, enquanto que a tensão base-emissor VBE de um transistor bipolar ou a tensão de limiar de um MOSFET fornece o termo complementar. Um bloco auxiliar é às vezes utilizado para fornecer as correntes de polarização do circuito, e outros blocos adicionais implementam a soma ponderada. A evolução da tecnologia de processos é o principal fator para aplicações em baixa tensão, enquanto que a emergência de dispositivos portáteis operados a bateria, circuitos biomédicos implantáveis e dispostivos de captura de energia do ambiente restringem cada circuito a consumir o mínimo possivel. Portanto, alimentações abaixo de 1 V e consumos na ordem de nanoWatts se tornaram características fundamentais de tais circuitos. Contudo, existem diversos desafios ao projetar referências de tensão de alta exatidão em processos CMOS modernos sob essas condições. As topologias tradicionais não são adequadas pois elas provêm uma referência de tensão acima de 1 V, e requerem resistências da ordem de G para atingir tão baixo consumo de potência, ocupando assim uma grande área de silício. Avanços recentes atingiram tais níveis de consumo de potência, porém com limitada exatidão, custosos procedimentos de calibração e grande área ocupada em silício. Nesta dissertação apresentam-se duas novas topologias de circuitos: uma tensão de junção bipolar com compensação de curvatura que não utiliza resistores e é auto-polarizada; e um circuito de referência bandgap sem resistores que opera abaixo de 1 V (também chamado de sub-bandgap). Ambos circuitos operam com consumo na ordem de nanoWatts e ocupam pequenas áreas de silício. Resultados de simulação para dois processos diferentes, 180 nm e 130 nm, e resultados experimentais de uma rodada de fabricação em 130 nm apresentam melhorias sobre tais limitações, mantendo as características desejadas de não conter resistores, ultra baixo consumo, baixa tensão de alimentação e áreas muito pequenas. / Integrated voltage references have always been a fundamental block of any electronic system, and an important research topic that has been extensively studied in the past 50 years. A voltage reference is a circuit that provides a stable voltage with low sensitivity to variations in temperature, supply, load, process characteristics and packaging stresses. They are usually implemented through the weighted sum of two independent physical phenomena with opposite temperature dependencies. Usually the thermal voltage, related to the Boltzmann’s constant and the electron charge, provides a positive temperature dependence, while the silicon bandgap voltage or a MOSFET’s threshold voltage provide the complementary term. An auxiliary biasing block is sometimes necessary to provide the necessary currents for the circuit to work, and additional blocks implement the weighted sum. The scaling of process technologies is the main driving factor for low voltage operation, while the emergence of portable battery-operated, implantable biomedical and energy harvesting devices mandate that every circuit consume as little power as possible. Therefore, sub-1 V supplies and nanoWatt power have become key characteristics for these kind of circuits, but there are several challenges when designing high accuracy voltage references in modern CMOS technologies under these conditions. The traditional topologies are not suitable because they provide a reference voltage above 1 V, and to achieve such power consumption levels would require G resistances, that occupy a huge silicon area. Recent advances have achieved these levels of power consumption but with limited accuracy, expensive calibration procedures and large silicon area.

Esta tese de doutorado trata de dois desafios que projetistas de circuitos integrados analógicos enfrentam quando estimando a confiabilidade de transistores fabricados em modernos processos CMOS: radiação e ruído flicker. Em relação a radiação, o foco desde trabalho é a Dose Total Ionizante (TID): acumulação de dose ionizante (elétrons e prótons) durante um longo período de tempo nas camadas isolantes dos dispositivos, então resultando na degradação dos parâmetros elétricos (por exemplo, a tensão de limiar e as correntes de fuga). Este trabalho apresenta um caso de estudo composto por circuitos referência tensões de baseados na tensão de bandgap e na tensão de limiar dos transistores. Esses circuitos foram fabricados em uma tecnologia comercial CMOS de 130 nm. Um chip contendo os circuitos foi irradiado usando raio gama de uma fonte de cobalto (60 Co), e o impacto dos efeitos da radiação até uma dose de 490 krad nas tensões de saída é apresentado. Foi verificado que o impacto da radiação foi similar ou até mesmo mais severo que os efeitos causados pelo processo de fabricação para a maior parte dos circuitos projetados. Para as referências baseadas na tensão de bandgap implementadas com transistores de óxido fino e grosso, a variação na tensão de saída causada pela radiação foi de 5.5% e 15%, respectivamente. Para as referências baseadas na tensão de limiar, a variação da tensão de saída foi de 2% a 15% dependendo da topologia do circuito. Em relação ao ruído, o foco desta tese é no ruído flicker do transitor MOS quando este está em operação ciclo-estacionária. Nesta condição, a tensão no terminal da porta está constantemente variando durante a operação e o ruído flicker se torna uma função da tensão porta-fonte e não é precisamente estimado pelos tradicionais modelos de ruído flicker dos transistores MOS. Esta tese apresenta um caso de estudo composto por osciladores de tensão (topologia baseada em anel e no tanque LC) projetados em processos 45 e 130 nm. A frequência de oscilação e sua dependência em relação à polarização do substrato dos transistores foi investigada. Considerando o oscilador em anel, a média da variação da frequência de oscilação causada pela variação da tensão de alimentação e da polarização do substrato foi 495 kHz/mV e 81 kHz/mV, respectivamente. A média da frequência de oscilação é de 103,4 MHz e a média do jitter medido para 4 amostras é de 7.6 ps. Para o tanque LC, a frequência de oscilação medida é de 2,419 GHz e sua variação considerando 1 V de variação na tensão de substrato foi de aproximadamente 0,4 %. / This thesis is focused on two challenges faced by analog integrated circuit designers when predicting the reliability of transistors implemented in modern CMOS processes: radiation and noise. Regarding radiation, the concern of this work is the Total Ionizing Dose (TID): accumulation of ionizing dose deposited (electrons and protons) over a long time in insulators leading to degradation of electrical parameters of transistors (e.g. threshold voltage and leakage). This work presents a case-study composed by bandgap-based and threshold voltagebased voltage reference circuits implemented in a commercial 130 nm CMOS process. A chip containing the designed circuits was irradiated through γ-ray Cobalt source (60 Co) and the impact of TID effects up to 490 krad on the output voltages is presented. It was found that the impact of radiation on the output voltage accuracy was similar or more severe than the variation caused by the process variability for most of the case-study circuits. For the bandgap-based reference implemented using thin-oxide and thick-oxide transistors, TID effects result in a variation of the output voltage of 5.5 % and 12%, respectively. For the threshold voltage references, the output variation was between 2% and 15% depending on the circuit topology. Regarding noise, the concern of this work is the transistor flicker noise under cyclostationary operation, that is, when the voltage at transistor gate terminal is constantly varying over time. Under these conditions, the flicker noise becomes a function of VGS; and its is not accurately predicted by traditional transistor flicker noise models. This thesis presents a case-study composed by voltage oscillators (inverter-based ring and LC-tank topologies) implemented in 45 and 130 nm CMOS processes. The oscillation frequency and its dependency on the bulk bias were investigated. Considering the ring-oscillator, the average oscillation frequency variation caused by supply voltage and bulk bias variation are 495 kHz/mV and 81 kHz/mV, respectively. The average oscillation frequency is 103.4 MHz for a supply voltage of 700 mV, and the measured averaged period jitter for 4 measured samples is 7.6 ps. For the LC-tank, the measured oscillation frequency was 2.419 GHz and the total frequency variation considering 1 V of bulk bias voltage was only ~ 0.4 %.

Esta tese de doutorado trata de dois desafios que projetistas de circuitos integrados analógicos enfrentam quando estimando a confiabilidade de transistores fabricados em modernos processos CMOS: radiação e ruído flicker. Em relação a radiação, o foco desde trabalho é a Dose Total Ionizante (TID): acumulação de dose ionizante (elétrons e prótons) durante um longo período de tempo nas camadas isolantes dos dispositivos, então resultando na degradação dos parâmetros elétricos (por exemplo, a tensão de limiar e as correntes de fuga). Este trabalho apresenta um caso de estudo composto por circuitos referência tensões de baseados na tensão de bandgap e na tensão de limiar dos transistores. Esses circuitos foram fabricados em uma tecnologia comercial CMOS de 130 nm. Um chip contendo os circuitos foi irradiado usando raio gama de uma fonte de cobalto (60 Co), e o impacto dos efeitos da radiação até uma dose de 490 krad nas tensões de saída é apresentado. Foi verificado que o impacto da radiação foi similar ou até mesmo mais severo que os efeitos causados pelo processo de fabricação para a maior parte dos circuitos projetados. Para as referências baseadas na tensão de bandgap implementadas com transistores de óxido fino e grosso, a variação na tensão de saída causada pela radiação foi de 5.5% e 15%, respectivamente. Para as referências baseadas na tensão de limiar, a variação da tensão de saída foi de 2% a 15% dependendo da topologia do circuito. Em relação ao ruído, o foco desta tese é no ruído flicker do transitor MOS quando este está em operação ciclo-estacionária. Nesta condição, a tensão no terminal da porta está constantemente variando durante a operação e o ruído flicker se torna uma função da tensão porta-fonte e não é precisamente estimado pelos tradicionais modelos de ruído flicker dos transistores MOS. Esta tese apresenta um caso de estudo composto por osciladores de tensão (topologia baseada em anel e no tanque LC) projetados em processos 45 e 130 nm. A frequência de oscilação e sua dependência em relação à polarização do substrato dos transistores foi investigada. Considerando o oscilador em anel, a média da variação da frequência de oscilação causada pela variação da tensão de alimentação e da polarização do substrato foi 495 kHz/mV e 81 kHz/mV, respectivamente. A média da frequência de oscilação é de 103,4 MHz e a média do jitter medido para 4 amostras é de 7.6 ps. Para o tanque LC, a frequência de oscilação medida é de 2,419 GHz e sua variação considerando 1 V de variação na tensão de substrato foi de aproximadamente 0,4 %. / This thesis is focused on two challenges faced by analog integrated circuit designers when predicting the reliability of transistors implemented in modern CMOS processes: radiation and noise. Regarding radiation, the concern of this work is the Total Ionizing Dose (TID): accumulation of ionizing dose deposited (electrons and protons) over a long time in insulators leading to degradation of electrical parameters of transistors (e.g. threshold voltage and leakage). This work presents a case-study composed by bandgap-based and threshold voltagebased voltage reference circuits implemented in a commercial 130 nm CMOS process. A chip containing the designed circuits was irradiated through γ-ray Cobalt source (60 Co) and the impact of TID effects up to 490 krad on the output voltages is presented. It was found that the impact of radiation on the output voltage accuracy was similar or more severe than the variation caused by the process variability for most of the case-study circuits. For the bandgap-based reference implemented using thin-oxide and thick-oxide transistors, TID effects result in a variation of the output voltage of 5.5 % and 12%, respectively. For the threshold voltage references, the output variation was between 2% and 15% depending on the circuit topology. Regarding noise, the concern of this work is the transistor flicker noise under cyclostationary operation, that is, when the voltage at transistor gate terminal is constantly varying over time. Under these conditions, the flicker noise becomes a function of VGS; and its is not accurately predicted by traditional transistor flicker noise models. This thesis presents a case-study composed by voltage oscillators (inverter-based ring and LC-tank topologies) implemented in 45 and 130 nm CMOS processes. The oscillation frequency and its dependency on the bulk bias were investigated. Considering the ring-oscillator, the average oscillation frequency variation caused by supply voltage and bulk bias variation are 495 kHz/mV and 81 kHz/mV, respectively. The average oscillation frequency is 103.4 MHz for a supply voltage of 700 mV, and the measured averaged period jitter for 4 measured samples is 7.6 ps. For the LC-tank, the measured oscillation frequency was 2.419 GHz and the total frequency variation considering 1 V of bulk bias voltage was only ~ 0.4 %.

Referências de tensão integradas sempre foram um bloco fundamental de qualquer sistema eletrônico e um importante tópico de pesquisa que tem sido estudado extensivamente nos últimos 50 anos. Uma tensão de referência é um circuito que provê uma tensão estável com baixa sensibilidade a variações em temperatura, alimentação, carga, características do processo de fabricação e tensões mecânicas de encapsulamento. Elas são normalmente implementadas através da soma ponderada de dois fenômenos físicos diferentes, com comportamentos em temperatura opostos. Normalmente, a tensão térmica, relacionada à constante de Boltzmann e à carga do elétron, fornece uma dependência positiva com temperatura, enquanto que a tensão base-emissor VBE de um transistor bipolar ou a tensão de limiar de um MOSFET fornece o termo complementar. Um bloco auxiliar é às vezes utilizado para fornecer as correntes de polarização do circuito, e outros blocos adicionais implementam a soma ponderada. A evolução da tecnologia de processos é o principal fator para aplicações em baixa tensão, enquanto que a emergência de dispositivos portáteis operados a bateria, circuitos biomédicos implantáveis e dispostivos de captura de energia do ambiente restringem cada circuito a consumir o mínimo possivel. Portanto, alimentações abaixo de 1 V e consumos na ordem de nanoWatts se tornaram características fundamentais de tais circuitos. Contudo, existem diversos desafios ao projetar referências de tensão de alta exatidão em processos CMOS modernos sob essas condições. As topologias tradicionais não são adequadas pois elas provêm uma referência de tensão acima de 1 V, e requerem resistências da ordem de G para atingir tão baixo consumo de potência, ocupando assim uma grande área de silício. Avanços recentes atingiram tais níveis de consumo de potência, porém com limitada exatidão, custosos procedimentos de calibração e grande área ocupada em silício. Nesta dissertação apresentam-se duas novas topologias de circuitos: uma tensão de junção bipolar com compensação de curvatura que não utiliza resistores e é auto-polarizada; e um circuito de referência bandgap sem resistores que opera abaixo de 1 V (também chamado de sub-bandgap). Ambos circuitos operam com consumo na ordem de nanoWatts e ocupam pequenas áreas de silício. Resultados de simulação para dois processos diferentes, 180 nm e 130 nm, e resultados experimentais de uma rodada de fabricação em 130 nm apresentam melhorias sobre tais limitações, mantendo as características desejadas de não conter resistores, ultra baixo consumo, baixa tensão de alimentação e áreas muito pequenas. / Integrated voltage references have always been a fundamental block of any electronic system, and an important research topic that has been extensively studied in the past 50 years. A voltage reference is a circuit that provides a stable voltage with low sensitivity to variations in temperature, supply, load, process characteristics and packaging stresses. They are usually implemented through the weighted sum of two independent physical phenomena with opposite temperature dependencies. Usually the thermal voltage, related to the Boltzmann’s constant and the electron charge, provides a positive temperature dependence, while the silicon bandgap voltage or a MOSFET’s threshold voltage provide the complementary term. An auxiliary biasing block is sometimes necessary to provide the necessary currents for the circuit to work, and additional blocks implement the weighted sum. The scaling of process technologies is the main driving factor for low voltage operation, while the emergence of portable battery-operated, implantable biomedical and energy harvesting devices mandate that every circuit consume as little power as possible. Therefore, sub-1 V supplies and nanoWatt power have become key characteristics for these kind of circuits, but there are several challenges when designing high accuracy voltage references in modern CMOS technologies under these conditions. The traditional topologies are not suitable because they provide a reference voltage above 1 V, and to achieve such power consumption levels would require G resistances, that occupy a huge silicon area. Recent advances have achieved these levels of power consumption but with limited accuracy, expensive calibration procedures and large silicon area.

The monolithic integration of III-V semiconductors on Si substrates is a part of a long-term technological roadmap for the semiconductor industry towards More-than-Moore technologies. Despite of the different lattice constants and thermal expansion coefficients, research efforts over the last two decades have shown that III-V crystals with a high structural quality can be grown epitaxially in the form of nanowires directly on Si using CMOS-compatible (Au-free) methods. Among other III-V compounds, InxGa1-xAs is of the special interest for the use in infrared photonics and high-speed electronics due to its tunable direct bandgap and low electron effective mass, respectively. For comparison, InxGa1-xAs thin films are typically grown on lattice-matched InP substrates with a limited range of compositions at around x=0.52. The realization of InxGa1-xAs nanowires on Si, though, has been proved challenging owing to the limited In-content when the nanowires are grown Ga-catalyzed or the high density of stacking faults when the nanowires are grown catalyst-free. In this work, the use of highly lattice-mismatched GaAs/InxGa1-xAs and GaAs/InxAl1-xAs core/shell nanowires on Si(111) substrates have been studied as an alternative to InxGa1-xAs nanowires. The core/shell mismatch strain and its accommodation within the nanowires plays an important role in the growth, the structural, and the electronic properties of the nanowires. A key parameter in this work was the unusually small diameter of 20 – 25 nm of the GaAs core. First, the strain-induced bending of the nanowires during the growth of the shell by molecular beam epitaxy was investigated. It was apparent that the nanowires bend as a result of a preferential incorporation of In adatoms on one side of the nanowires. To obtain straight nanowires with symmetric shell composition and thickness around the core, it was necessary to choose relatively low growth temperatures and high growth rates that limited the surface diffusivity of In adatoms. Second, the strain accommodation in straight nanowires was investigated as a function of the shell thickness and composition using a combination of Raman scattering spectroscopy and X-ray diffraction. For a fixed shell composition of x=0.20 and small enough shell thicknesses, the strain in the shell is compressive and decreases progressively as the shell grows thicker. On the other hand, the strain in the core is tensile with hydrostatic character and increases with shell thickness. Finally, for shell thicknesses larger than 40 nm, the shell becomes strain-free, whereas the strain in the core saturates at 3.2% without any dislocations. For a fixed shell thickness of 80 nm, the strain in the core was further increased by increasing the In-content in the shell, reaching values as high as 7% for x=0.54. A plastic relaxation via misfit dislocations was observed only for the next highest In-content of x=0.70. In agreement to theoretical predictions, the tensile strain in the core resulted in a large reduction of the GaAs bandgap (as measured by photoluminescence spectroscopy), up to approximately 40% of the strain-free value. A similar reduction in electron effective mass is also expected. The transport properties of electrons inside the strained GaAs core were assessed by optical-pump terahertz-probe spectroscopy. Quite high mobility values of approximately 6100 cm2/Vs at 300 K for a carrier concentration of 9×1017 cm−3 were measured, which are the highest reported in the literature for GaAs nanowires, but also higher than the values for unstrained bulk GaAs. The importance of the results in this work is two-fold. On the one hand, strain-free InxGa1-xAs nanowire shells were grown on Si substrates with x up to 0.54 and thicknesses well beyond the critical thickness of their thin film counterparts. Such shells could potentially be employed as conduction channels in high electron mobility transistors (HEMTs) integrated in Si platforms. On the other hand, highly tensile-strained GaAs cores with electronic properties like those of InxGa1-xAs thin films were obtained. In this case, the results demonstrate, that GaAs nanowires can be suitable for photonic devices across the near-infrared range, including telecom photonics at 1.3 and potentially 1.55 μm, as well as for high-speed electronics. GaAs as a binary material is expected to be advantageous compared to InxGa1-xAs due to the absence of structural imperfections typically present in ternary alloys. Finally, to explore the potential of the core/shell nanowires as HEMTs, self-consistent Schrödinger-Poisson calculations of two different modulation-doped heterostructures were performed. In the case of a strained GaAs core overgrown by an unstrained InxGa1-xAs shell and an additional unstrained Si-doped InxAl1-xAs shell, the possibility to form a cylindrical-like two-dimensional electron gas inside the InxGa1-xAs shell was found. In the alternative case of a strained GaAs core overgrown by an unstrained Si-doped InxAl1-xAs shell, it was found that it is possible to form a quasi-one-dimensional electron gas at the center of the core. Both structures are the subject of ongoing research.:1 Introduction 1 2 Fundamentals and state-of-the-art 7 2.1 Electronic and structural properties of III-V semiconductors 7 2.2 Growth of III-V nanowires on Si 20 2.3 Core/shell heterostructure nanowires 29 2.4 Strain in epilayers and core/shell nanowires 36 2.5 Strain engineering in core/shell nanowires and its effect on band parameters 46 2.6 Modulation-doped III-V semiconductor heterostructures 56 3 Methods 61 3.1 Optical and electron microscopes 61 3.2 X-ray diffraction 64 3.3 Raman scattering spectroscopy 65 3.4 Photoluminescence spectroscopy 75 3.5 Optical-pump terahertz-probe spectroscopy and photoconductivity in semiconductors 77 3.6 Device processing 82 3.7 Semiconductor nanodevice software “nextnano” 85 3.8 MBE for crystal growth and core/shell nanowire growth 86 4 Results and discussions 91 4.1 Structural, compositional analyses of straight nanowires and coherent growth limit 91 4.2 Bent nanowires 95 4.3 Strain analyses in core/shell nanowires 97 4.3.1 Dependence of strain on shell thickness 97 4.3.2 Dependence of strain on the shell chemical composition 102 4.3.3 Dependence of strain on the core diameter 105 4.4 Strain-induced modification of electronic properties 106 4.5 Strain-enhanced electron mobility of GaAs nanowires higher than the bulk limit 114 4.6 Towards high electron mobility transistors 123 5 Conclusion and outlook 129 Bibliography 131 List of abbreviations I List of Symbols III List of publications VII List of conference contributions VIII Acknowledgements X

This diploma thesis deals with optimization of planar antennas on the Electromagnetic Bandgap (EBG) substrates by the help of Ant Colony Optimization (ACO). This method is based on the communications mechanisms of a real ant colony. Firstly, the working principle of the planar antennas and the theory of the Ant Colony Optimization are analyzed. Next, the description of the working principle of the Electromagnetic Bandgap and generally physical phenomena accompanying electromagnetic waves propagation in a periodic medium are given. In the second part of this thesis, the ACO was implemented into the VBA language, and was applied to two models of planar antennas. These models were created in the CST Microwave Studio. After an optimization of the antennas the results were evaluated, and the optimization of one of the antennas was compared to the optimization methods in CST Microwave Studio. Then, the standard substrate of the second model was replaced by the EBG substrate, and the results were confronted. Two types of EBG lattice were used. The design procedure of the square lattice was described, and the dispersion diagram was created in the CST Microwave Studio. In the final part of thesis, the verification of the results was carried out in Ansoft HFSS, and the results from both simulation programs were compared to each other.

This diploma thesis is specialized on a design of a high accuracy voltage reference Bandgap. A very low temperature coefficient and output voltage approx. 1,205V are the main features of this circuit. The paper contains a derivation of the Bandgap principle, examples of realizations of the circuits and methods of compensation temperature dependence and manufacture process, design of Brokaw and Gilbert reference, design of a testchip and measurement results.