The third quadrant (3rd-quad) conduction (or reverse conduction) of power transistors is critical for synchronous power converters. For power metal-oxide-semiconductor field-effect-transistors (MOSFETs), there are two current paths in the 3rd-quad conduction, namely the MOS channel path and the body diode path. It is well known that, for 1.2 kV silicon carbide (SiC) planar MOSFETs, the conduction loss in the 3rd-quad is reduced by turning on the MOS channel with a positive gate bias (VGS) and keeping the dead time as small as possible. Under this scenario, the current is conducted through both paths, allowing the device to take advantage of the zero 3rd-quad forward voltage drop (VF3rd) of the MOS channel path and the small differential resistance of the body diode path. However, in this thesis work, this popular belief is found to be invalid for power MOSFETs with higher voltage ratings (e.g., 3.3 kV and 10 kV), particularly at high temperatures and current levels. The aforementioned MOS channel and body diode paths compete in the device’s 3rd-quad conduction, and their competition is affected by VGS and device structure. This thesis work presents a comparative study on the 3rd-quad behavior of 1.2 kV to 10 kV SiC planar MOSFET through a combination of device characterization, TCAD simulation and analytical modeling. It is revealed that, once the MOS channel turns on, it changes the potential distribution within the device, which further makes the body diode turn on at a source-to-drain voltage (VSD) much higher than the built-in potential of the pn junction. In 10 kV SiC MOSFETs, with the MOS channel on, the body diode does not turn on over the entire practical VSD range. As a result, the positive VGS leads to a completely unipolar conduction via the MOS channel, which could induce a higher VF3rd than the bipolar body diode at high temperatures. Circuit test is performed, which validates that a negative VGS control provides the smallest 3rd-quad voltage drop and conduction loss at high temperatures in 10 kV SiC planar MOSFET. The study is also extended to the trench MOSFET, another major structure of commercial SiC MOSFETs. Based on the revealed physics for planar MOSFETs, the optimal VGS control for the 3rd-quad conduction in different types of commercial trench MOSFETs is discussed, which provides insights for the design of high-voltage trench MOSFETs. These results provide key guidelines for the circuit applications of medium-voltage SiC power MOSFETs. / M.S. / Recent years, the prosperity of power electronics applications such as electric vehicle and smart grid has led to a rapid increase in the adoption of wide bandgap (WBG) power devices. Silicon Carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) is one of the most attractive candidates in WBG devices, owing to its good tradeoff between breakdown voltage and on resistance, capability of operation at high temperatures, and superior device robustness over other WBG power devices. In most power converters, power device is required to conduct current in its third quadrant (3rd-quad) (i.e., conduct reverse current) either for handling current during the dead time or acting as a commutation switch. In a SiC MOSFET, there are two current paths in the 3rd-quad conduction, namely the MOS channel path and the body diode path. It is widely accepted that by turning on the MOS channel with a positive gate-to-source bias (VGS), both paths are turned on in parallel such that the 3rd-quad conduction loss can be reduced. In this thesis work, it is shown that this long-held opinion does not hold for SiC MOSFETs with high voltage ratings (e.g., 3.3 kV and 10 kV). Through a combination of device characterization, TCAD simulation, and analytical modeling, this thesis work unveils the competing current sharing between the MOS channel and the body diode. Once the MOS channel turns on, it delays the turn-on of the body diode and suppresses the diode current. This effect is more pronounced in MOSFETs with higher voltage ratings. In 10 kV SiC MOSFETs, with the MOS channel on, the body diode does not turn on in the practical operation conditions. At high temperatures, as the bipolar diode path possesses the conductivity modulation, which can significantly lower the voltage drop and is absent in the MOS channel, it would be optimal to turn off the MOS channel. Circuit test is also performed to validate these device findings and evaluate their impact on device applications. Finally, the study is also extended to the commercial SiC trench MOSFET, the other mainstream type of SiC power MOSFETs. These results provide key guidelines for the circuit applications of medium-voltage SiC power MOSFETs.

No description available.

Power device robustness refers to the device capability of withstanding abnormal events in power electronics applications, which is one of the key device capabilities that are desired in numerous applications. While the current robustness test methods and qualification standards are developed across the 70 years of Silicon (Si) device history, their applicability to the recent wide bandgap (WBG) power devices is questionable. While the market of WBG power devices has exceeded $1 billion and is fast growing, there are many knowledge gaps regarding their robustness, including the failure or degradation physics, testing methods, and lifetime extraction. This dissertation work studies the robustness of Gallium Nitride (GaN) power device. The structures of many GaN power devices are fundamentally different from Si or Silicon Carbide (SiC) power devices, leading to numerous open questions on GaN power device robustness. Based on the device structure, this dissertation is divided into two parts: The first half discusses the robustness of lateral GaN high electron mobility transistor (HEMT), which recently sees rapid adoption among wide range of applications such as the power adapter and chargers, data center, and photovoltaic panels. The absence of p-n junction between the source and drain of GaN HEMT results in the lack of avalanche mechanism. This raises a concern on the device capability of withstanding surge-energy or overvoltage stress, which hinders the penetration of GaN HEMTs in broader applications. To address this concern, the study begins with conducting the single-event unclamped inductive switching (UIS) test on two mainstream commercial p-gate GaN HEMTs with the Ohmic- and Schottky-type gate contacts, where the GaN HEMT is found to withstand surge energy through a resonant energy transfer between the device capacitance and the loop inductance. The failure mechanism is identified to be a pure electrical breakdown determined by device transient breakdown voltage (BV). The BV of GaN HEMT is further found to be "dynamic" from the switching tests with various pulse widths and frequencies, which is further explained by the time-dependent buffer trapping. This dynamic BV (BVDYN) phenomenon indicates that the static or single-pulse test may not reveal the true BV of GaN HEMT in high frequency switching applications. To address this gap, a novel testbed based on a zero-voltage-switching converter with an active clamping circuit is developed to enable the stable switching with kilovolt overvoltage and megahertz frequency. The overvoltage failure boundaries and failure mechanisms of four commercial p-gate GaN HEMTs from multiple vendors are explored. In addition to the frequency-dependent BVDYN, two new failure mechanisms are observed in some devices, which are attributable to the serious carrier trapping in GaN HEMTs under the high-frequency overvoltage switching. At last, based on the findings in the high frequency overvoltage test (HFOT), a physics-based lifetime model for commercial GaN HEMTs utilizing the device on resistance (RON) shift is established and validated by experimental results. Overall, the switching-based test methodology and experimental results provide critical references for the overvoltage protection and qualification of GaN power HEMTs. The second half of the dissertation discusses the robustness of the vertical GaN fin-channel junction field effect transistor (Fin-JFET), a promising pre-commercialized GaN power device with the p-n junction embedded between the gate and drain which enables the avalanche breakdown. The robustness study on GaN JFET follows similar test approaches as Si metal-oxide-semiconductor field-effect transistor (MOSFET) with two key interests: the avalanche and short circuit capabilities. The avalanche breakdown is first explored via the single-event and repetitive UIS tests and under various gate drivers, from which an interesting "avalanche-through-fin-channel" mechanism is discovered. By leveraging this avalanche path, the electro-thermal stress migrates from the main blocking p-n junction to the n-GaN fin channel, resulting in a very favorable failure-to-open-circuit signature. The single-pulse critical avalanche energy density (EAVA) of vertical GaN Fin-JFET is measured to be as high as 10 J/cm2, which is much higher than the Si MOSFET and comparable to the SiC MOSFET. The short circuit capability is explored utilizing the hard-switching fault on the 650-V rated GaN Fin-JFET, with a gate driving circuit identical to the switching application to best mimic device operation in converters. The short circuit withstanding time is measured to be 30.5 µs at an input voltage of 400 V, 17.0 µs at 600 V, and 11.6 µs at 800 V, all among the longest reported for 600-700 V normally-off transistors. In addition, the failure-to-open-circuit signature is also shown in the single-event and repetitive short circuit tests; all devices retain the avalanche breakdown after failure, which is highly desirable for system applications. These results suggest that, while GaN HEMT is already available in market, vertical GaN Fin-JFET shows superior avalanche and short-circuit robustness and thereby can unlock great potential of GaN devices for applications like automotive powertrains, motor drives, and grids. / Doctor of Philosophy / In recent years, many power electronics applications such as data centers and electric vehicles have witnessed a rapid increase in the adoption of wide bandgap (WBG) power devices. The Gallium Nitride (GaN) device is one of the most attractive candidates in WBG devices, owing to its good tradeoff between breakdown voltage and on resistance, as well as the small gate charge that enables high frequency switching. For power devices, their robustness against overvoltage and overcurrent stresses is as important as their performance under normal operations. However, the new material, new device structure, and new device physics in GaN power devices brought up many open knowledge gaps in their robustness study, particularly under the dynamic operation in switching circuits. This dissertation presents the work in exploring the robustness of GaN power devices. Based on the device structure, the discussion is divided in two parts: The first half of the dissertation focuses on the overvoltage robustness of the lateral GaN High Electron Mobility Transistor (HEMT), the commercially available device covering 30 to 900 V voltage classes. A key feature of this device is the lack of p-n junction between source and drain, leading to an absence of avalanche capability. The study is conducted on mainstream, commercial p-gate GaN HEMTs, with a combination of circuit testing, microscale failure analysis, and physics-based device simulation. The main contribution is on three aspects: identifying the single-event and high-frequency repetitive overvoltage boundaries of GaN HEMT, unveiling the failure and degradation mechanisms under transient overvoltage conditions, and providing guidelines to GaN HEMT device users with proper robustness test methodology for device qualification and screening. The second half of the dissertation focuses on the robustness of vertical GaN fin-channel junction field effect transistor (Fin-JFET), a promising pre-commercial GaN power device with the p-n junction implemented between the source and drain. The robustness tests follow the classic approaches deployed for Silicon power devices, where both the avalanche and short circuit capabilities are investigated. From the single-event and repetitive test results, the GaN JFET shows excellent avalanche robustness with a desirable failure-to-open-circuit behavior, as well as a critical avalanche energy (EAVA) of 10 J/cm2 that is higher than the Silicon metal-oxide-semiconductor field-effect transistor (MOSFET) and comparable to the Silicon Carbide MOSFET. For a 650-V rated GaN Fin-JFET, a record high 30.5 μs short circuit time is demonstrated under the hard-switching fault condition at 400 V input voltage. Overall, the results show great potential of GaN power devices for the power electronics applications that involve more stressful operation conditions for devices.

No description available.

Bandgap determines the suitability of materials for device applications such as \cite{lyu2021predictive} light-emitting diodes (LED), solar cells, and photo-detectors. The accuracy of the bandgap predicted using standard LDA or GGA functional is underestimated by density functional theory (DFT) when compared to experimental values. However, DFT combined with Machine Learning (ML) allows computational screening of materials with better accuracy. The training data for the models is obtained from density functional theory calculations which consist of A, B, and X-site elemental properties. The feature importance procedure screens the relative important features among all input features considered in the study. CatBoost(CB) regression model, \cite{Catboost} is an open-source library for gradient boosting. It gives high-perfromance on decision tress as it is based on gradient boosting algorithm and is suitable for small data sets as reduces overfitting, is implemented that can accurately predict the bandgap of $A_2BX_6$ perovskite. Eleven ML techniques were implemented, and their predictions of energy bandgap were compared, such as gradient boosted, random forest, support vector, AdaBoost, linear, K-nearest neighbor, kernel ridge, and decision tree. As per the study, the best performance is achieved by CatBoost regression model.

Power-efficient circuits are a vital step in moving towards a greener future. Battery life can get substantially improved by decreasing the amount of power a circuit needs. Lower power also leads to less excess heat generated. Electronics are within everything today – from phones and microwaves to cars! If we want to optimize the electronics to require less power, we need to understand it. In some integrated circuits that utilize bipolar transistors, it has been concluded that the main limitation regarding low-power, high-temperature operations is leakage currents that arise in reverse biased p–n junctions. There is a lack of understanding regarding the magnitude of these leakage currents, especially at higher temperatures. This thesis aims to provide an understanding of the magnitude of the leakage currents in lateral gated PNP bipolar transistors and to provide empirical models of these currents.A discussion of semiconductor physics takes place, explaining how leakage currents arise in reverse-biased pn junctions. Measurements were taken on a chip with the help of different instruments and a relay network that configured the experimental setup into different circuits while measurements were being conducted.It was shown that the leakage currents are clearly exponential to temperature, as was expected. Empirical models are created with the help of the Gauss-Newton linearization method and shown to be of the form<img src="http://www.diva-portal.org/cgi-bin/mimetex.cgi?$y=%20%5Ctheta_1%20%5Cmathrm%7Be%7D%5E%7B%5Ctheta_2%5Cleft(T-%5Ctheta_4%5Cright)%7D+%5Ctheta_3$" data-classname="equation" data-title="" />,where 𝜃 are parameters for the different models.A discussion is held on the impact of the results and how to improve upon them. Numerous sources of error are discussed, and further work is recommended.

State-of-the-art silicon-based power supplies have reached a point of maturity in performance. Efficiency, power density, and cost are major trade-offs involved in further improvements. Most products are custom designed with significant non-recurrent engineering and manufacturing processes that are labor intensive. In particular, conventional magnetic components, including transformers and inductors, have largely remained the same for the past five decades. Those large and bulky magnetic components are major roadblocks toward an automated manufacturing process. In addition, there is no specific approach to reduce electromagnetic interference (EMI) in conventional practices. In certain cases, EMI filter design even requires a trial-and-error process. With recent advances in wide-bandgap (WBG) power semiconductor devices, namely, SiC and GaN, we have witnessed significant improvements in efficiency and power density, compared to their silicon counterparts. In a power factor correction (PFC) rectifier/inverter, the totem-pole configuration with critical conduction mode (CRM) operation to realize zero-voltage switching (ZVS) is deemed most desirable for a switching frequency 10 times higher than current practice. With a significantly higher operating frequency, the integration of inductors with embedded windings in the printed circuit board (PCB) is feasible. However, a PCB winding-based inductor has a fundamental limitation in terms of its power handling capability. The winding loss is proportional to the magnetomotive force (MMF), which is Ni. That is to say, with the number of layers (turns) and currents increased, winding loss is increased nonlinearly. Furthermore, for a large-size planar inductor, flux distribution is usually non-uniform, resulting in dramatically increased hysteresis loss and eddy loss. Thus, current designs are challenged by the capability to increase their power range. To address those issues, a modular building block approach is proposed in this dissertation. A planar PCB inductor is formed by an array of pillars that are integrated into one magnetic core, where each pillar handles roughly 750 W of power. The winding loss is reduced by limiting the number of turns for each pillar. The core loss is minimized with a proposed planar magnetic structure where rather uniformly distributed fluxes were observed in the plates. The proposed approach has a similar loss to a conventional litz wire-based design but features a higher power density and can be easily assembled in automation. A 3 kW high frequency PFC converter with 99% efficiency is demonstrated as an example. Furthermore, PCB-based designs up to 6 kW are provided. Another challenge in a WBG-based PFC/inverter is the high common-mode (CM) noises associated with the high dv/dt of the WBG devices. Symmetry and cancellation techniques are often employed to suppress CM noises in switching power converters. Meanwhile, shielding technique has been demonstrated to effectively suppress CM noises in an isolated converter with PCB-based transformer design. However, for non-isolated converters, such as PFC circuits, none of the techniques mentioned above are deemed applicable or justifiable. Recently, the balance technique has been demonstrated to effectively suppress CM noises up to a point where the parasitic ringing between the inductor and its winding capacitor is observed. This dissertation presents an improved balance technique in a PCB-based coupled inductor design that compensates for the detrimental effect of the interwinding capacitors. A CM noise model is established to simplify the convoluted couplings into a decoupled representation so as to illustrate the necessary conditions for realizing a balanced network. In the given 1 kW PFC example, CM noise suppression is effective in the frequency range of interest up to 30 MHz. The parasitic oscillation of inductors, known to be detrimental for CM noise reduction, is circumvented with the improved magnetic structure. By applying the balance technique to a PFC converter and the shielding technique to an LLC DC/DC converter, significant noise reductions were realized. This provides the opportunity to use a simple one-stage EMI filter to achieve the required EMI noise attenuation for a server power supply. This dissertation further offers an in-depth study on reducing the unwanted near-field couplings between the CM/DM inductors and DM filter capacitors, as well as unwanted self-parasitics such as the ESL of the DM capacitors. An exhaustive finite element analysis (FEA) and near field measurements are conducted to better understand the effect of frequency on the polarization of the near field due to the displacement current. The knowledge gained in this study enables one to minimize unwanted mutual coupling effects by means of physical placement of these filter components. Thus, for the first time, a single-stage EMI filter is demonstrated to meet the EMI standard in an off-line 1 kW, 12 V server power supply. With the academic contributions in this dissertation, a PCB winding-based inductor can be successfully applied to a high-frequency PFC/inverter to achieve high efficiency, high power density, automation in manufacturing, lower EMI, and lower cost. Suffice it to say, the proposed approach enables a paradigm shift in the designing and manufacturing of a PFC/inverter for the next generation of power supplies. / Doctor of Philosophy / State-of-the-art silicon device-based switching power supplies have reached a point of maturity in performance. Efficiency, power density, and cost are major trade-offs involved in performance improvements. Most products are custom designed, requiring significant non-recurrent engineering and labor-intensive manufacturing processes. In particular, conventional magnetic components, including transformers and inductors, have largely remained the same for the past five decades. Those large and bulky magnetic components are major roadblocks toward an automated manufacturing process. In addition, there is no specific approach to reduce electromagnetic interference (EMI) in conventional practices. In consequence, a large multi-stage EMI filter is usually adopted between the power converter and the grid to reduce the EMI noise. It generally occupies 1/4-1/3 of the total converter volume. In certain cases, EMI filter design even requires a trial-and-error process. Suffice it to say, EMI is still regarded as both science and art. With recent advances in wide-bandgap (WBG) power semiconductor devices, namely, SiC and GaN, we have witnessed significant improvements in efficiency and power density, compared to their silicon counterparts. With GaN devices, the switching frequency of a PFC converter is able to be increased by 10 times compared to the state-of-the-art design without compromising efficiency. With a significantly higher operating frequency, the integration of inductors with embedded windings in the printed circuit board (PCB) is feasible. However, the state-of-the-art PCB winding-based inductor has a fundamental limitation in power range. Its winding loss and core loss increase dramatically in high powers. To address this issue, a modular building block approach is proposed in this dissertation. A planar PCB inductor is formed by an array of pillars that are integrated into one magnetic core, where each pillar handles roughly 750 W of power. The winding loss is reduced by limiting the number of turns for each pillar. The core loss is minimized with a proposed planar magnetic structure where rather uniformly distributed fluxes have been observed in the magnetic core plates. A 3 kW high-frequency PFC converter with a 99% peak efficiency is demonstrated as an example. Furthermore, PCB-based designs up to 6 kW are provided. Another challenge in a WBG-based PFC/inverter is the high common-mode (CM) noises caused by the high switching speed of the WBG devices. Symmetry and cancellation techniques are often employed to suppress CM noises in switching power converters. Meanwhile, shielding technique has been demonstrated to effectively suppress CM noises in an isolated converter with PCB-based transformer. However, for non-isolated converters, such as PFC circuits, none of the techniques mentioned above are deemed applicable or justifiable. Recently, the balance technique has been demonstrated to effectively suppress CM noises up to several MHz. However, the CM noise reduction is not effective beyond that. This dissertation presents an improved balance technique in a PCB-based coupled inductor to circumvent the limits. In the given 1 kW PFC example, CM noise suppression is effective in the frequency range of interest up to 30 MHz. By applying the balance technique to a PFC converter and the shielding technique to an LLC DC/DC converter, significant noise reductions were realized. This provides the opportunity to use a simple one-stage EMI filter to achieve the required EMI noise attenuation for a server power supply. It features a smaller volume compared to a conventional multi-stage filter. To further enhance the filter's performance at high frequencies, an exhaustive finite element analysis and near field measurements are conducted to better understand the effect of frequency on the polarization of the near field due to the displacement current. The knowledge gained in this study enables one to minimize unwanted mutual coupling effects through physical placement of these filter components. Several approaches for improving the filter performance at high frequency are conducted. With these approaches applied, a single-stage filter is demonstrated in an off-line 1 kW, 12 V server power supply. Thus, for the first time, a single-stage EMI filter can be contemplated to meet the EMI standard in server power supplies. With the academic contributions in this dissertation, a PCB-winding based inductor can be successfully applied to a high-frequency PFC/inverter to achieve high efficiency, high power density, automation in manufacturing, lower EMI, and lower cost. Suffice it to say, the proposed approach in this work enables a paradigm shift in the designing and manufacturing of a PFC/inverter for the next generation of power supplies.

Interest in wide bandgap semiconductors such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga 2 O 3 ) and diamond has increased due to their ability to deliver high power, high switching frequency and low loss electronic devices for power conversion applications. To meet these requirements, semiconductor material defects, introduced during growth and fabrication, must be minimized. Otherwise, theoretical limits of operation cannot be achieved. In this dissertation, the non-ideal current- voltage (IV) behavior of GaN-based Schottky diodes is discussed first. Here, a new model is developed to explain better the temperature dependent performance typically associated with a multi-Gaussian distribution of barrier heights at the metal-semiconductor interface [Section 3.1]. Application of this model gives researches a means of understanding not only the effective barrier distribution at the MS interface but also its voltage dependence. With this information, the consequence that material growth and device fabrication methods have on the electrical characteristics can be better understood. To show its applicability, the new model is applied to Ru/GaN Schottky diodes annealed at increasing temperature under normal laboratory air, revealing that the origin of excess reverse leakage current is attributed to the low-side inhomogeneous barrier distribution tail [Section 3.2]. Secondly, challenges encountered during MOCVD growth of low-doped GaN drift layers for high-voltage operation are discussed with focus given to ongoing research characterizing deep-level defect incorporation by deep level transient spectroscopy (DLTS) and deep level optical spectroscopy (DLOS) [Section 3.3 and 3.4]. It is shown that simply increasing TMGa so that high growth rates (>4 µm/hr) can be achieved will cause the free carrier concentration and the electron mobilities in grown drift layers to decrease. Upon examination of the deep-level defect concentrations, it is found that this is likely caused by an increase in 4 deep level defects states located at E C - 2.30, 2.70, 2.90 and 3.20 eV. Finally, samples where the ammonia molar flow rate is increased while ensuring growth rate is kept at 2 µm/hr, the concentrations of the deep levels located at 0.62, 2.60, and 2.82 eV below the conduction band can be effectively lowered. This accomplishment marks an exciting new means by which the intrinsic impurity concentration in MOCVD-grown GaN films can be reduced so that >20 kV capable devices could be achieved. / Doctor of Philosophy / We constantly rely on electronics to help assist us in our everyday lives. However, to ensure functionality we require that they minimize the amount of energy lost through heat during operation. One contribution to this inefficiency is incurred during electrical power conversion. Examples of power conversion include converting from the 120 V wall outlet to the 5 V charging voltage used by cellphones or converting the fluctuating voltage from a solar panel (due to varying sun exposure) to the 120 V AC power found in a typical household. Electrical circuits can be simply designed to accomplish these conversions; however, consideration to every component must be given to ensure high efficiency. A popular example of an electrical power conversion circuit is one that switches the input voltage on and off at high rates and smooths the output with an inductor/capacitor network. A good analogy of this process is trying to create a small stream of water from a fire hydrant which can either be off or on at full power. Here we can use a small cup but turning the fire hydrant on and trying to fill the cup will destroy it. However, if the fire hydrant is pulsed on and off at very short intervals (1 µs), its possible to fill the cup without damaging it or having it overflow. Now, under ideal circumstances if a small hole is poked in the bottom of the cup and the interval of the fire hydrant is timed correctly, a small low power stream of water is created without overflowing the cup and wasting water. In this analogy, a devices capable of switching the stream of water on and off very fast would need to be implemented. In electrical power conversion circuits this device is typically a transistor and diode network created from a semiconducting material. Here, similar to the fire hydrant analogy, a switch would need to be capable of holding off the immense power when in the off position and not impeding the powerful flow when in the on position. The theoretical limit of these two characteristics is dependent on the material properties of the switch where typically used semiconductors include silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). Currently, GaN is considered to be a superior option over Si or SiC to make the power semiconductor switching device, however research is still required to remove non-ideal behavior that ultimately effects power conversion efficiency. In this work, we first examine the spurious behavior in GaN-based Schottky diodes and effectively create a new model to describe the observed behavior. Next, we fabricated Ru/GaN Schottky diodes annealed at different temperatures and applied the model to explain the room-temperature electrical characteristics. Finally, we grew GaN under different conditions (varying TMGa and ammonia) so that quantum characteristics, which have been shown to affect the overall ability of the device, could be measured.

Power electronics plays an important role in many energy conversion applications in modern society including consumer electronics, data centers, electric vehicles, and power grids, etc. The key components of power electronic circuits are power semiconductor devices including diodes and transistors, which determine the performance of power electronics circuits. Traditional power devices are based on the semiconductor silicon (Si), which have already reached the silicon's material limit. Gallium nitride (GaN) is a wide bandgap semiconductor with high electron mobility and high critical electric field. GaN-based power devices promise superior device performance over the Si-based counterpart. The primary design target of a unipolar power device is to achieve low on-resistance and high breakdown voltage. Although GaN high electron mobility transistor (HEMT) is commercially available in a voltage class from 15 V to 900 V, the performance of GaN devices is still far below the GaN material limit, due to several reasons: 1) To achieve the normally-off operation in a GaN HEMT, the density of two-dimensional electron gas (2DEG) channel cannot be too high; this limits the on-resistance reduction in the access region. 2) The gate capacitance of GaN HEMT is usually low so that the carrier concentration in the channel underneath the gate is relatively low, limiting the on-resistance reduction in the gated channel region. 3) The electric-field distribution in the drift region is not uniform, resulting in a limited breakdown voltage. We proposed to use the junction-based structure in GaN power devices to address the above problems and fully exploit GaN's material properties. The first part of this dissertation characterizes nickel oxide (NiO) as a p-type material to construct the junction-based GaN power devices. Although the homogenous p-GaN/n-GaN junction is preferred in many devices, the selective-area, p-GaN regrowth can lead to excessive leakage current; in comparison, the p-NiO/n-GaN junction is stable without leakage. This section describes the optimization of NiO deposition as well as the NiO characterization. Although acceptor in NiO is not generated by impurity doping, the acceptor concentration modulation is realized by tuning the O2 partial pressure during the sputtering process. Practical breakdown electric field is also characterized and confirmed to be higher than GaN. These results provide the design guidelines for NiO-GaN junction-based power devices. The second part of this dissertation demonstrates the 3D NiO-GaN junction gate to improve the GaN HEMT's on-resistance. The 3D junction gate structure enables a high carrier concentration under the gate region in the device on-state. Meanwhile, the strong depletion effect of the junction-based gate allows for a robust normally-off operation; as a result, the GaN wafer with a higher 2DEG concentration can be used to achieve both normally-off and low on-state resistance in HEMT devices. Simulation is also performed to project the performance space of trigate GaN junction HEMTs using the p-GaN instead of NiO. The third part of this dissertation presents the application of the p-GaN/n-GaN junction in the drift region of the multi-channel lateral devices to achieve the high breakdown voltage. Here p-GaN is grown in-situ with the multi-channel AlGaN/GaN structure, and there is no leakage problem. The structure is designed to achieve charge balance between the acceptor in p-GaN and the net donor in the multichannel AlGaN/GaN. This design enables a uniform electric field distribution and breakdown voltage over 10 kV. The fourth part of this dissertation presents the application of the p-NiO/n-GaN junction in vertical superjunction (SJ) devices. We show the design and simulation of this heterojunction structure in a SJ and confirm the uniform electric field and high breakdown voltage under the charge balance. Then the device fabrication is presented in detail, which mainly comprises the deep GaN trench etch, NiO self-aligned lift off, and photoresist trench planarization. The optimized device shows a trade-off between its drift region specific on-resistance versus breakdown that exceeds the 1D GaN's limit. The last part of this dissertation is exploring the design and fabrication of p-GaN/n-GaN based SJ devices. First, the challenges in p-GaN regrowth especially the introduction of interface impurities are discussed, followed by device simulation and modeling to optimize the SJ performance considering these interface impurities. The activation of regrown p-GaN in deep trenches is more difficult than planar p-GaN, and we present the characterization and physical model for the activation of the deep buried p-GaN. Last, the results of p-GaN filling regrowth and the acceptor concentration calibration in the lightly doped p-GaN are presented and discussed. In summary, our work combines experimental device fabrication and characterization, TCAD simulation, and device modeling to demonstrate the benefit of multi-dimensional, junction-based GaN power devices as compared to the traditional GaN power devices. The junction-based structure at gate region can provides stable normally-off operation and low on-resistance. When being applied to the drift region, the multidimensional junction structure can push the device specific on-resistance versus breakdown voltage trade-off near or even exceeding the material limit. These results will advance the performance and application spaces of GaN power devices. / Doctor of Philosophy / Power electronics plays an important role in many energy conversion applications in modern society including consumer electronics, data centers, electric vehicles, and power grids, etc. The key components of power electronic circuits are power semiconductor devices including diodes and transistors, which determine the performance of power electronics circuits. Traditional power devices are based on the semiconductor silicon (Si), which have already reached the silicon's material limit. Gallium nitride (GaN) is a wide bandgap semiconductor with high electron mobility and high critical electric field. GaN-based power devices promise superior device performance over the Si-based counterpart. Currently, GaN power devices performance is still far below its material limit due to several reasons: 1) To achieve normally-off operation, the carriers at gate region need to be fully depleted at zero bias. Due to a relatively limited depletion capability of the planar gate, the normally-off operation poses an upper limit on the channel carrier density, which increases the device on-resistance. 2) The electric field distribution is not uniform when the device is blocking off-state voltage, and the crowded electric field will cause the device premature breakdown. This work proposed to use multi-dimensional, p-n junction-based device structure to overcome the above challenges. The devices with diverse structures are fabricated, characterized, and compared with the commercially available devices. The multi-dimensional, junction-based gate structure provides strong electrostatic control to realize normally-off operation and allow for higher carrier concentration and lower on-resistance. The devices with multi-dimensional, junction-based drift region enables the uniform electric field distribution at the device off-state, allowing devices to block high voltage without compromising the on-state resistance. Examples of such devices investigated in this dissertation include the tri-gate junction transistors, reduced-surface-field (RESURF) diodes, and superjunction diodes. In summary, this work demonstrates the multi-dimensional, junction-based device structure to overcome the performance limitations of planar devices and fully exploit GaN's material benefits for power devices. The multi-dimensional, junction-based devices are experimentally fabricated and characterized, manifesting the superior performance over traditional GaN devices. This work will significantly boost the performance and application space of GaN power devices.

𝛼-Ga₂O₃ ist ein Halbleiter mit extrem großer Bandlücke, der als solar-blinder Ultraviolett (UV) Photodetektor eingesetzt werden kann. Seine rhomboedrische Kristallstruktur ermöglicht es Legierungen mit isostrukturellem 𝛼-Al₂O₃ und verschiedenen Übergangsmetall-Sesquioxiden wie z.B. 𝛼-Cr₂O₃ und 𝛼-V₂O₃ zu bilden. Damit kann eine Variation der Bandlücke über einen noch nie dagewesenen Spektralbereich vom Infraroten bis zum tiefen UV erreichtwerden. In der vorliegenden Arbeit wird demonstriert, wie räumlich adressierbare 𝛼-(Ga,Al,Cr,V,Ti)₂O₃ Materialbibliotheken durch kombinatorische gepulste Laserabscheidung (c-PLD) realisiert und ihre physikalischen Eigenschaften mittels anschließender Hochdurchsatzmessungen bestimmt werden können. Im ersten Teil dieser Arbeit wird die Entwicklung eines umfassenden Modells für die numerische Beschreibung der lateralen Kompositions- und Schichtdickenverteilung, die bei der c-PLD entstehen, vorgestellt. Durch Identifikation und Korrektur eines Fehlers in einem etablierten Modell zur adiabatischen Expansion des Plasmas, wird erstmals eine realistische Beschreibung von PLD-Prozessen ermöglicht und das Modell für verschiedene Materialien verifiziert. Im zweiten Teil dieser Arbeit wird das Wachstum von 𝛼-Ga₂O₃ Dünnschichten mittels PLD vorgestellt. Dazu wird ein umfassendes Phasendiagramm für das Wachstum von Ga₂O₃ auf m-Saphir erstellt, das ein ausgeprägtes Wachstumsfenster für die metastabile 𝛼-Phase mit hoher struktureller Qualität aufzeigt. Darauf basierend wurden Materialbibliotheken aus (CrₓGa₁₋ₓ)₂O₃, (VₓGa₁₋ₓ)₂O₃ und (TiₓGa₁₋ₓ)₂O₃ mit kontinuierlicher Kompositionsverteilung durch c-PLD hergestellt. Ihre physikalischen Eigenschaften wurden durch lateral aufgelöste Röntgenbeugung (XRD), energiedispersive Röntgenspektroskopie und Transmissionsmessungen erfasst. Es werden Vergleiche zwischen der gemessenen Verteilung der Zusammensetzung der Dünnschichten und dem zuvor entwickelten c-PLD-Modell erörtert, die Aufschluss über die Wachstumskinetik der verschiedenen Sesquioxide geben. Sowohl für (CrₓGa₁₋ₓ)₂O₃ als auch für (VₓGa₁₋ₓ)₂O₃ wurde das phasenreineWachstum in der rhomboedrischen 𝛼-Phase durchXRD-Messungen über den untersuchten Zusammensetzungsbereich von 0,08< x(Cr) <0,54 und 0,07 < x(V)<0,62 bestätigt. Die Absorptionsenergie der 𝛼-(VₓGa₁₋ₓ)₂O₃-Dünnfilme zeigte eine systematische Verschiebung bei steigendem x(V) von 5,3 eV auf 2,9 eV. Damit wird zum ersten Mal eine Bandlückenverschiebung hin zu niedrigeren Energien innerhalb des rhomboedrischen Sesquioxid-Material-systems über einen derart breiten Spektralbereich demonstriert. Diese Ergebnisse sind vielversprechend für mögliche Anwendungen des Materialsystems, z.B. als wellenlängenselektiver Photodetektor,:1. Introduction 2. Theoretical Background 2.1 Material Properties 2.1.1 Rhombohedral 𝛼-Ga2O3 2.1.2 Other Ga2O3 Polymorphs 2.1.3 Ternary (Me,Ga)2O3 Alloys 2.1.4 Growth mechanisms of Ga2O3 2.2 Layer Thickness Distributions for PLD Growth 2.2.1 Approaches to Layer Thickness Distributions 2.2.2 Adiabatic Plasma Plume Expansion Model for Pulsed Laser Deposition 3. Experimental Methods 3.1 Growth methods and sample preparation 3.1.1 Pulsed Laser Deposition 3.1.2 Photolithography 3.2 Characterization Techniques 3.2.1 X-Ray Diffraction 3.2.2 Spectroscopic Ellipsometry 3.2.3 Transmission Measurements 3.2.4 Atomic Force Microscopy 3.2.5 Profilometry 3.2.6 Energy-Dispersive X-Ray Spectroscopy 4. Analysis of PLD-Thickness Distributions and Applications to High-Throughput Combinatorial PLD 4.1 Analytical Description of PLD Thickness Distributions 4.2 Analysis of Lateral Thickness Distributions of Sesquioxide thin films 4.3 Modelling of combinatorial PLD for arbitrary target segmentations 5 A Novel PLD-Control Software and FAIR-Data Management 5.1 Digital Data Management 5.2 A Digital Twin for PLD 5.3 cPLD - Software 6. Growth of Phase-Pure, Highly Crystalline 𝛼-Ga2O3 Thin Films by PLD 6.1 Influence of Substrate Orientation 6.2 Influence of Growth Temperature 6.3 Influence of Layer Thickness 6.4 Comprehensive 𝑝(O2)-𝑑-𝑇g-phase diagram for PLD of Ga2O3 on m-plane sapphire 6.5 Achieving thick 𝛼-Ga2O3 layers on m-plane sapphire 6.6 Structuring 𝛼-Ga2O3 by Sacrificial ZnO Layers 6.7 High-Throughput Electrical Property Screening 6.8 Intermediate Summary 7 Ternary Alloys of 𝛼-Ga2O3 and Transition Metal Sesquioxides 7.1 Preliminary investigations of binary Cr2O3 and Ti2O3 thin films 7.2 Investigations of ternary (Ga,TM)2O3 alloys 7.2.1 Characterization of (Ga,Cr)2O3 thin films 7.2.2 Characterization of (Ga,V)2O3 thin films 7.2.3 Characterization of (Ga,Ti)2O3 thin-films 7.3 Intermediate Summary 8 Summary and Outlook 8.1 Summary 8.2 Outlook Abbreviations List of Symbols List of Electronic Lab Book References List of Own and Contributed Articles Collaborations and third-party services Supervisors Institutes Bibliography Appendix Acknowledgement / 𝛼-Ga₂O₃ is an ultra-wide bandgap semiconductor, with potential applications as a solar blind ultraviolett (UV) photodetector. Due to its rhombohedral crystal structure, alloying to isostructural 𝛼-Al₂O₃ and various transition metal sesquioxides like e.g., 𝛼-Cr₂O₃ and 𝛼-V₂O₃, enables bandgap engineering over an unprecedented large spectral range from the infrared to the deep-UV. In the present work, the realization of spatially-addressable 𝛼-(Ga,Al,Cr,V,Ti)₂O₃ material libraries by combinatorial pulsed laser deposition (c-PLD) and the subsequent high-throughput screening of their physical properties are discussed. In the first part of this thesis the development of a comprehensive model for the numerical description of lateral composition and thickness distributions arising during c-PLD are presented. An error in a well-established adiabatic plasma plume expansion model is identified and corrected, such that a real-world description of PLD processes is feasible from now on. In the second part of this thesis, the growth of 𝛼-Ga2O3 thin films by PLD is presented. Therefore, for the first time a comprehensive phase diagram for the growth of Ga2O3 on m-plane sapphire is constructed, exhibiting a distinct growth window for metastable 𝛼-Ga₂O₃ thin films with up to now unprecedented structural quality. Based on optimized process parameters, material libraries of (CrₓGa₁₋ₓ)₂O₃, (VₓGa₁₋ₓ)₂O₃ and (TiₓGa₁₋ₓ)₂O₃ with continuous composition spread were deposited by c-PLD. Their physical properties were mapped by high throughput laterally resolved X-ray diffraction, energy-dispersive X-ray spectroscopy and transmission measurements. Comparisons of the measured compositional distribution of the thin films to the c-PLD model developed earlier are discussed, revealing insight into the growth kinetics of the different sesquioxides. For both, (CrₓGa₁₋ₓ)₂O₃ and (VₓGa₁₋ₓ)₂O₃, phase-pure growth in the rhombohedral 𝛼-phase was confirmed by XRD measurements over the investigated composition range of 0. 08<𝑥(Cr) <0. 54 and 0. 07<𝑥(V) <0. 62. The absorption onset energy of the 𝛼-(VₓGa₁₋ₓ)₂O₃ thin films showed a systematic shift for increasing 𝑥(V) from 5.3 eV to 2.9 eV. With that, bandgap engineering within the rhombohedral sesquioxide material system towards lower energies over a wide spectral range is demonstrated for the first time. These results are promising for possible applications of the material system as e.g., a wavelength selective photodetector.:1. Introduction 2. Theoretical Background 2.1 Material Properties 2.1.1 Rhombohedral 𝛼-Ga2O3 2.1.2 Other Ga2O3 Polymorphs 2.1.3 Ternary (Me,Ga)2O3 Alloys 2.1.4 Growth mechanisms of Ga2O3 2.2 Layer Thickness Distributions for PLD Growth 2.2.1 Approaches to Layer Thickness Distributions 2.2.2 Adiabatic Plasma Plume Expansion Model for Pulsed Laser Deposition 3. Experimental Methods 3.1 Growth methods and sample preparation 3.1.1 Pulsed Laser Deposition 3.1.2 Photolithography 3.2 Characterization Techniques 3.2.1 X-Ray Diffraction 3.2.2 Spectroscopic Ellipsometry 3.2.3 Transmission Measurements 3.2.4 Atomic Force Microscopy 3.2.5 Profilometry 3.2.6 Energy-Dispersive X-Ray Spectroscopy 4. Analysis of PLD-Thickness Distributions and Applications to High-Throughput Combinatorial PLD 4.1 Analytical Description of PLD Thickness Distributions 4.2 Analysis of Lateral Thickness Distributions of Sesquioxide thin films 4.3 Modelling of combinatorial PLD for arbitrary target segmentations 5 A Novel PLD-Control Software and FAIR-Data Management 5.1 Digital Data Management 5.2 A Digital Twin for PLD 5.3 cPLD - Software 6. Growth of Phase-Pure, Highly Crystalline 𝛼-Ga2O3 Thin Films by PLD 6.1 Influence of Substrate Orientation 6.2 Influence of Growth Temperature 6.3 Influence of Layer Thickness 6.4 Comprehensive 𝑝(O2)-𝑑-𝑇g-phase diagram for PLD of Ga2O3 on m-plane sapphire 6.5 Achieving thick 𝛼-Ga2O3 layers on m-plane sapphire 6.6 Structuring 𝛼-Ga2O3 by Sacrificial ZnO Layers 6.7 High-Throughput Electrical Property Screening 6.8 Intermediate Summary 7 Ternary Alloys of 𝛼-Ga2O3 and Transition Metal Sesquioxides 7.1 Preliminary investigations of binary Cr2O3 and Ti2O3 thin films 7.2 Investigations of ternary (Ga,TM)2O3 alloys 7.2.1 Characterization of (Ga,Cr)2O3 thin films 7.2.2 Characterization of (Ga,V)2O3 thin films 7.2.3 Characterization of (Ga,Ti)2O3 thin-films 7.3 Intermediate Summary 8 Summary and Outlook 8.1 Summary 8.2 Outlook Abbreviations List of Symbols List of Electronic Lab Book References List of Own and Contributed Articles Collaborations and third-party services Supervisors Institutes Bibliography Appendix Acknowledgement