In recent years, amorphous oxide semiconductors have been studied due to their superior characteristics, such as transparent property, high electron mobility exceeding 10 cm2/V¡Es, and can be fabricated on plastic substrates at low temperatures. According to these advantages, a-IGZO thin-film transistors are promising as next-generation electronic devices. Although a-IGZO TFTs have such unique properties, the electrical performances are strongly dependent on its environment such as oxygen, water and visible light. In this study, the electrical characteristics of a-IGZO TFTs under positive bias stress with different ambient gases have been discussed. In particular, the total duration of the negative gate bias applied on the switching transistor is larger than that of the positive gate bias in display application. Therefore, the electrical stability under negative bias stress is vital to investigate. Moreover, a-IGZO TFT regarded as a panel switch may be exposed to visible light for the application of liquid crystal display. The electrical stability under illumination of visible light is also important to study. Experiment results show that device characteristics are affected under water-containing oxygen ambience. We indicates that the existence of water molecules can assist more oxygen to adsorb on the a-IGZO surface than the case without water assisting. That cause the variation of transfer curve under positive bias stress. However, the degradations in subthreshold swing and threshold voltage are caused by the state-related adsorption of water molecules under negative bias stress. Furthermore, adsorbed oxygen on the surface of a-IGZO can be desorbed by illumination of visible light, leading to large variation in transfer curve.

The higher mobility is needed for thin film transistor (TFT) mainly used to be applied in the larger size flat-panel displays (FPDs). The amorphous metal oxide TFT has mobility higher than 10 cm2/V¡Es and can substitute the poor mobility (<1 cm2/V¡Es) of traditional amorphous silicon TFT, which shows a great potential for the next generation. Due to the superior characteristics in amorphous metal oxide TFT, therefore, the amorphous metal oxide TFT has been studied extensively. Usually, the source/drain with island type device has a large overlapped/contact area that we cannot determine the exact electron path. That the sample of inverted stagger £\-IGZO TFTs with via type device has smaller contact area and can be estimated the electron path. In this thesis, the devices with different M1 overlaps etching stop layer (ESL) via distance, M2 £\-IGZO contact size and the fringe field effect are investigated. Although the characteristics of £\-IGZO TFTs have great performance, the electrical stability under illumination and long term bias stress are still a important issue to study before implement them into display. Thus, the devices with different structures that we mentioned previously are investigated the electrical reliability which are the negative bias stress of gate voltage, hot carrier stress effect and negative bias of illumination. The electron path of via type is extracted by contact resistance which is greater than the distance between S/D via. Experiment results show that the increased offset between M1 and ESL via generates the resistance-liked effect in electrical characteristics. The hot carrier stress effect is independent of M2 £\-IGZO contact size in short channel length devices and there are close depletion lengths in drain side. The negative bias stress of illumination is proceeded in the fringe field effect devices, which results a negative shift of threshold voltage due to the hole trapping.

Organic thin film transistors (OTFT) are a key active devices of future organic electronic circuits. The biggest advantages of organic electronics are the potential for cheep production and the enabling of new applications for light, bendable or transparent devices. These benefits are offered by a wide spectrum of various molecules and polymers that are optimized for different purpose. In this work, several interesting organic semiconductors are compared as well as transistor geometries and processing steps. In a cooperation with an industrial partner, test series of transistors are produced that are intensively characterized and used as a basis for later device simulation. Therefore, among others 4-point-probe measurements are used for a potential mapping of the transistor channel and via transfer line method the contact resistance is measured in a temperature range between 173 and 353 K. From later comparison with the simulation models, it appears that the geometrical resistance is actually more important for the transistor performance than the resistance of charge-carrier injection at the electrodes. The charge-carrier mobility is detailed evaluated and discussed. Within the observed temperature range a Arrhenius-like thermal activation of the charge- carrier transport is determined with an activation energy of 170 meV. Furthermore, a dependence of the electric field-strength of a Poole-Frenkel type is found with a Poole-Frenkel factor of about 4.9 × 10E−4 (V/m) −0.5 that is especially important for transistors with small channel length. With these two considerations, already a good agreement between device simulation and measurement data is reached. In a detailed discussion of the dependence on the charge-carrier density and from comparison with established the charge-carrier mobility models, an exponential density of states could be estimated for the organic semiconductor. However, reliability of OTFTs remains one of the most challenging hurdles to be understood and resolved for broad commercial applications. In particular, bias-stress is identified as the key instability under operation for numerous OTFT devices and interfaces. In this work, a novel approach is presented that allows controlling and significantly alleviating the bias-stress effect by using molecular doping at low concentrations. For pentacene as semiconductor and SiO2 as gate oxide, we are able to reduce the time constant of degradation by three orders of magnitude. The effect of molecular doping on the bias-stress is explained in terms of the shift of Fermi level and, thus, exponentially reduced proton generation at the pentacene/oxide interface. For transistors prepared in cooperation with the industrial partner, a second effect is observed that can be explained by a model considering a ferroelectric process in the dielectric and counteracts the bias-stress behavior.

Organic thin film transistors (OTFT) are a key active devices of future organic electronic circuits. The biggest advantages of organic electronics are the potential for cheep production and the enabling of new applications for light, bendable or transparent devices. These benefits are offered by a wide spectrum of various molecules and polymers that are optimized for different purpose. In this work, several interesting organic semiconductors are compared as well as transistor geometries and processing steps. In a cooperation with an industrial partner, test series of transistors are produced that are intensively characterized and used as a basis for later device simulation. Therefore, among others 4-point-probe measurements are used for a potential mapping of the transistor channel and via transfer line method the contact resistance is measured in a temperature range between 173 and 353 K. From later comparison with the simulation models, it appears that the geometrical resistance is actually more important for the transistor performance than the resistance of charge-carrier injection at the electrodes. The charge-carrier mobility is detailed evaluated and discussed. Within the observed temperature range a Arrhenius-like thermal activation of the charge- carrier transport is determined with an activation energy of 170 meV. Furthermore, a dependence of the electric field-strength of a Poole-Frenkel type is found with a Poole-Frenkel factor of about 4.9 × 10E−4 (V/m) −0.5 that is especially important for transistors with small channel length. With these two considerations, already a good agreement between device simulation and measurement data is reached. In a detailed discussion of the dependence on the charge-carrier density and from comparison with established the charge-carrier mobility models, an exponential density of states could be estimated for the organic semiconductor. However, reliability of OTFTs remains one of the most challenging hurdles to be understood and resolved for broad commercial applications. In particular, bias-stress is identified as the key instability under operation for numerous OTFT devices and interfaces. In this work, a novel approach is presented that allows controlling and significantly alleviating the bias-stress effect by using molecular doping at low concentrations. For pentacene as semiconductor and SiO2 as gate oxide, we are able to reduce the time constant of degradation by three orders of magnitude. The effect of molecular doping on the bias-stress is explained in terms of the shift of Fermi level and, thus, exponentially reduced proton generation at the pentacene/oxide interface. For transistors prepared in cooperation with the industrial partner, a second effect is observed that can be explained by a model considering a ferroelectric process in the dielectric and counteracts the bias-stress behavior.:1. Introduction and Motivation 10 2. Organic Semiconductors and Thin-Film Transistors 12 2.1. Fundamentals of Organic Semiconductors 12 2.1.1. Structural and Electronic Properties 12 2.1.2. Polarons and Trap States 15 2.1.3. Doping of Organic Semiconductors 16 2.2. Charge-Carrier Transport in Organic Semiconductors 18 2.2.1. Field-Effect Mobility 18 2.2.2. Gaussian Disorder Model 21 2.2.3. Variable-Range Hopping Models 24 2.2.4. Fishchuk Model 26 2.3. Organic Field-Effect Transistors 27 2.3.1. Transistor Geometry 27 2.3.2. Transistor Equations 29 2.3.3. Evaluation of Mobility 32 2.3.4. Threshold Voltage 34 2.3.5. Contact Resistance 35 2.3.6. Au-SAMs 38 2.3.7. Dielectric 39 2.3.8. Scaling and Short Channel Effects 41 2.3.9. Stability and Bias-Stress 43 2.4. Device Simulation 44 3. Materials and Methods 46 3.1. Materials 46 3.2. Sample Preparation 50 3.2.1. Sample Preparation in cooperation with the industrial partner 51 3.2.2. Sample Preparation at IAPP 52 3.2.3. Staggered Transistors at IAPP 56 3.3. Sample Characterization 57 3.3.1. Electrical Measurement Setup 57 3.3.2. Parameter Extraction 60 3.3.3. Contact Resistance 61 3.3.4. Kelvin-Probe Atomic Force Microscopy 64 3.3.5. UPS Measurement 65 4. Organic Field-Effect Transistors - Experiment and Simulation 67 4.1. Bottom-Gate Transistors 67 4.1.1. Semiconductors 67 4.1.2. Bipolar Transport 72 4.1.3. Electrode Treatments 74 4.1.4. Channel Treatments 77 4.1.5. Polymer Transistors 79 4.2. Polymer Transistors at Room Temperature 85 4.2.1. Parameter Extraction 85 4.2.2. Four-Point-Probe Measurements 90 4.2.3. Transferline Methode 96 4.2.4. UPS Measurements 100 4.3. Cryostat Measurements 102 4.3.1. Transistor Characteristics 102 4.3.2. Contact Resistance 105 4.3.3. Density of States 107 4.4. Transistor Simulation 110 4.4.1. Introduction of Device Simulation with Genius 110 4.4.2. Mesh and Geometry 111 4.4.3. Contact Resistance of Charge-Carrier Injection 112 4.4.4. Temperature Dependent Simulations 114 4.4.5. Implementation of Donor Traps 116 4.4.6. Poole-Frenkel Discussion 118 4.4.7. Contact Resistance of Geometry 122 4.4.8. Simulation with Advanced Mobility Models 123 4.5. Bias-Stress Reliability 128 4.5.1. Bias-Stress Phenomena 128 4.5.2. Doped Transistors 136 4.5.3. Polymer Transistors 145 5. Conclusion and Outlook 150 A. Appendix 154 A.1. Charge-Carrier Mobility measurements for solar cell materials 154 A.2. Simulation pictures 154 B. Bibliography 160

abstract: This thesis work mainly examined the stability and reliability issues of amorphous Indium Gallium Zinc Oxide (a-IGZO) thin film transistors under bias-illumination stress. Amorphous hydrogenated silicon has been the dominating material used in thin film transistors as a channel layer. However with the advent of modern high performance display technologies, it is required to have devices with better current carrying capability and better reproducibility. This brings the idea of new material for channel layer of these devices. Researchers have tried poly silicon materials, organic materials and amorphous mixed oxide materials as a replacement to conventional amorphous silicon layer. Due to its low price and easy manufacturing process, amorphous mixed oxide thin film transistors have become a viable option to replace the conventional ones in order to achieve high performance display circuits. But with new materials emerging, comes the challenge of reliability and stability issues associated with it. Performance measurement under bias stress and bias-illumination stress have been reported previously. This work proposes novel post processing low temperature long time annealing in optimum ambient in order to annihilate or reduce the defects and vacancies associated with amorphous material which lead to the instability or even the failure of the devices. Thin film transistors of a-IGZO has been tested for standalone illumination stress and bias-illumination stress before and after annealing. HP 4155B semiconductor parameter analyzer has been used to stress the devices and measure the output characteristics and transfer characteristics of the devices. Extra attention has been given about the effect of forming gas annealing on a-IGZO thin film. a-IGZO thin film deposited on silicon substrate has been tested for resistivity, mobility and carrier concentration before and after annealing in various ambient. Elastic Recoil Detection has been performed on the films to measure the amount of hydrogen atoms present in the film. Moreover, the circuit parameters of the thin film transistors has been extracted to verify the physical phenomenon responsible for the instability and failure of the devices. Parameters like channel resistance, carrier mobility, power factor has been extracted and variation of these parameters has been observed before and after the stress. / Dissertation/Thesis / M.S. Electrical Engineering 2013

L'objectif de ce travail de recherche est l'élaboration et l'optimisation de transistors à effet de champ organiques de type N (OTFTs). Des transistors en structure Bottom Gate Bottom Contact sont fabriqués à basse température T<120°C. Trois différentes molécules organiques conductrices d'électrons, déposées par évaporation thermiques, sont utilisées pour la couche active. Les OTFTs à base de la première molécule à corps LPP présentent de faibles mobilités à effet de champ de l'ordre de 10-5cm2/V.s. L'étude d'optimisation menée sur les conditions de dépôt de cette dernière n'a pas permis d'améliorer ses performances électriques. L'étude de stabilité électrique ''Gate Bias Stress'' a mis en évidence les instabilités de cette molécule. Les OTFTs à base des deux dérivés indénofluorènes (IF) possèdent des mobilités plus importantes. Dans les conditions optimales la molécule IF(CN2)2 méta permet d'atteindre une mobilité d'effet de champ µFE=2.1x10-4 cm2/V, alors que la molécule IF(CN2)2 para permet d'obtenir des mobilités µFE=1x10-2cm2/V.s après recuit. L'étude de stabilité électrique a mis en évidence une meilleure stabilité des OTFTs à base de IF(CN2)2 para. Une étude des phénomènes de transport de charges est menée pour les deux types de molécules. Les OTFTs de type N réalisés sont utilisés pour la réalisation d'un circuit logique de type inverseur pseudo-CMOS. Finalement, ce procédé basse température nous a permis de réaliser des OTFTs sur substrat flexible. / The main goal of this present work consists in the fabrication and optimization of N type organic field effect transistors. Bottom Gate Bottom Contact transistors are performed at low temperature T<120°C. Three different electro-deficient organic molecules are thermally evaporated and used as active layer. OTFTs based on LPP core molecule present low field effect mobility around 10-5cm2/V.s. The optimization study investigated on deposition parameters of this molecule on OTFTs performances does not allow improving this mobility. Moreover gate bias stress measurements reveal important instabilities related to this molecule. Indenfluorene derivatives core (IF) based OTFTs show better performances. Field effect mobility µFE=2.1x10-4 cm2/V is reached using IF(CN2)2 meta in optimized deposition conditions and µFE=1x10-2 cm2/V.s is obtained using IF(CN2)2 para after annealing treatment. The investigated gate bias stress study highlights the good electrical stability of IF(CN2)2 para based OTFTs. Temperature measurements allow us studying the charge transport phenomenon in these indenofluorene derivatives. Fabricated N-type OTFTs are used to perform a first electronic circuit that consists in a logic gate (invertor).Finally this low temperature process led us to achieve OTFTs devices on flexible substrates (PEN).

Silicon Carbide, a wide band gap (WBG) semiconductor, has pushed electrical limits beyond Silicon (Si) when it comes to power electronics. It has offered the electrification of society showing promise for a greener future. However, owing to higher material defects, particularly at the oxide/semiconductor interface, threshold voltage (VTH) instability has been a persistent problem. This thesis examines the drift in VTH when a bipolar ac gate bias stress is applied to 4H-SiC MOSFETs. For this purpose, a gate stress setup using a gate driver IC is created. This is followed by a measure-stress-measure (MSM) sequence at varying gate voltages to study the effects of VGS,on, VGS,off, and voltage overshoots on the drift. Two critical VGS,off biases are found. The drift is negligible until the first critical point, accelerated, between the first and second bias, and decelerated beyond the second point with degradation of the oxide. Overshoots/undershoots in the gate drive loop shows an excess drift of 37.77% with only undershoots contributing entirely to this percentage. Drift at higher temperature is smaller than at room temperature but with changing slope. After 400 hours of stress at +18/ − 8V, a VTH drift of 17.5% while a RDS,on drift of only 2.5 % is measured. End of life VTH for devices in this thesis show a drift of 280mV at the automotive application switching limit and 500mV at the solar applications switching limit. The findings are intended for better understanding of device performance limits at high switching cycles and voltage biases. / Bredbandgapsmaterialet kiselkarbid har utvidgat gränserna för kraftelektronikens elektriska prestanda jämfört med vad som går att åstadkomma med kisel. Kiselkarbiden har gett nya möjligheter för samhällets elektrifiering vilket är lovande för en grön framtid. På grund av materialdefekter speciellt vid gränsytan mellan kiselkarbid (SiC) och kiseldioxid har det varit ett bestående problem med drivande tröskelspänning. Det här examensarbetet undersöker drift för tröskelspänningen då gate-terminalen i en 4H-SiC MOSFET utsätts för en bipolär alternerande spännings-stress. För detta ändamål har en mätuppställning med en IC-krets för gate-styrning byggts upp. Detta följs av en mät-stress-mät sekvens för varierande gate-source spänningar (VGS) för att studera effekter av VGS,on,VGS,off och spännings-överslängar på tröskelspänningsdriften. Två kritiska nivåer för VGS,off har påvisats. Tröskelspänningsdriften är försumbar före den första nivån, accelererad mellan den första och andra nivån, och retarderad efter den andra nivån med degradering av gate-oxiden. För överslängar och underslängar i gate-spänningen syns en extra tröskelspänningsdrift på 37.77 % där enbart underslängarna bidrar till driften. Tröskelspänningsdriften vid högre temperatur är mindre än vid rumstemperatur men med förändrad lutning för subtröskelspänningskarakteristiken. Efter 400 timmars stress med +18V/-8V, uppmättes en tröskelspänningsdrift på 17.5 % men endast 2.5 % drift för on-resistansen. Vid slutet av förväntad livstid i form av switch-cykler uppmättes 280 mV drift för biltillämpningar och 500 mV för solpanelstillämpningar. Resultaten är ämnade att förbättra förståelsen för komponentprestandans begränsningar efter ett stort antal switch-cykler och olika gate-source spänningar.

Nanostructured ZnO films were obtained via thermal oxidation of thin films formed with metallic Zn-nanoparticle dispersions. Commercial zinc nanoparticles used for this work were characterized by microscopic and thermal analysis methods to analyze the Zn-ZnO core shell structure, surface morphology and oxidation characteristics. These dispersions were spin-coated on SiO₂/Si substrates and then annealed in air between 100 and 600 °C. Significant nanostructural changes were observed for the resulting films, particularly those from larger Zn nanoparticles. These nanostructures, including nanoneedles and nanorods, were likely formed due to fracturing of ZnO outer shell due to differential thermal expansion between the Zn core and the ZnO shell. At temperatures above 227 °C, the metallic Zn has a high vapor pressure leading to high mass transport through these defects. Ultimately the Zn vapor rapidly oxidizes in air to form the ZnO nanostructures. We have found that the resulting films annealed above 400 °C had high electrical resistivity. The zinc nanoparticles were incorporated into zinc indium oxide solution and spin-coated to form thin film transistor (TFT) test structures to evaluate the potential of forming nanostructured field effect sensors using simple solution processing. The functionalization of zinc tin oxide (ZTO) films with self-assembled monolayers (SAMs) of n-hexylphosphonic acid (n-HPA) was investigated. The n-HPA modified ZTO surfaces were characterized using contact angle measurement, x-ray photoelectron spectroscopy (XPS) and electrical measurements. High contact angles were obtained suggesting high surface coverage of n-HPA on the ZTO films, which was also confirmed using XPS. The impact of n-HPA functionalization on the stability of ZTO TFTs was investigated. The n-HPA functionalized ZTO TFTs were either measured directly after drying or after post-annealing at 140 °C for 48 hours in flowing nitrogen. Their electrical characteristics were compared with that of non-functionalized ZTO reference TFTs fabricated using identical conditions. We found that the non-functionalized devices had a significant turn-on voltage (V[subscript ON]) shift of ~0.9 V and ~1.5 V for the non-annealed and the post-annealed conditions under positive gate bias stress for 10,000 seconds. The n-HPA modified devices showed very minimal shift in V[subscript ON] (0.1 V), regardless of post-thermal treatment. The VON instabilities were attributed to the interaction of species from the ambient atmosphere with the exposed ZTO back channel during gate voltage stress. These species can either accept or donate electrons resulting in changes in the channel conductance with respect to the applied stress. / Graduation date: 2012 / Access restricted to the OSU Community at author's request from Jan. 6, 2012 - Jan. 6, 2013

Les technologies de transistors bipolaires à hétérojonctions (HBT) ont montré leur efficacité pour permettre aux circuits de traiter les grands signaux au delà de 100Gbit/s pour les réseaux optiques Ethernet. Pour assurer ce résultat, une bonne fiabilité doit être garantie. Des tests de vieillissements accélérés sous contraintes thermiques et électrothermiques sont réalisés et analysés avec les outils de simulation physique Sentaurus TCAD afin d’obtenir les lois de vieillissement physiques. Le modèle compact HICUM niveau 2, basé sur la physique, est utilisé pour modéliser précisément le composant avant vieillissement, puis pour ajuster les caractéristiques intermédiaires pendant le vieillissement. L’évolution des paramètres du modèle est décrit avec des équations appropriées pour obtenir un modèle électrique compact du vieillissement basé sur la physique. Les lois de vieillissement et les équations d’évolutions des paramètres avec le temps de contrainte sont implantées dans le modèle électrique de vieillissement en langage Verilog-A, ce qui permet de simuler l’impact des mécanismes de défaillances sur le circuit en conditions opérationnelles. / Modern InP Heterojunction Bipolar Transistors (HBT) technology has shown its efficiency for making large signal ICs working above 100 Gbits/s for Ethernet optical transport network. To full-fill this expectation, a good reliability has to be assured. Accelerated aging tests under thermal and electro-thermal stress conditions are performed and analyzed with Sentaurus TCAD device simulation tools to achieve the physical aging laws. The physics based advanced bipolar compact model HICUM Level 2 is used for precise modeling of the devices before aging. The HICUM parameters are extracted to fit the intermediate characterizations during aging. The evolution of the model parameters is described with suitable equations to achieve a physics based compact electrical aging model. The aging laws and the parameter evolution equations with stress time are implemented in compact electrical aging model in Verilog-A languages which allows us to simulate the impact of device failure mechanisms on the circuit in operating conditions.