O mercado de sistemas embarcados tem demandado uma variada gama de aplicações, aplicações estas cada vez mais complexas. Para atender tal demanda, visto o declínio da lei de Moore e os processadores chegando ao seu limite de dissipação térmica, os projetistas são pressionados a desenvolverem novas organizações computacionais. Para manter a compatibilidade binária, de forma que a grande quantidade de aplicativos e ferramentas já desenvolvidas possa ser reutilizada, as empresas desenvolvem seus produtos focando em melhorias de um dado processador que irá executar a mesma ISA (Instruction Set Architecture). Essa necessidade de compatibilidade de código impõe muitas restrições à equipe de projeto, haja vista as limitações impostas pela ISA legada. A Tradução Binária (TB) abre novas possibilidades aos projetistas, visto que permite a execução de códigos previamente compilados para uma determinada arquitetura em outra arquitetura. No entanto, a TB acrescenta mais uma camada entre o código e sua execução, trazendo perdas de desempenho. Este trabalho explora um novo mecanismo de tradução binária dinâmico de dois níveis que, ao trocar o primeiro nível, pode executar ISAs diferentes de forma totalmente transparente e ainda amortiza os custos de tradução. Da mesma forma ao trocar o segundo nível de tradução binária pode-se trocar a arquitetura alvo. Com base nesse tradutor de dois níveis, é apresentado como estudo de caso um sistema computacional composto por uma arquitetura reconfigurável capaz de executar códigos x86, ARM, PowerPC e MIPS de forma transparente, com compatibilidade binária e com ganhos de desempenho. / The embedded systems market is demanding a wide range of applications, and these applications are increasing in complexity. In order to meet this demand, since the decline of Moore’s law and processors reaching their thermal dissipation limits, designers are pushed to develop new computer organizations. In order to support binary compatibility, so that the large quantity of applications and tools already deployed can be reused, companies develop their products focusing on improvement of a given processor that will execute the same ISA (Instruction Set Architecture) as before. This need for code compatibility impose a lot of restrictions to the design team, considering the limitations imposed by the legacy ISA. Binary Translation (BT) open new possibilities for designers, since it allows the execution of a code previously compiled to a specific architecture in another architecture. However, BT adds another layer between code and actual execution, therefore bringing performance penalties. This work explores a dynamic two-level binary translation system that, by changing the first BT level, allows the execution of different ISAs in a transparent fashion and still amortizes translation costs. In the same way, it is possible to switch to another target architecture by only changing the second BT level. Based on this two-level translator this work presents, as a case study, a computational architecture comprising of an dynamic reconfigurable array that can execute x86, ARM, PowerPC and MIPS binary codes in a transparent way, maintaining binary compatibility with performance gains.

O mercado de sistemas embarcados tem demandado uma variada gama de aplicações, aplicações estas cada vez mais complexas. Para atender tal demanda, visto o declínio da lei de Moore e os processadores chegando ao seu limite de dissipação térmica, os projetistas são pressionados a desenvolverem novas organizações computacionais. Para manter a compatibilidade binária, de forma que a grande quantidade de aplicativos e ferramentas já desenvolvidas possa ser reutilizada, as empresas desenvolvem seus produtos focando em melhorias de um dado processador que irá executar a mesma ISA (Instruction Set Architecture). Essa necessidade de compatibilidade de código impõe muitas restrições à equipe de projeto, haja vista as limitações impostas pela ISA legada. A Tradução Binária (TB) abre novas possibilidades aos projetistas, visto que permite a execução de códigos previamente compilados para uma determinada arquitetura em outra arquitetura. No entanto, a TB acrescenta mais uma camada entre o código e sua execução, trazendo perdas de desempenho. Este trabalho explora um novo mecanismo de tradução binária dinâmico de dois níveis que, ao trocar o primeiro nível, pode executar ISAs diferentes de forma totalmente transparente e ainda amortiza os custos de tradução. Da mesma forma ao trocar o segundo nível de tradução binária pode-se trocar a arquitetura alvo. Com base nesse tradutor de dois níveis, é apresentado como estudo de caso um sistema computacional composto por uma arquitetura reconfigurável capaz de executar códigos x86, ARM, PowerPC e MIPS de forma transparente, com compatibilidade binária e com ganhos de desempenho. / The embedded systems market is demanding a wide range of applications, and these applications are increasing in complexity. In order to meet this demand, since the decline of Moore’s law and processors reaching their thermal dissipation limits, designers are pushed to develop new computer organizations. In order to support binary compatibility, so that the large quantity of applications and tools already deployed can be reused, companies develop their products focusing on improvement of a given processor that will execute the same ISA (Instruction Set Architecture) as before. This need for code compatibility impose a lot of restrictions to the design team, considering the limitations imposed by the legacy ISA. Binary Translation (BT) open new possibilities for designers, since it allows the execution of a code previously compiled to a specific architecture in another architecture. However, BT adds another layer between code and actual execution, therefore bringing performance penalties. This work explores a dynamic two-level binary translation system that, by changing the first BT level, allows the execution of different ISAs in a transparent fashion and still amortizes translation costs. In the same way, it is possible to switch to another target architecture by only changing the second BT level. Based on this two-level translator this work presents, as a case study, a computational architecture comprising of an dynamic reconfigurable array that can execute x86, ARM, PowerPC and MIPS binary codes in a transparent way, maintaining binary compatibility with performance gains.

Orientador: Edson Borin / Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Computação / Made available in DSpace on 2018-08-25T09:40:30Z (GMT). No. of bitstreams: 1 Gomes_GabrielFerreiraTeles_M.pdf: 1568441 bytes, checksum: b0b5fb8e25907bd153706a27a9b597ea (MD5) Previous issue date: 2014 / Resumo: Tradução dinâmica de binários é uma técnica de emulação comumente utilizada na implementação de máquinas virtuais. Neste contexto, a emulação de saltos indiretos é uma das principais fontes de perda de eficiência, o que atrapalha a aplicabilidade de tradutores dinâmicos de binários. Essa dissertação descreve diversas técnicas que tentam melhorar o desempenho e a eficiência da emulação de saltos indiretos em máquinas virtuais eficientes. O DynamoRIO é uma máquina virtual que se enquadra nessa categoria e que utiliza características de diversas dessas técnicas. Nessa dissertação, nós apresentamos a implementação atual do DynamoRIO, modificamos seu código para incluir duas novas técnicas de emulação de saltos indiretos (Inline Caching e IBTC) e as comparamos com outras técnicas descritas na literatura / Abstract: Dynamic binary translation is an emulation technique commonly employed in the implementation of virtual machines. One of the main sources of overhead that hinder the applicability of dynamic binary translators is that caused by the emulation of indirect branch instructions. This master thesis describes several techniques that try to improve the performance and efficiency of indirect branch emulation in efficient virtual machines. DynamoRIO is one of such machines and it implements features used by several of those techniques. In this master thesis, we present current implementations of DynamoRIO, modify its code to include two new techniques (Inline Caching and IBTC) and compare it with other techniques described in the literature / Mestrado / Ciência da Computação / Mestre em Ciência da Computação

Binary recompilation and translation play an important role in computer systems today. It is used by systems such as Java and .NET, and system emulators like VMWare and VirtualPC. A dynamic binary translator have several things in common with a regular compiler but as they usually have to translate code in real-time several constraints have to be made, especially when it comes to making code optimisations. Designing a dynamic recompiler is a complex process that involves repetitive tasks. Translation tables have to be constructed for the source architecture which contains the data necessary to translate each instruction into binary code that can be executed on the target architecture. This report presents a method that allows a developer to specify how the source and target architectures work using a set of scripting languages. The purpose of these languages is to relocate the repetitive tasks to computer software, so that they do not have to be performed manually by programmers. At the end of the report a simple benchmark is used to evaluate the performance of a basic IA32 emulator running on a PowerPC target that have been implemented using the system described here. The results of the benchmark is compared to the results of running the same benchmark on other, existing, emulators in order to show that the system presented here can compete with the existing methods used today. Several ongoing research projects are looking into ways of designing binary translators. Most of these projects focus on ways of optimising code in real-time and how to solve the problems related to binary translation, such as handling self-modifying code.

As computer systems become increasingly complex and diverse, so too do the architectures they implement. This leads to an increase in complexity in the tools used to design new hardware and software. One particularly important tool in hardware and software design is the Instruction Set Simulator, which is used to prototype new architectures and hardware features, verify hardware, and test and debug software. Many Architecture Description Languages exist which facilitate the description of new architectural or hardware features, and generate a tools such as simulators. However, these typically suffer from poor performance, are difficult to test effectively, and may be limited in functionality. This thesis considers three objectives when developing Instruction Set Simulators: performance, correctness, and completeness, and presents techniques which contribute to each of these. Performance is obtained by combining Dynamic Binary Translation techniques with a novel analysis of high level architecture descriptions. This makes use of partial evaluation techniques in order to both improve the translation system, and to improve the quality of the translated code, leading a performance improvement of over 2.5x compared to a naïve implementation. This thesis also presents techniques which contribute to the correctness objective. Each possible behaviour of each described instruction is used to guide the generation of a test case. Constraint satisfaction techniques are used to determine the necessary instruction encoding and context for each behaviour to be produced. It is shown that this is a significant improvement over benchmark-driven testing, and this technique has led to the discovery of several bugs and inconsistencies in multiple state of the art instruction set simulators. Finally, several challenges in ‘Full System’ simulation are addressed, contributing to both the performance and completeness objectives. Full System simulation generally carries significant performance costs compared with other simulation strategies. Crucially, instructions which access memory require virtual to physical address translation and can now cause exceptions. Both of these processes must be correctly and efficiently handled by the simulator. This thesis presents novel techniques to address this issue which provide up to a 1.65x speedup over a state of the art solution.

Dans cette thèse nous nous intéressons à l'accélération des accès mémoire dans la traduction binaire dynamique.Pour cela, nous nous basons sur des méthodes dont la principale finalité est de gérer l'espace mémoire de la cible avec le matériel de l'hôte.Deux grandes méthodes pour cela ont été exploré, l'une basé sur la support matériel à la virtualisation, et l'autre sur un module Linux.Dans le cas du support matériel à la virtualisation, nous avons utilisé le simulateur comme un invité spécifique.Celui ci jouant un rôle analogue à celui d'un OS, en plus de son rôle de simulateur, pour la cible.En particulier il se charge de lui créer un espace d'adressage enchevêtré, qui puisse être utiliser directement, sans simulation logicielle de la gestion de la mémoire virtuelle.Dans le cas de la méthode basée sur un module Linux, les mêmes finalités sont poursuivi.Mais le simulateur continue de fonctionner comme un processus normal.En revanche, il possède désormais un module compagnon, avec lequel il peut communiquer au travers d'ioctl.Ce module est chargé de manipuler la gestion de la mémoire virtuelle de l'hôte et ce afin de créer un espace d'adressage enchevêtré pour la cible.Ces méthodes ont été implémenté dans Qemu et Linux et mène à des gains de performances significatifs. / In this thesis we are interested in the acceleration of memory accesses in dynamic binary translation.For this, we base ourselves on methods whose main purpose is to manage the target's address space with the host's hardware.Two main methods for this have been explored, one based on hardware assisted virtualization, and the other on a Linux module.In the case of hardware assisted virtualization, we used the simulator as a specific guest.This one playing a role similar to that of an OS, in addition to its role of simulator, for the target.In particular, it is responsible for creating an enmbedded address space that can be used directly, without software simulation of an MMU.In the case of a method based on a Linux module, the same purpose is pursued.But the simulator continues to operate as a normal process.On the other hand, it now has a companion module, with which it can communicate through ioctl.This module is responsible for manipulating the host's virtual memory management to create an embedded address space for the target.These methods have been implemented in Qemu and Linux and lead to significant performance gains.

Cette thèse porte sur l’utilisation de techniques d’accélération matérielle pour la conception de processeurs basés sur l’optimisation dynamique de binaires. Dans ce type de machine, les instructions du programme exécuté par le processeur sont traduites et optimisées à la volée par un outil de compilation dynamique intégré au processeur. Ce procédé permet de mieux exploiter les ressources du processeur cible, mais est délicate à exploiter car le temps de cette recompilation impacte de manière très significative l’effet global de ces optimisations. Dans cette thèse, nous montrons que l’utilisation d’accélérateurs matériels pour certaines étapes clés de cette compilation (construction de la représentation intermédiaire, ordonnancement des instructions), permet de ramener le temps de compilation à des valeurs très faible (en moyenne 6 cycles par instruction, contre plusieurs centaines dans le cas d’une mise en œuvre classique). Nous avons également montré comment ces techniques peuvent être exploitées pour offrir de meilleurs compromis performance/consommation sur certains types de noyaux de calculs. La thèse à également débouché sur la mise à disposition de la communauté de recherche du compilateur développé. / This thesis is focused on the hardware acceleration of processors based on Dynamic Binary Translation. Such architectures execute binaries by translating and optimizing each instruction at run-time, thanks to a DBT toolchain embedded in the system. This process leads to a better ressource utilization but also induces execution time overheads, which affect the overall performances. During this thesis, we've shown that the use of hardware components to accelerate critical parts of the DBT process (First translation, generation of an intermediate representation and instruction scheduling) drastically reduce the compilation time (around 6 cycles to schedule one instruction, against several hundreds for a fully-software DBT). We've also demonstrated that the proposed approach enables several continuous optimizations flow, which offers better energy/performance trade-offs. Finally, the DBT toolchain is open-source and available online.

Orientador: Guido Costa Souza de Araujo / Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Computação / Made available in DSpace on 2018-08-11T00:36:00Z (GMT). No. of bitstreams: 1 Souza_MaxwellMonteiroAndradede_M.pdf: 1735414 bytes, checksum: 76715c4172c656603702b765b56a679f (MD5) Previous issue date: 2008 / Resumo: Tradução binária dinâmica consiste em permitir que programas originalmente compilados para uma determinada arquitetura, executem sobre um nova arquitetura sem a necessidade de recompilação. Esta técnica pode ser usada como ferramenta de migração de aplicações entre arquiteturas ou até mesmo para permitir que uma aplicação execute sobre várias arquiteturas de forma transparente. A tradução binária dinâmica também permite que otimizações, não possíveis em tempo de compilação, sejam feitas em tempo de execução. ISAMAP é um sistema de tradução binária orientado a especificações de mapeamento de instruções entre um Conjunto de Instruções (ISA) origem e um ISA alvo. Em ISAMAP seqüências de instruções da ISA alvo são associadas á instruções da ISA origem, permitindo um mapeamento rápido e otimizado. Atualmente o ISAMAP realiza tradução binária de código PowerPC 32 para código x86 / Abstract: The main role of Dynamic Binary Translation is the capability of running applications compiled for a specific architecture over a totally diferent one without sources recompiling. This technique can be used neither in legacy code migration or in a transparent run-time environment to run applications of different arquitectures. Dynamic Binary Translation also offers otimizations possibilities once informations about application run-time behaviour are available. The ISAMAP is a mapping instructions driven dynamic binary translation system that makes able a mapping between two differents arquitectures. Instructions sequence of the source ISA are mapped to target ISA instructions, providing a fast and optimized mapping. In the current state ISAMAP translates PowerPC 32 binary code to x86 binary / Mestrado / Geração Dinamica de Codigo / Mestre em Ciência da Computação

I dagens informationssamhälle pågår en växande trend av molnbaserade tjänster. Vid implementering av molnbaserade tjänster används metoden Virtualisering. Denna metod minskar behovet av antal fysiska datorsystem i ett datacenter. Vilket har en positiv miljöpåverkan eftersom energikonsumtionen minskar när hårdvaruresurser kan utnyttjas till sin fulla kapacitet. Molnbaserade tjänster skapar samhällsnytta då nya aktörer utan teknisk bakgrundskunskap snabbt kan komma igång med verksamhetsberoende tjänster. För tillämpning av Virtualisering används en så kallad Hypervisor vars uppgift är att distribuera molnbaserade tjänster. Efter utvärdering av vetenskapliga studier har vi funnit att det finns skillnader i prestanda och funktionalitet mellan olika Hypervisors. Därför väljer vi att göra en prestanda- samt funktionsanalys av Hypervisors som kommer från de största aktörerna på marknaden. Dessa är Microsoft Hyper-V Core Server 2012, Vmware ESXi 5.1.0 och Citrix XenServer 6.1.0 Free edition. Vår uppdragsgivare är försvarsmakten som bekräftade en stor efterfrågan av vår undersökning. Rapporten innefattar en teoretisk grund som beskriver tekniker bakom virtualisering och applicerbara användningsområden. Genomförandet består av två huvudsakliga metoder, en kvalitativ- respektive kvantitativ del. Grunden till den kvantitativa delen utgörs av ett standardsystem som fastställdes utifrån varje Hypervisors begränsningar. På detta standardsystem utfördes prestandatester i form av dataöverföringar med en serie automatiserade testverktyg. Syftet med testverktygen var att simulera datalaster som avsiktligt påverkade CPU och I/O för att avgöra vilka prestandaskillnader som förekommer mellan Hypervisors. Den kvalitativa undersökningen omfattade en utredning av funktionaliteter och begränsningar som varje Hypervisor tillämpar. Med tillämpning av empirisk analys av de kvantitativa mätresultaten kunde vi fastställa orsaken bakom varje Hypervisors prestanda. Resultaten visade att det fanns en korrelation mellan hur väl en Hypervisor presterat och vilken typ av dataöverföring som den utsätts för. Den Hypervisor som uppvisade goda prestandaresultat i samtliga dataöverföringar är ESXi. Resultaten av den kvalitativa undersökningen visade att den Hypervisor som offererade mest funktionalitet och minst begränsningar är Hyper-V. Slutsatsen blev att ett mindre datacenter som inte planerar en expansion bör lämpligtvis välja ESXi. Ett större datacenter som både har behov av funktioner som gynnar molnbaserade tjänster och mer hårdvaruresurser bör välja Hyper-V vid implementation av molntjänster. / A growing trend of cloud-based services can be witnessed in todays information society. To implement cloud-based services a method called virtualization is used. This method reduces the need of physical computer systems in a datacenter and facilitates a sustainable environmental and economical development. Cloud-based services create societal benefits by allowing new operators to quickly launch business-dependent services. Virtualization is applied by a so-called Hypervisor whose task is to distribute cloud-based services. After evaluation of existing scientific studies, we have found that there exists a discernible difference in performance and functionality between different varieties of Hypervisors. We have chosen to perform a functional and performance analysis of Hypervisors from the manufacturers with the largest market share. These are Microsoft Hyper-V Core Server 2012, Vmware ESXi 5.1.0 and Citrix XenServer 6.1.0 Free edition. Our client, the Swedish armed forces, have expressed a great need of the research which we have conducted. The thesis consists of a theoretical base which describes techniques behind virtualization and its applicable fields. Implementation comprises of two main methods, a qualitative and a quantitative research. The basis of the quantitative investigation consists of a standard test system which has been defined by the limitations of each Hypervisor. The system was used for a series of performance tests, where data transfers were initiated and sampled by automated testing tools. The purpose of the testing tools was to simulate workloads which deliberately affected CPU and I/O to determine the performance differences between Hypervisors. The qualitative method comprised of an assessment of functionalities and limitations for each Hypervisor. By using empirical analysis of the quantitative measurements we were able to determine the cause of each Hypervisors performance. The results revealed that there was a correlation between Hypervisor performance and the specific data transfer it was exposed to. The Hypervisor which exhibited good performance results in all data transfers was ESXi. The findings in the qualitative research revealed that the Hypervisor which offered the most functionality and least amount of constraints was Hyper-V. The conclusion of the overall results uncovered that ESXi is most suitable for smaller datacenters which do not intend to expand their operations. However a larger datacenter which is in need of cloud service oriented functionalities and requires greater hardware resources should choose Hyper-V at implementation of cloud-based services.