The technological development is enabling the production of increasingly complex electronic systems. All such systems must be verified and tested to guarantee their correct behavior. As the complexity grows, testing has become one of the most significant factors that contribute to the total development cost. In recent years, we have also witnessed the inadequacy of the established testing methods, most of which are based on low-level representations of the hardware circuits. Therefore, more work has to be done at abstraction levels higher than the classical gate and register-transfer levels. At the same time, the automatic test equipment based solutions have failed to deliver the required test quality. As a result, alternative testing methods have been studied, which has led to the development of built-in self-test (BIST) techniques. In this thesis, we present a novel hybrid BIST technique that addresses several areas where classical BIST methods have shortcomings. The technique makes use of both pseudorandom and deterministic testing methods, and is devised in particular for testing modern systems-on-chip. One of the main contributions of this thesis is a set of optimization methods to reduce the hybrid test cost while not sacrificing test quality. We have devel oped several optimization algorithms for different hybrid BIST architectures and design constraints. In addition, we have developed hybrid BIST scheduling methods for an abort-on-first-fail strategy, and proposed a method for energy reduction for hybrid BIST. Devising an efficient BIST approach requires different design modifications, such as insertion of scan paths as well as test pattern generators and signature analyzers. These modifications require careful testability analysis of the original design. In the latter part of this thesis, we propose a novel hierarchical test generation algorithm that can be used not only for manufacturing tests but also for testability analysis. We have also investigated the possibilities of generating test vectors at the early stages of the design cycle, starting directly from the behavioral description and with limited knowledge about the final implementation. Experiments, based on benchmark examples and industrial designs, have been carried out to demonstrate the usefulness and efficiency of the proposed methodologies and techniques.

The goal of this work is to understand types of defects in semiconductor memories and algorithms for their testing. In the second part the work describes design and implementation of programmable BIST controller with small digital block size requirments.

Ce mémoire présente une technique de BIST dont l'interface est totalement numérique, pour le test fréquentiel de circuits analogiques et mixtes. L'objectif de cette approche est de faciliter les techniques de test à bas coût des Systèmes sur Puce, rendant le test des blocs mixtes compatibles avec l'utilisation de testeurs numériques. La génération de signal de test analogique est réalisée sur la puce elle-même par un filtrage passe-bas d'un train binaire encodé par un modulateur Sigma-Delta. L'analyse harmonique de la réponse analogique est également réalisée sur la puce en utilisant une modulation par un signal carré et une modulation par un modulateur Sigma-Delta. La génération de signal analogique et l'analyse de la réponse de test étant programmables numériquement sur la puce, la compatibilité avec un testeur numérique à faible coût est assurée. L'optimisation des signatures de test est discutée en détail pour trouver un compromis entre temps et qualité du test.

Le coût et le temps de test élevés des testeurs RadioFréquences (RF) poussent à l'optimisation de test, voir même à des méthodes alternatives de test pour les circuits analogiques-mixtes RF. Jusqu'à présent, le test des circuits RF était effectué par la validation des spécifications fonctionnelles du circuit. Cependant, à cause des contraintes imposées par les fréquences en jeu de plus en plus élevées et par des temps de test les plus réduits possible, la mesure de certaines spécifications fonctionnelles, même sur testeurs dédiés, n'est plus faisable. Il est ainsi nécessaire de développer de nouvelles méthodes de test permettant de répondre à ces besoins. Cette thèse a pour objectif de commencer le développement d'un bouquet des circuits de test sur puce de type BIST (Built-In Self Test) le plus général possible pour les circuits RF afin de supporter l'étape de conception et d'optimiser le test de production. La validation de ces circuits de BIST est orientée défaut. Le développement de la stratégie de validation d'un circuit de BIST se base sur les points suivants : choix des mesures de test avec simulation du circuit sous test ; modélisation des mesures de test et de spécifications du circuit sous test a travers simulations Monte-Carlo ; génération d'une population statistiquement plus représentative a travers la théorie des Copules ; génération d'une liste de fautes qui peuvent se produire dans le circuits sous test ; simulations d'injection de fautes ; analyse des métriques de test telles que le taux de couverture, le taux de circuits défaillants qui passent le test (defect level) et le rejet de circuits fonctionnels par le test (yield loss). Ces travaux ont été menés sur un cas d'étude industriel de type synthétiseur de fréquence, PLL (Phase-Locked Loop), conçu à STMicroelectronics.

The cost to test chips has risen tremendously. Additionally, the process for testing all functionalities of both analog and digital part is far from simple. One attractive option is moving some or all of the testing functions onto the chip itself leading to the use of built-in self-tests (BISTs). The frequency generator or frequency synthesizer is a key element of the BIST. It generates the clock frequencies needed for testing. A wide-band frequency synthesizer is designed in the project. The architecture of a PLL is analyzed as well as the modifications carried out. The modified structure has three blocks: basic PLL based frequency synthesizer, frequency down-converter, and output selector. Each of these blocks is analyzed and designed. This frequency synthesizer system overcomes challenges faced by the traditional PLL based frequency synthesizer.

The expanding wireless market has resulted in complex integrated transceivers that involve RF, analog and mixed-signal circuits, resulting in expensive and complicated testing. The most important challenges that test engineering faces today are (1) providing a fast and accurate fault-diagnosis and performance characterization so as to accelerate the time-to-market and (2) providing an inexpensive test strategy that can be integrated with the design so as to aid the high-volume manufacturing process. The first part of the research focuses on the design of an RMS detector for built-in-self-test (BIST) of an RF integrated transceiver that can directly provide information at various test points in the design. A cascode low noise amplifier (LNA) has been chosen as the device under test (DUT). A compact (< 0.031 mm2) RF RMS detector with negligible input capacitance (< 13 fF) has been implemented in 0.35 µm CMOS technology along with the DUT. Experimental results are currently being assimilated and compared with the simulation results. Frequency limitations were encountered during the testing process due to unexpected increase in the value of the N-well resistors. All other problems faced during the testing, as well as the results obtained so far, are presented in this thesis. In the second part of the research, the use of the RMS detector for BIST has been extended to a continuous-time high-frequency boost-filter. The proposed HF RMS detector has been implemented along with a 24 dB 350 MHz boost filter as the DUT on 0.35 µm CMOS technology. The HF RMS detector occupies 0.07 mm2 and has an input capacitance of 7 fF. The HF RMS detector has a dynamic range greater than 24 dB starting from -38 dBm of input power. The bandwidth and boost of the filter have been accurately estimated in simulation using the HF RMS detector. The sensitivity of an intermediate band pass node of the filter has also been monitored to predict the filter's sensitivity to Q errors. The final part of the research describes the design of a single-ended to differential converter for use in a broadband transceiver operating from 50-850 MHz. This circuit is used as the second stage in the transceiver after the LNA. The design has been simulated on a 0.35 um CMOS process and has a power consumption of 13.5 mW and less than 8 dB of noise figure over the entire band. It is capable of driving a 500fF load with less than 1dB of gain ripple over the entire band (50-850 MHz).

With the scaling of technology nodes, the speed performance of microprocessors has rapidly improved but the scaling of off-chip input/output (I/O) bandwidth is limited by physical pin resources and interconnect technologies. In order to reduce the performance gaps, new interface techniques have emerged and the marketplace has moved towards higher levels of integration with system on a chip (SoC) implementations. The advent of new techniques, however, has led to new challenges on the semiconductor and automated test equipment (ATE) industries. The relatively slow growing ATE technology comparing to I/O speeds especially intensifies manufacturing test issues. Testing high speed I/O timing parameters requires expensive high performance test equipment with high accuracy and resolution. The requirements increase integrated circuit (IC) manufacturing costs and thus test issues have become critical. This thesis focuses on on-chip test methods to improve test accuracy and reduce test costs for high speed double data rate (DDR) memory I/Os using source synchronous clocking. For testing the I/O timing parameters, a phase interpolator based on-chip timing sampler using a cycle-by-cycle control method was developed. This circuit generates data and clock patterns and controls the time delay between data and clock to detect the timing mismatch which indicates timing degradations. The on-chip timing sampler was implemented as a built-in self test (BIST) circuit for low-cost parametric timing measurements. The BIST scheme was fabricated with a 0.18-um CMOS process technology. Using the static and dynamic modes, measurement results are obtained for the I/O timing parameters such as the setup and hold times, input voltage-level variations tolerances, duty distortion tolerances and data skews. Moreover, a delay mismatch measurement method was developed to improve measurement accuracy using a simple control circuit. This delay mismatch detector measures timing mismatches between data and clock paths and then the timing mismatches are converted to timing specifications. This scheme is also implemented along with analog to digital converter (ADC) to collect digital test results supporting low-cost system-level tests. Thus, the low-frequency test results show that our on-chip measurement techniques provide an attractive low-cost solution and is effectively applied for testing high speed source synchronous systems. / text

The static linearity test is one of the fundamental production tests used to measure DC performance of analog to digital converters (ADCs). It comes with high test equipment cost. An ADC built-in-self-test (BIST) is an attractive solution. However the stringent linearity requirement for an on-chip signal generator has made it prohibitive. The stimulus error identification and removal (SEIR) method has greatly reduced the linearity requirement. However, it requires a highly stable voltage offset, which remains a daunting task. This work exploits the inherit capacitive sample-and-hold circuit used in various ADC architectures to inject offset with very good constancy. A 16-bit successive approximate register (SAR) ADC with the proposed BIST scheme is modeled and simulated in Matlab to prove its validity. The results show that the estimation error on the maximum INL is less than 0.07 LSB. This BIST solution is then naturally extended to the calibration of an ADC. It is shown missing codes of such ADC can be effectively estimated and calibrated out. / text

Jitter is generally defined as a time deviation of the clock waveform from its desired position. The deviation which occurs can be on the leading or lagging side and it can be bounded (deterministic) or unbounded (random). Jitter is a critical specification in the digital system design. There are various techniques to measure the jitter. The straightforward approach is based on spectrum analyzer or oscilloscope measurements. In this thesis an on-chip jitter measurement technique is investigated and the respective circuit is designed using 65 nm CMOS technology. The work presents the high level model and transistor level model, both implemented using Cadence software. Based on the Vernier concept the circuit is composed of an edge detector, two oscillators, and a phase detector followed by a binary counter, which provides the measurement result. The designed circuit attains resolution of 10ps and can operate in the range of 100 - 500 MHz Compared to other measurement techniques this design features low power consumption and low chip area overhead that is essential for built-in self-test (BIST) applications.

abstract: Testing and calibration constitute a significant part of the overall manufacturing cost of microelectromechanical system (MEMS) devices. Developing a low-cost testing and calibration scheme applicable at the user side that ensures the continuous reliability and accuracy is a crucial need. The main purpose of testing is to eliminate defective devices and to verify the qualifications of a product is met. The calibration process for capacitive MEMS devices, for the most part, entails the determination of the mechanical sensitivity. In this work, a physical-stimulus-free built-in-self-test (BIST) integrated circuit (IC) design characterizing the sensitivity of capacitive MEMS accelerometers is presented. The BIST circuity can extract the amplitude and phase response of the acceleration sensor's mechanics under electrical excitation within 0.55% of error with respect to its mechanical sensitivity under the physical stimulus. Sensitivity characterization is performed using a low computation complexity multivariate linear regression model. The BIST circuitry maximizes the use of existing analog and mixed-signal readout signal chain and the host processor core, without the need for computationally expensive Fast Fourier Transform (FFT)-based approaches. The BIST IC is designed and fabricated using the 0.18-µm CMOS technology. The sensor analog front-end and BIST circuitry are integrated with a three-axis, low-g capacitive MEMS accelerometer in a single hermetically sealed package. The BIST circuitry occupies 0.3 mm2 with a total readout IC area of 1.0 mm2 and consumes 8.9 mW during self-test operation. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2017