abstract: Micro Electro Mechanical Systems (MEMS) is one of the fastest growing field in silicon industry. Low cost production is key for any company to improve their market share. MEMS testing is challenging since input to test a MEMS device require physical stimulus like acceleration, pressure etc. Also, MEMS device vary with process and requires calibration to make them reliable. This increases test cost and testing time. This challenge can be overcome by combining electrical stimulus based testing along with statistical analysis on MEMS response for electrical stimulus and also limited physical stimulus response data. This thesis proposes electrical stimulus based built in self test(BIST) which can be used to get MEMS data and later this data can be used for statistical analysis. A capacitive MEMS accelerometer is considered to test this BIST approach. This BIST circuit overhead is less and utilizes most of the standard readout circuit. This thesis discusses accelerometer response for electrical stimulus and BIST architecture. As a part of this BIST circuit, a second order sigma delta modulator has been designed. This modulator has a sampling frequency of 1MHz and bandwidth of 6KHz. SNDR of 60dB is achieved with 1Vpp differential input signal and 3.3V supply / Dissertation/Thesis / M.S. Electrical Engineering 2013

abstract: Radio frequency (RF) transceivers require a disproportionately high effort in terms of test development time, test equipment cost, and test time. The relatively high test cost stems from two contributing factors. First, RF transceivers require the measurement of a diverse set of specifications, requiring multiple test set-ups and long test times, which complicates load-board design, debug, and diagnosis. Second, high frequency operation necessitates the use of expensive equipment, resulting in higher per second test time cost compared with mixed-signal or digital circuits. Moreover, in terms of the non-recurring engineering cost, the need to measure complex specfications complicates the test development process and necessitates a long learning process for test engineers. Test time is dominated by changing and settling time for each test set-up. Thus, single set-up test solutions are desirable. Loop-back configuration where the transmitter output is connected to the receiver input are used as the desirable test set- up for RF transceivers, since it eliminates the reliance on expensive instrumentation for RF signal analysis and enables measuring multiple parameters at once. In-phase and Quadrature (IQ) imbalance, non-linearity, DC offset and IQ time skews are some of the most detrimental imperfections in transceiver performance. Measurement of these parameters in the loop-back mode is challenging due to the coupling between the receiver (RX) and transmitter (TX) parameters. Loop-back based solutions are proposed in this work to resolve this issue. A calibration algorithm for a subset of the above mentioned impairments is also presented. Error Vector Magnitude (EVM) is a system-level parameter that is specified for most advanced communication standards. EVM measurement often takes extensive test development efforts, tester resources, and long test times. EVM is analytically related to system impairments, which are typically measured in a production test i environment. Thus, EVM test can be eliminated from the test list if the relations between EVM and system impairments are derived independent of the circuit implementation and manufacturing process. In this work, the focus is on the WLAN standard, and deriving the relations between EVM and three of the most detrimental impairments for QAM/OFDM based systems (IQ imbalance, non-linearity, and noise). Having low cost test techniques for measuring the RF transceivers imperfections and being able to analytically compute EVM from the measured parameters is a complete test solution for RF transceivers. These techniques along with the proposed calibration method can be used in improving the yield by widening the pass/fail boundaries for transceivers imperfections. For all of the proposed methods, simulation and hardware measurements prove that the proposed techniques provide accurate characterization of RF transceivers. / Dissertation/Thesis / Ph.D. Electrical Engineering 2013

abstract: The applications which use MEMS accelerometer have been on rise and many new fields which are using the MEMS devices have been on rise. The industry is trying to reduce the cost of production of these MEMS devices. These devices are manufactured using micromachining and the interface circuitry is manufactured using CMOS and the final product is integrated on to a single chip. Amount spent on testing of the MEMS devices make up a considerable share of the total final cost of the device. In order to save the cost and time spent on testing, researchers have been trying to develop different methodologies. At present, MEMS devices are tested using mechanical stimuli to measure the device parameters and for calibration the device. This testing is necessary since the MEMS process is not a very well controlled process unlike CMOS. This is done using an ATE and the cost of using ATE (automatic testing equipment) contribute to 30-40% of the devices final cost. This thesis proposes an architecture which can use an Electrical Signal to stimulate the MEMS device and use the data from the MEMS response in approximating the calibration coefficients efficiently. As a proof of concept, we have designed a BIST (Built-in self-test) circuit for MEMS accelerometer. The BIST has an electrical stimulus generator, Capacitance-to-voltage converter, ∑ ∆ ADC. This thesis explains in detail the design of the Electrical stimulus generator. We have also designed a technique to correlate the parameters obtained from electrical stimuli to those obtained by mechanical stimuli. This method is cost effective since the additional circuitry needed to implement BIST is less since the technique utilizes most of the existing standard readout circuitry already present. / Dissertation/Thesis / M.S. Electrical Engineering 2014

Ce travail concerne l'étude et la réalisation de stratégies d'auto-test intégrées pour VCO radiofréquence (RF). La complexité des circuits intégrés RF devient un obstacle pour la mesure des principaux blocs RF des chaines de transmission/réception. Certains nœuds ne sont pas accessibles, l'excursion en tension des signaux baisse et les signaux haute fréquence ne peuvent pas être amenés à l'extérieur de la puce sans une forte dégradation. Le s techniques habituelles de test deviennent très couteuses et lentes. Le test pour le wafer-sort est étudié en premier. La solution proposée est la mise en œuvre d'une stratégie d'auto-test intégrée (BIST) qui puisse discriminer entre circuits sans fautes et circuits avec fautes pendant le wafer-test. La méthodologie utilisée est le test structurel. La couverture des fautes est étudiée pour connaitre la quantité à capter au niveau intégré afin de maximiser la probabilité de trouver tous les défauts physiques dans le VCO. Le résultat de cette analyse montre que la couverture des fautes est maximisée quand la tension crête-crête en sortie du VCO est captée. La caractérisation complète (validation de la puce et process-monitoring) du VCO est étudiée dans la deuxième étape. Les informations à extraire de la puce sont: amplitude des signaux, consommation du VCO, fréquence d'oscillation, gain de conversion (Kvco) et une information à propos du bruit de phase. Un démonstrateur pour le test au niveau wafer est réalisé en technologie ST CMOS 65nm. Le démonstrateur est composé d'un VCO 3.5GHz (le circuit sous test), un LDO, une référence de tension indépendante de température et variations d'alimentation, un capteur de tension crête-crête et un comparateur. Le capteur Vpp donne en sortie une information DC qui est comparée avec une plage de valeurs acceptables. Le BIST donne en sortie une information numérique pass/fail. / This work deals with the study and the realization of Built-In Self-Tests (BIST) for RF VCOs (Voltage Controlled Oscillators) The increasing complexity of RF integrated circuits is creating an obstacle for the correct measurement of the main RF blocks of any transceiver. Some nodes are not accessible, the voltage excursion of the signals is getting lower and lower and high frequency signals cannot be driven off the die without a main degradation. The common test techniques become then very expensive and time consuming. The wafer sort is firstly approached. The proposed solution is the implementation of a BIST strategy able to discriminate between faulty and good circuits during the wafer test. The chosen methodology is the structural test (fault-oriented). A fault coverage campaign is carried out in order to find the quantity to monitor on-chip that maximizes the probability to find all possible physical defects in the VCO. The result of the analysis reveals that the fault coverage is maximized if the peak-to-peak output voltage is monitored. The complete on-chip characterization of the VCO is then addressed, for chip validation and process monitoring. The information that need to be extracted on-chip concern: amplitude of the signal, consumption of the VCO, frequency of oscillation, its conversion gain (voltage-to-frequency) and eventually some information on the phase noise. A silicon demonstrator for wafer sort purposes is implemented using the ST CMOS 65nm process. It includes a 3.5GHz VCO, an LDO, a temperature and supply-voltage independent voltage reference, a peak-to-peak voltage detector and a comparator. The Vpp detector outputs a DC-voltage that is compared to a predefined acceptance boundary. A logic pass/fail signal is output by the BIST. The attention is then turned to the study of the proposed architecture for an on-chip frequency-meter able to measure the RF frequency with high accuracy. Behavioral simulations using VHDL-AMS lead to the conclusion that a TDC (Time-to-Digital Converter) is the best solution for our goal. The road is then opened to the measure of long-time jitter making use of the same TDC.

No description available.

Cette thèse vise l’étude de techniques de type BIST pour un front-end RF, considérant des nouveaux types des capteurs intégrés très simples pour l’extraction de signaux. Ces signaux et les stimuli de test associés seront par la suite traités par des algorithmes de l’apprentissage automatique qui devront permettre une prédiction des performances des différents blocs du système. Une évaluation des capteur proposés en tant que métriques de test paramétrique et couverture des fautes catastrophique sera nécessaire pour pouvoir aboutir à des techniques de test à bas coût pour le test de production, permettant une réduction importante du coût de revient des produits. / This thesis aims to study techniques such BIST for RF front-end, whereas new types of simple integrated sensors for signal extraction. These signals and stimuli associated test will then be processed by machine learning algorithms that will allow prediction of the performance of different blocks of the system. An evaluation of the proposed sensor as parametric test metrics and coverage of catastrophic faults will be needed to reach test techniques for low-cost production test, allowing a significant reduction in the cost of products

Made available in DSpace on 2015-05-08T14:57:17Z (GMT). No. of bitstreams: 1 arquivototal.pdf: 3191819 bytes, checksum: 142a338f10b5b1c73f589237be4728c2 (MD5) Previous issue date: 2014-02-26 / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior - CAPES / This work aims to carry out an analysis of the main existing testing strategies for FPGA, and propose a new strategy applied to the interconnection network of the Xilinx Spartan 3E FPGA based on linear feedback shift register synthesized by Berlekamp Massey Algorithm that can accurately localize the failure. For this, we used softwares from Xilinx manufacturer (specifically, XDL and FPGA_editor) to determine the FPGA based configuration and than create a new proposal and evaluate their employability. As a result of the proposed strategy, it was possible to route 7 WUTs (Wires Under Test) of total of 8 for the FPGA under investigation. Thus, it was necessary 24 test configurations to test and locate the failure on all hexlines and doublelines. The results show that this strategy is able to test 7 WUTs at a time and needs 24 test configurations to test and diagnose precisely the failure location. / Este trabalho objetiva realizar uma análise das principais estratégias de teste já existentes para FPGA, e propor uma nova estratégia aplicada à rede de interconexão do FPGA Xilinx Spartan 3E baseada em registradores de deslocamento com realimentação linear sintetizável pelo Algoritmo de Berlekamp-Massey e que possa diagnósticar com precisão o local da falha. Para isso, foram utilizados softwares da fabricante de FPGAs Xilinx (especificamente, XDL e FPGA_editor) para determinar precisamente a configuração do FPGA e, assim, criar uma nova proposta e avaliar sua empregabilidade. Como resultado, a partir da estratégia adotada foi possível rotear 7 WUTs (Wires Under Test) em um total de 8 para o FPGA em questão. Sendo assim, foram necessárias 24 configurações de teste para testar e diagnósticar todas as linhas do tipo HexLine e DoubleLine. Os resultados obtidos mostram que a estratégia proposta é capaz de testar 7 WUTs por vez e necessita de 24 configurações para testar e diagnósticar precisamente o local da falha na rede de interconexão.

Le test de circuits analogiques et mixtes est de plus en plus difficile du fait de l’intégration d’un nombre croissant de composants complexes au sein d’un même système. Les techniques de BIST permettent la réalisation d’un test efficace en intégrant au système les ressources nécessaires au test. Dans cette thèse, nous présentons une structure BIST pour les Convertisseurs Analogiques-Numériques (CAN) tout numérique. Le générateur de stimuli est un oscillateur Sigma-Delta numérique délivrant, après un simple filtrage analogique, une sinusoïde. L’analyse de la réponse se fait au moyen d’un banc de filtres numériques séparant les différentes composantes harmoniques du signal issu du CAN. A partir de ces composantes harmoniques, différents paramètres spectraux sont calculés. Afin de valider cette structure, différents prototypes ont été conçu sur FPGA. Les résultats expérimentaux confirment la capacité de notre structure à tester efficacement un CAN 12 bits ayant un SNR de 70 dB. / Analog and mixed circuit testing is more and more difficult because of the integration of agrowing number of complex components in one system. BIST techniques allow the realizationof an effective test system by integrating the test resources to the system. In this thesis, wepresent a BIST Structure for Analog to Digital Converters (ADC). The stimuli generatoris a digital Sigma-Delta oscillator delivering a sine wave after a simple analog filtering. Abank of digital filters separating the different harmonic components of the signal from theADC is used to analyze of the response. From these harmonic components, different spectralparameters are calculated. To validate this structure, different prototypes have been designedon FPGA. The experimental results confirm the ability of our structure to effectively test a12-bit ADC with a 70-dB-SNR.

Grandes saltos tecnológicos viabilizaram a integração de circuitos digitais de alta complexidade, com centenas de pinos e milhões de transistores. Sistematicamente, dispositivos eletromecânicos estão sendo substituídos por Circuitos Integrados (CIs) que contêm sistemas inteiros, ampliando o uso generalizada da eletrônica. Com o aumento da complexidade e quantidade de CIs produzidos, a tarefa de detectar de forma rápida e eficiente aqueles chips com problemas assumiu grande importância. Como a Testabilidade [McClu 86] de um CI afeta sua qualidade, um circuito que não é completamente testável, para um determinado modelo de falha, tem menos valor que outro inteiramente testável [De Mi 94]. Em estudos sobre confiabilidade, desempenho, custos e Testabilidade de circuitos VLSI verificou-se que o custo associado ao processo de testes de circuitos VLSI estava praticamente estabilizado, enquanto outros componentes do preço final do chip caíam. Por estas razões, a Testabilidade foi incorporada ao projeto desde suas concepções iniciais, apresentando geralmente resultados com menor Sobreárea e mínimo impacto no desempenho, quando comparado a CIs produzidos sem considerações relacionadas a testes. Uma técnica de teste que dispensa o uso de Equipamento Automático de Teste, conhecida como Autoteste Incorporado (em inglês, Built-In Self-Test – BIST), consiste em adaptar partes do próprio CI para gerar Vetores de Teste, comprimir e analisar os resultados. A técnica BIST tem sido empregada com sucesso em ambientes de projeto de Síntese de Alto Nível (High Level Synthesis, HLS), que tende a reduzir o tempo de projeto de um ASIC, auxiliando a determinação da arquitetura RTL [Stru et al. 99]. Nesta dissertação, considera-se uma forma específica de BIST, o structural off-line BIST [Abr et al. 90], em que o Autoteste se dá quando o CI digital é retirado de sua operação normal e colocado em modo teste, para que um Plano de Teste para Unidades Funcionais seja executado (na fase de manufatura e/ou de serviço em campo). O Plano de Teste, baseado em uma descrição estrutural do CI, é gerado por um algoritmo concebido para detectar os registradores que devem ser reconfigurados em Geradores de Padrões de Teste (em inglês, Test Pattern Generators, TPGs) e Analisadores de Assinatura (Signature Analyzers, SAs). O critério de seleção dos registradores baseia-se numa Função Custo, que avalia globalmente o grau de compartilhamento de cada registrador candidato, e a contribuição que a sua eventual escolha causaria no tempo final de teste. Os Registradores de Teste, reconfigurados em Autômatos Celulares (Cellular Automata, CAs), devem operar segundo um “Rule Number", neste caso, Regra 90 ou 150. A tarefa do Autoteste paralelo é dividida em duas etapas: na primeira, a cada uma das Unidades Funcionais é associado o melhor momento possível para início de sua sessão de teste, resultando na construção gradativa de uma Matriz de Estado de Teste, e na segunda, com a Matriz de Estado de Teste já totalmente definida, é feita uma análise global para minimizar o número de candidatos a registrador de teste. O resultado final é um Plano de Teste Otimizado definindo as regras dos TPGs (TPG90 e/ou TPG150), o custo em termos de Sobreárea, o início da geração dos Vetores de Teste, sua duração e a Cobertura de Falha mínima. / Great technological developments have made possible the integration of digital circuits of high complexity, with hundreds of pins and million of transistors. Electromechanical devices are being systematically substituted for Integrated Circuits (ICs) that contain complete systems, extending the generalized use of electronics. With the increasing complexity and amount of ICs, the task of detecting faulty chips in a fast and efficient way has assumed great importance. As testability [McClu 86] affects the quality of an IC, a circuit that is not fully testable for one determined fault model has less value than another which is entirely testable [De Mi 94]. It was verified in studies on reliability, performance, costs and testability of VLSI circuits that the cost associated with tests was practically stabilized, while other components of the final price fell. For these reasons, testability was incorporated in the design since its initial conception, producing generally minor area overhead and minimum impact on the performance, when compared to ICs produced without test considerations. One test technique that eliminates de needs for use of Automatic Test Equipment, known as BIST - Built-In Self-Test, consists of adapting parts of the IC to generate Test Vectors, compress and analyze the results. The BIST technique has been used successfully in design of HLS - High Level Synthesis - environments, which tends to reduce the ASIC’s design time, easing the task of determining the RTL architecture [Stru et al. 99]. In this dissertation a specific form of BIST, the structural off-line BIST [Abr et al. 90], is considered. To start the self-test it is necessary to halt the normal operation of the digital IC and put it in test mode, so that a Test Plan for Functional Units is executed (in the phase of manufacture and/or in the field). The Test Plan based on the structure of the IC is generated by an algorithm conceived to detect the registers which will be reconfigured in TPGs - Test Pattern Generators, and SAs - Signature Analyzers. The criterion for selection of the registers is based on a Cost Function, which globally evaluates the degree of sharing of each register candidate, and the contribution that its eventual choice would cause in the final test time. The Test Registers reconfigured in CAs – Cellular Automata - must operate according to a “Rule Number", in this case Rule 90 or 150. The task of the parallel self-test is divided into two stages: in the first one, to each Functional Unit is associated the best possible moment for its test session beginning, resulting in the gradual construction of a Test Status Matrix, and in the second, with the Test Status Matrix completely defined, a global analysis is made to minimize the number of register candidates. The final result is an Optimized Test Plan, which defines the rules of the TPGs (TPG90 and/or TPG150), the area overhead cost, the beginning of the Test Vector Generation, its duration and the minimum Fault Coverage.

With rapid development in semiconductor technology, today's large and complex integrated circuits require a large amount of test data to achieve desired test coverage. Test cost, which is proportional to the size of the test set, can be reduced by generating a small number of highly effective test patterns. Automatic Test Pattern Generators (ATPGs) generate effective deterministic test patterns for different fault models and can achieve high test coverage. To reduce ATPG-produced test set size, design for test (DFT) methods can be used to further improve the ATPG process and apply generated test patterns in more efficient ways. The first part of this dissertation introduces a test point insertion (TPI) technique that reduces the test pattern counts and test data volume of a design by adding additional hardware called control points. These dedicated control points are inserted at internal nodes of the design to resolve large internal conflicts during ATPG. Therefore, more faults can be detected by a single test pattern. To minimize silicon area needed to implement these control points, we propose a method that reuses some existing functional flip-flops as drivers of the control points, instead of inserting dedicated flip-flops for the control points. Experimental results on industrial designs indicate that the proposed technique can achieve significant test pattern reductions, similar to the control points using dedicated flip-flops. The second part of this dissertation proposes a staggered ATPG scheme that produces deterministic test-per-clock-based staggered test patterns by using dedicated compactor scan chains to capture additional test responses during scan shift cycles that are used for regular scan cells to completely load each test pattern. These compactor scan chains are formed by dedicated capture-per-cycle observation test points inserted at suitable locations of the design. By leveraging this new scan infrastructure, more compacted test patterns can be generated, and more faults can also be systematically detected during the simulation process, thus reducing the overall test pattern count. To meet the stringent test requirements for in-system test (especially for automotive test), a built-in self-test (BIST) approach, called Stellar BIST, is introduced in the last part of this dissertation. Stellar BIST employs a dedicated BIST infrastructure with additional on-system memory to store some parent test patterns (seeds). Derivative test patterns can be obtained by complementing selected bits of corresponding parent patterns through an on-chip Stellar BIST controller. A dedicated ATPG process is also proposed for generating a minimal set of test patterns that need to be stored and their effective derivative patterns that require short test application time. Furthermore, the proposed scheme can provide flexible trade-offs between stored test data volume and test application time.