In recent years, there has been a growing interest in wireless ad hoc network. One of the major issues in wireless network is developing efficient routing protocol. Based on the concept of designing protocol model such as OSI model, the designers distilled the process of transmitting data to its most fundamental elements and identified which networking functions had related uses and collected those functions into discrete groups that became the layers. It is not suitable to design wireless ad hoc routing protocol based on OSI model conception because the OSI model is developed from the view point of wired network and there are many different characteristics between wired and wireless environment. The main different characteristics between wired and wireless are the mobility of mobile host and the transmission medium. Such differences have great effect on network performance. Due to the differences between wired and wireless characteristics, we present a comprehensive conception of designing wireless ad hoc routing protocol. In this context, we provide a wireless ad hoc routing protocol based on physical layer characteristics, ex: bit error rate, robust link. Our routing protocol will find out a route in good transmission environment and it is efficient to improve network throughput. Furthermore, our routing protocol will decrease the number of route request packets, the amount of retransmissions, link breakage rate, and increase throughput.

As the size and power consumption of microelectronic circuits continues to decrease, passively-powered sensors promise to come to the forefront of commercial electronics. One of the most promising technologies that could realize this goal is backscatter sensing. Backscatter sensors could harvest power from and modulate data onto an impinging carrier waveform. Currently radio frequency identification (RFID) technology passively powers itself and transmits statically stored data. However, this technology has two major weaknesses: lack of resiliency against narrowband interference and slow data rates. Both of these issues could be detrimental in sensing applications. This thesis will lay out a method for addressing both of these weaknesses through a unique application of spread spectrum encoding. Instead of spread spectrum being viewed as the multiplication of an already encoded data sequence with a periodic pseudorandom sequence, each sequence could be viewed in an aperiodic manner, where a single period of a pseudorandom sequence represents a data symbol. In this manner, backscatter sensors not only benefit from the increased resiliency that spread spectrum provides, but also can have higher data rates, since multiple bits can be encoded on a single symbol and multiple nodes can be read simultaneously, using spread spectrum multiple access techniques. In this thesis, 63-chip and 255-chip Kasami sequences, as well as 127-chip Gold sequences, will be analyzed for their use in various aperiodic direct sequence spread spectrum/multiple access system configurations (systems that have up to three nodes and use up to four different aperiodic sequences per node to represent different symbols). For each different configuration, near-"ideal" code configurations/rotations will be determined for use in the system.

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In wireless Communication, the need of radio spectrum increases nowadays. But in the system we are losing approximately 82-86% of spectrum most of the time due to the absence of Primary User (PU). To overcome this issue Cognitive Radio (CR) is an admirable approach. The concept of cooperative communication needs to be considering because high data rate is the demand for wireless services. Cooperative diversity in the network realized by 3-hop Decode, Amplify and Forward (DAF) and Decode and Forward (DF) and in 2-hop DF and Amplify and Forward (AF) Protocols implemented in cognitive radio communication network using Orthogonal Space Time Block Coding (OSTBC). The communication between end points is accomplished by using Multiple Input and Multiple Output (MIMO) antenna arrangement. During the Propagation, Alamouti Space Time Block Coding is used to accomplish spatial diversity and the encoded data is transmitted through Rayleigh fading channel. CR decodes the transmitted signal using Maximum Likelihood (ML) decoding method. Afterward signal broadcast toward the destination. To check the energy level of signal, energy detection technique applies at the Cognitive Controller (CC). Finally, CC will take ultimate decision for the presence of primary user if the energy level of signal is greater than predefined threshold level, it means PU is present otherwise it is absent. The main objective of this thesis is to analyze the performance of 3-hop and 2-hop communication network using relays. The performance is compared on the bases of two parameters i.e. Bit Error Rate (BER) and Probability of Detection (PD). The results are processed and validated by MATLAB simulation.

There are a number of testability considerations for VLSI design, but test coverage, test time, accuracy of test patterns and correctness of design information for DFD (Design for debug) are the most important ones in design with embedded memories. The goal of DFT (Design-for-Test) is to achieve zero defects. When it comes to the memory subsystem in SOCs (system on chips), many flavors of memory BIST (built-in self test) are able to get high test coverage in a memory, but often, no proper attention is given to the memory interface logic (shadow logic). Functional testing and BIST are the most prevalent tests for this logic, but functional testing is impractical for complicated SOC designs. As a result, industry has widely used at-speed scan testing to detect delay induced defects. Compared with functional testing, scan-based testing for delay faults reduces overall pattern generation complexity and cost by enhancing both controllability and observability of flip-flops. However, without proper modeling of memory, Xs are generated from memories. Also, when the design has chip compression logic, the number of ATPG patterns is increased significantly due to Xs from memories. In this dissertation, a register based testing method and X prevention logic are presented to tackle these problems. An important design stage for scan based testing with memory subsystems is the step to create a gate level model and verify with this model. The flow needs to provide a robust ATPG netlist model. Most industry standard CAD tools used to analyze fault coverage and generate test vectors require gate level models. However, custom embedded memories are typically designed using a transistor-level flow, there is a need for an abstraction step to generate the gate models, which must be equivalent to the actual design (transistor level). The contribution of the research is a framework to verify that the gate level representation of custom designs is equivalent to the transistor-level design. Compared to basic stuck-at fault testing, the number of patterns for at-speed testing is much larger than for basic stuck-at fault testing. So reducing test and data volume are important. In this desertion, a new scan reordering method is introduced to reduce test data with an optimal routing solution. With in depth understanding of embedded memories and flows developed during the study of custom memory DFT, a custom embedded memory Bit Mapping method using a symbolic simulator is presented in the last chapter to achieve high yield for memories. / text

ITC/USA 2014 Conference Proceedings / The Fiftieth Annual International Telemetering Conference and Technical Exhibition / October 20-23, 2014 / Town and Country Resort & Convention Center, San Diego, CA / Typical airborne test platforms use multiple telemetry transmit antennas in a top and bottom configuration in order to mitigate signal shadowing during maneuvers on high dynamic platforms. While mitigating one problem, this also creates a co-channel interference problem as the same signal, time delayed with differing amplitude, is sent to both antennas. Space-Time Coding (STC) was developed with the intention of mitigating this co-channel interference problem, also known as the "two antenna problem". Lab testing and preliminary flight testing of developmental and pre-production hardware has been completed and documented. This is the first test dedicated to assessing the performance of a production STC system in a real-world test environment. This paper will briefly describe lab testing that preceded the flight testing, describes the airborne and ground station configurations used during the flight test, and provides detailed results of the performance of the space time coded telemetry link as compared against a reference telemetry link.

ITC/USA 2013 Conference Proceedings / The Forty-Ninth Annual International Telemetering Conference and Technical Exhibition / October 21-24, 2013 / Bally's Hotel & Convention Center, Las Vegas, NV / Since the waveform was first developed by the Advanced Range Telemetry Program (ARTM) and adopted by the Range Commanders Council Telemetry Group (RCC/TG), receiver/demodulators for the ARTM Continuous Phase Modulation (CPM) waveform have undergone continued development by several hardware vendors to boost performance in terms of phase noise, detection performance, and resynchronization time. These same results were initially presented at the International Telemetry Conference (ITC) 2003 when hardware first became available supporting this waveform, at the time called ARTM Tier II. This paper reexamines the current state of the art performance of ARTM CPM receiver/demodulators available in the marketplace today.

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This thesis presents the design and experimental results of a low-power pipeline ADC that applies front-end capacitor-sharing. The ADC operates at 20 MS/s, resolves 1.5 bits/stage, and is implemented in IBM 0.13um technology. The purpose of the technique is to reduce power consumption in the front-end S/H. This work is a proof-of-concept and it concentrates on the front-end design. A comparison is conducted between a capacitor-sharing ADC and a regular ADC and as a result, the technique reduces the power consumption in the front-end S/H by 39%. At an input frequency of 9.53 MHz and a sampling rate of 20 MS/s, the fabricated capacitor-sharing ADC consumes 4.7 mW at 1.2 V, and it achieves an ENOB of 8.5 bits and a FOM of 0.68 pJ/step. It has an ENOB as high as 8.67 bits at 0.4 MS/s and a FOM as low as 0.6 pJ/step when sub-sampling at 20 MS/s.

This thesis presents the design and experimental results of a low-power pipeline ADC that applies front-end capacitor-sharing. The ADC operates at 20 MS/s, resolves 1.5 bits/stage, and is implemented in IBM 0.13um technology. The purpose of the technique is to reduce power consumption in the front-end S/H. This work is a proof-of-concept and it concentrates on the front-end design. A comparison is conducted between a capacitor-sharing ADC and a regular ADC and as a result, the technique reduces the power consumption in the front-end S/H by 39%. At an input frequency of 9.53 MHz and a sampling rate of 20 MS/s, the fabricated capacitor-sharing ADC consumes 4.7 mW at 1.2 V, and it achieves an ENOB of 8.5 bits and a FOM of 0.68 pJ/step. It has an ENOB as high as 8.67 bits at 0.4 MS/s and a FOM as low as 0.6 pJ/step when sub-sampling at 20 MS/s.