We present novel architectures for parallel-node low-density parity-check convolutional code (PN-LDPC-CC) encoders and decoders. Based on a recently introduced implementation-aware class of LDPC-CCs, these encoders and decoders take advantage of increased node-parallelization to simultaneously decrease the energy-per-bit and increase the decoded information throughput. A series of progressively improved encoder and decoder designs are presented and characterized using synthesis results with respect to power, area and throughput. The best of the encoder and decoder designs significantly advance the state-of-the-art in terms of both the energy-per-bit and throughput/area metrics. One of the presented decoders, for an Eb /N0 of 2.5 dB has a bit-error-rate of 106, takes 4.5 mm2 in a CMOS 90-nm process, and achieves an energy-per-decoded-information-bit of 65 pJ and a decoded information throughput of 4.8 Gbits/s. We implement an earlier non-parallel node LDPC-CC encoder, decoder and a channel emulator in silicon. We provide readers, via two sets of tables, the ability to look up our decoder hardware metrics, across four different process technologies, for over 1000 variations of our PN-LDPC-CC decoders. By imposing practical decoder implementation constraints on power or area, which in turn drives trade-offs in code size versus the number of decoder processors, we compare the code BER performance. An extensive comparison to known LDPC-BC/CC decoder implementations is provided.

This thesis studies cooperative techniques that rely on femtocell user diversity to improve the downlink communication quality of macrocell users. We analytically analyze and evaluate the achievable performance of these techniques in the downlink of Rayleigh fading channels. We provide an approximation of both the bit-error rate (BER) and the data throughput that macrocell users receive with femtocell user cooperation. Using simulations, we show that under reasonable SNR values, cooperative schemes enhance the performances of macrocells by improving the BER, outage probability, and data throughput of macrocell users significantly when compared with the traditional, non-cooperative schemes. / Graduation date: 2012

This thesis is divided into two parts. In the first part we focus mainly on certain aspects of the AdS/CFT correspondence. The AdS/CFT correspondence is a proposed duality between Type IIB superstring theory on AdS5 x S5 and N = 4 supersymmetric Yang-Mills theory. In the BMN limit string states located in the center of AdS5 rotate quickly around the equator of the S5 and correspond, in the dual theory, to operators constructed as long chains of sub-operators. This structure of the operators can be formulated as a spin chain and by using the Bethe ansatz their properties can be obtained by solving a set of Bethe equations. Having infinitely many sub-operators, there are methods for solving the Bethe equations in certain sectors. In paper III finite size corrections to the anomalous dimensions in the SU(2) sector are calculated to leading order. Inspired by the chain structure of the corresponding operators, the theory of string bits treats the strings as a discrete sets of points. This theory suffers from the problem of fermion doubling, a general pathology of fermions on a lattice. In paper II we show how to adjust the theory in order to avoid this problem and, in fact, use the fermion doubling to our advantage. The second part of the thesis studies the low energy behaviour of SU(2) Yang-Mills theory in 4 space-time dimensions. In paper I we perform numerical calculations on an effective action for this theory. We propose the existence of a knotted trajectory within the dynamics of this effective action.

Fjords contain a significant quantity of sediments deposited in coastal zones over the last ~100,000 years. Studies of Northern Hemisphere fjords have shown that a large part of the high concentration of sedimentary organic matter (OMsed) is terrestrial in origin (OMterr), composed of a modern detrital fraction and an old mineral-associated fraction (OMfossil). These results suggest that fjords are disproportionately responsible, on a per area basis, for the burial of organic matter in coastal zones. This study, after a rigorous examination of CuO and GDGT biomarker methods used to quantify terrestrial organic matter in coastal environments, demonstrated this hypothesis in a Southern Hemisphere fjord system, Fiordland, New Zealand. CuO analysis of Doubtful Sound surface sediments indicated a large contribution of vascular plant material to fjord sediments. The BIT Index correlated strongly with both delta13C and C/N values in Doubtful Sound surface sediments, indicated that it may accurately trace the relative proportions of marine and soil organic matter (OMsoil) in Fiordland. However, a detailed analysis of the conversion of the BIT Index to quantitative estimates of terrestrial (soil) organic matter revealed that these values are overestimates. Reconstructions of the BIT Index and tetraethers in cores from two locations on the Louisiana continental shelf demonstrated the influence of the crenarchaeol term on BIT Index-based terrestrial organic matter estimates. The differences in the applicability of the BIT Index to these two coastal environments was most likely due to large seasonal changes in productivity on the Louisiana Continental Shelf as well as higher marine relative to terrestrial inputs. Six cores were reconstructed for contributions from marine OM (OMmar), OMfossil, and OMterrestrial representing the last ~500 years of sedimentation. Spatial variations were larger than temporal variations, owing to negligible development and deforestation in the region. OMterr was the dominant fraction in all but one core, and OMfossil inputs were significant. Additionally, source reconstructions from a variety of biomarkers indicated that Landslides deliver large volumes of detrital organic matter to fjord sediments. These results confirm that fjords bury quantitatively significant volumes of organic carbon on a global scale.

We construct polar codes for binary relay channels with orthogonal receiver components. We show that polar codes achieve the cut-set bound when the channels are symmetric and the relay-destination link supports compress-and-forward relaying based on Slepian-Wolf coding. More generally, we show that a particular version of the compress-and-forward rate is achievable using polar codes for Wyner-Ziv coding. In both cases the block error probability can be bounded as O(2-Nβ) for 0 &lt; β &lt; 1/2 and sufficiently large block length N. / <p>© 2010 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. QC 20111207</p>

<p>This dissertation studies a state-of-the-art bandwidth-efficient coded modulation technique, known as bit interleaved coded modulation with iterative decoding (BICM-ID), together with various diversity techniques to dramatically improve the performance of digital communication systems over wireless channels.</p> <p>For BICM-ID over a single-antenna frequency non-selective fading channel, the problem of mapping over multiple symbols, i.e., multi-dimensional (multi-D) mapping, with 8-PSK constellation is investigated. An explicit algorithm to construct a good multi-D mapping of 8-PSK to improve the asymptotic performance of BICM-ID systems is introduced. By comparing the performance of the proposed mapping with an unachievable lower bound, it is conjectured that the proposed mapping is the global optimal mapping. The superiority of the proposed mapping over the best conventional (1-dimensional complex) mapping and the multi-D mapping found previously by computer search is thoroughly demonstrated.</p> <p>In addition to the mapping issue in single-antenna BICM-ID systems, the use of signal space diversity (SSD), also known as linear constellation precoding (LCP), is considered in BICM-ID over frequency non-selective fading channels. The performance analysis of BICM-ID and complex N-dimensional signal space diversity is carried out to study its performance limitation, the choice of the rotation matrix and the design of a low-complexity receiver. Based on the design criterion obtained from a tight error bound, the optimality of the rotation matrix is established. It is shown that using the class of optimal rotation matrices, the performance of BICM-ID systems over a frequency non-selective Rayleigh fading channel approaches that of the BICM-ID systems over an additive white Gaussian noise (AWGN) channel when the dimension of the signal constellation increases. Furthermore, by exploiting the sigma mapping for any M-ary quadrature amplitude modulation (QAM) constellation, a very simple sub-optimal, yet effective iterative receiver structure suitable for signal constellations with large dimensions is proposed. Simulation results in various cases and conditions indicate that the proposed receiver can achieve the analytical performance bounds with low complexity.</p> <p>The application of BICM-ID with SSD is then extended to the case of cascaded Rayleigh fading, which is more suitable to model mobile-to-mobile communication channels. By deriving the error bound on the asymptotic performance, it is first illustrated that for a small modulation constellation, a cascaded Rayleigh fading causes a much more severe performance degradation than a conventional Rayleigh fading. However, BICM-ID employing SSD with a sufficiently large constellation can close the performance gap between the Rayleigh and cascaded Rayleigh fading channels, and their performance can closely approach that over an AWGN channel.</p> <p>In the next step, the use of SSD in BICM-ID over frequency selective Rayleigh fading channels employing a multi-carrier modulation technique known as orthogonal frequency division multiplexing (OFDM) is studied. Under the assumption of correlated fading over subcarriers, a tight bound on the asymptotic error performance for the general case of applying SSD over all N subcarriers is derived and used to establish the best achievable asymptotic performance by SSD. It is then shown that precoding over subgroups of at least L subcarriers per group, where L is the number of channel taps, is sufficient to obtain this best asymptotic error performance, while significantly reducing the receiver complexity. The optimal joint subcarrier grouping and rotation matrix design is subsequently determined by solving the Vandermonde linear system. Illustrative examples show a good agreement between various analytical and simulation results.</p> <p>Further, by combining the ideas of multi-D mapping and subcarrier grouping, a novel power and bandwidth-efficient bit-interleaved coded modulation with OFDM and iterative decoding (BI-COFDM-ID) in which multi-D mapping is performed over a group of subcarriers for broadband transmission in a frequency selective fading environment is proposed. A tight bound on the asymptotic error performance is developed, which shows that subcarrier mapping and grouping have independent impacts on the overall error performance, and hence they can be independently optimized. Specifically, it is demonstrated that the optimal subcarrier mapping is similar to the optimal multi-D mapping for BICM-ID in frequency non-selective Rayleigh fading environment, whereas the optimal subcarrier grouping is the same with that of OFDM with SSD. Furthermore, analytical and simulation results show that the proposed system with the combined optimal subcarrier mapping and grouping can achieve the full channel diversity without using SSD and provide significant coding gains as compared to the previously studied BI-COFDM-ID with the same power, bandwidth and receiver complexity.</p> <p>Finally, the investigation is extended to the application of BICM-ID over a multiple-input multiple-output (MIMO) system equipped with multiple antennas at both the transmitter and the receiver to exploit both time and spatial diversities, where neither the transmitter nor the receiver knows the channel fading coefficients. The concentration is on the class of unitary constellation, due to its advantages in terms of both information-theoretic capacity and error probability. The tight error bound with respect to the asymptotic performance is also derived for any given unitary constellation and mapping rule. Design criteria regarding the choice of unitary constellation and mapping are then established. Furthermore, by using the unitary constellation obtained from orthogonal design with quadrature phase-shift keying (QPSK or 4-PSK) and 8-PSK, two different mapping rules are proposed. The first mapping rule gives the most suitable mapping for systems that do not implement iterative processing, which is similar to a Gray mapping in coherent channels. The second mapping rule yields the best mapping for systems with iterative decoding. Analytical and simulation results show that with the proposed mappings of the unitary constellations obtained from orthogonal designs, the asymptotic error performance of the iterative systems can closely approach a lower bound which is applicable to any unitary constellation and mapping.</p>

Implementation of the polyphase decomposed FIR filter structure involves two steps; the generation of the partial products and the efficient reduction of the generated partial products. The partial products are generated by a constant multiplication of the filter coefficients with the input data and the reduction of the partial products is done by building a pipelined adder tree using FAs and HAs. To improve the speed and to reduce the complexity of the reduction tree a4:2 counter is introduced into the reduction tree. The reduction tree is designed using a bit-level optimized ILP problem which has the objective function to minimize the overall cost of the hardware used. For this purpose the layout design for a 4:2 counter has been developed and the cost function has been derived by comparing the complexity of the design against a standard FA design. The layout design for a 4:2 counter is implemented in a 65nm process using static CMOS logic style and DPL style. The average power consumption drawn from a 1V power supply, for the static CMOS design was found to be 16.8μWand for the DPL style it was 12.51μW. The worst case rise or fall time for the DPL logic was 350ps and for the static CMOS logic design it was found to be 260ps. The usage of the 4:2 counter in the reduction tree infused errors into the filter response, but it helped to reduce the number of pipeline stages and also to improve the speed of the partial product reduction.

Continuous scaling of the transistor size and reduction of the operating voltage have led to a significant performance improvement of integrated circuits. However, the vulnerability of the scaled circuits to transient data upsets or soft errors, which are caused by alpha particles and cosmic neutrons, has emerged as a major reliability concern. In this thesis, we have investigated the effects of soft errors in combinational circuits and proposed soft error detection techniques for high speed adders. In particular, we have proposed an area-efficient 64-bit soft error robust logarithmic adder (SRA). The adder employs the carry merge Sklansky adder architecture in which carries are generated every 4 bits. Since the particle-induced transient, which is often referred to as a single event transient (SET) typically lasts for 100~200 ps, the adder uses time redundancy by sampling the sum outputs twice. The sampling instances have been set at 110 ps apart. In contrast to the traditional time redundancy, which requires two clock cycles to generate a given output, the SRA generates an output in a single clock cycle. The sampled sum outputs are compared using a 64-bit XOR tree to detect any possible error. An energy efficient 4-input transmission gate based XOR logic is implemented to reduce the delay and the power in this case. The pseudo-static logic (PSL), which has the ability to recover from a particle induced transient, is used in the adder implementation. In comparison with the space redundant approach which requires hardware duplication for error detection, the SRA is 50% more area efficient. The proposed SRA is simulated for different operands with errors inserted at different nodes at the inputs, the carry merge tree, and the sum generation circuit. The simulation vectors are carefully chosen such that the SET is not masked by error masking mechanisms, which are inherently present in combinational circuits. Simulation results show that the proposed SRA is capable of detecting 77% of the errors. The undetected errors primarily result when the SET causes an even number of errors and when errors occur outside the sampling window.

The compressive sensing (CS) framework aims to ease the burden on analog-to-digital converters (ADCs) by exploiting inherent structure in natural and man-made signals. It has been demonstrated that structured signals can be acquired with just a small number of linear measurements, on the order of the signal complexity. In practice, this enables lower sampling rates that can be more easily achieved by current hardware designs. The primary bottleneck that limits ADC sampling rates is quantization, i.e., higher bit-depths impose lower sampling rates. Thus, the decreased sampling rates of CS ADCs accommodate the otherwise limiting quantizer of conventional ADCs. In this thesis, we consider a different approach to CS ADC by shifting towards lower quantizer bit-depths rather than lower sampling rates. We explore the extreme case where each measurement is quantized to just one bit, representing its sign. We develop a new theoretical framework to analyze this extreme case and develop new algorithms for signal reconstruction from such coarsely quantized measurements. The 1-bit CS framework leads us to scenarios where it may be more appropriate to reduce bit-depth instead of sampling rate. We find that there exist two distinct regimes of operation that correspond to high/low signal-to-noise ratio (SNR). In the measurement compression (MC) regime, a high SNR favors acquiring fewer measurements with more bits per measurement (as in conventional CS); in the quantization compression (QC) regime, a low SNR favors acquiring more measurements with fewer bits per measurement (as in this thesis). A surprise from our analysis and experiments is that in many practical applications it is better to operate in the QC regime, even acquiring as few as 1 bit per measurement. The above philosophy extends further to practical CS ADC system designs. We propose two new CS architectures, one of which takes advantage of the fact that the sampling and quantization operations are performed by two different hardware components. The former can be employed at high rates with minimal costs while the latter cannot. Thus, we develop a system that discretizes in time, performs CS preconditioning techniques, and then quantizes at a low rate.

This thesis is one part of a overall task of designing a module for frequency shift keying (FSK) to be used in an Ultra Wide Band (UWB) system. The FSK system has a Direct Digital Synthesizer (DDS) and Digital-to-Analog (DAC). The DACs differential current signals are directly fed to a RF (Radio Frequency) unit that generates the UWB RF signal. The focus of this thesis is on DAC while the DDS is developed in VHDL as another thesis work. This thesis demonstrates a low-power, ultra wide band 10 bit DAC with an update frequency of 24 MSPS(Mega Samples Per Second). The DAC uses a L-fold linear interpolation architecture. It includes a 16-tap voltage controlled delay line and a 10 bit binary-weighted DAC with a time interleaved structure. The linear interpolation technique improves the attenuation of mirror components and also reduces the glitch. This helps to relax the analog filter requirements and sometimes an off chip capacitor is enough as low pass filter. The attenuation of image components is doubled in decibels(dB) compared with that of conventional DAC. In this work various DAC architectures are studied. The current-steering DAC is chosen due to its high speed and high resolution. A binary weighted architecture is chosen to reduce the digital circuits. This helped in reducing the power consumption. The design and simulation is done with help of Cadence. The layout is done in Cadence Virtuoso and the DDS is integrated with the DAC. The chip is to be manufactured in 130 nm CMOS process.