Made available in DSpace on 2014-06-12T17:37:54Z (GMT). No. of bitstreams: 2 arquivo5366_1.pdf: 1972339 bytes, checksum: e5b3a59fb56a1a862b786b1c37e1e5a4 (MD5) license.txt: 1748 bytes, checksum: 8a4605be74aa9ea9d79846c1fba20a33 (MD5) Previous issue date: 2008 / Companhia Energética de Pernambuco / Os códigos corretores de erros quânticos estão sendo desenvolvidos com o intuito de aumentar a confiabilidade do hardware quântico. A maioria dos códigos quânticos conhecidos são códigos de bloco, tendo os primeiros códigos convolucionais quânticos surgido recentemente. Já bastante difundida na teoria da codificação clássica, a proteção desigual de erros (UEP - do inglês unequal error protection), ainda não foi estudada no contexto de códigos quânticos, sendo este o principal objetivo desta dissertação. Introduziremos o conceito do vetor de separação quântico e uma técnica de análise da característica UEP de códigos de bloco quânticos para canais de inversão de bit e canais de inversão de fase

While probabilistic neural networks are a staple of the neural network field, their study in the context of real hardware has been limited. Probabilistic spin logic entails the study of probabilistic neurons that have real hardware counterparts. This comes under a new effort, termed Purdue-P, whose goal it is to develop efficient, probabilistic neural network hardware to solve some of today’s most difficult problems. An important step in this effort has been the development of a website, purdue.edu/p-bit, to act as a “front page” for the effort. This website introduces the idea of probabilistic spin logic to newcomers, houses an online web simulator and blog, and provides instructions on how to access a powerful asynchronous p-computing co-processor through the cloud. The thoughts behind the flow of content, the web simulator, and cloud access of the co-processor constitute the crux of the thesis.

The past few years have brought a major surge in the volumes of collected data. More and more enterprises and research institutions find tremendous value in data analysis and exploration. Big Data analytics is used for improving customer experience, perform complex weather data integration and model prediction, as well as personalized medicine and many other services. Advances in technology, along with high interest in big data, can only increase the demand on data collection and mining in the years to come. As a result, and in order to keep up with the data volumes, data processing has become increasingly distributed. However, most of the distributed processing for large data is done by batch processing and interactive exploration is hardly an option. To efficiently support queries over large amounts of data, appropriate indexing mechanisms must be in place. This dissertation proposes an indexing and query processing framework that can run on top of a distributed computing engine, to support fast, interactive data explorations in data warehouses. Our data processing layer is built around bit-vector based indices. This type of indexing features fast bit-wise operations and scales up well for high dimensional data. Additionally, compression can be applied to reduce the index size, and thus utilize less memory and network communication. Our work can be divided into two areas: index compression and query processing. Two compression schemes are proposed for sparse and dense bit-vectors. The design of these encoding methods is hardware-driven, and the query processing is optimized for the available computing hardware. Query algorithms are proposed for selection, aggregation, and other specialized queries. The query processing is supported on single machines, as well as computer clusters.

Learning a predictive model for a large scale real-world problem presents several challenges: the choice of a good feature set and a scalable machine learning algorithm with small generalization error. A support vector machine (SVM), based on statistical learning theory, obtains good generalization by restricting the capacity of its hypothesis space. A SVM outperforms classical learning algorithms on many benchmark data sets. Its excellent performance makes it the ideal choice for pattern recognition problems. However, training a SVM involves constrained quadratic programming, which leads to poor scalability. In this dissertation, we propose several methods to improve a SVM's scalability. The evaluation is done mainly in the context of a plankton recognition problem. One approach is called active learning, which selectively asks a domain expert to label a subset of examples from a lot of unlabeled data. Active learning minimizes the number of labeled examples needed to build an accurate model and reduces the human effort in manually labeling the data. We propose a new active learning method "Breaking Ties" (BT) for multi-class SVMs. After developing a probability model for multiple class SVMs, "BT" selectively labels examples for which the difference in probabilities between the predicted most likely class and second most likely class is smallest. This simple strategy required several times less labeled plankton images to reach a given recognition accuracy when compared to random sampling in our plankton recognition system. To speed up a SVM's training and prediction, we show how to apply bit reduction to compress the examples into several bins. Weights are assigned to different bins based on the number of examples in the bin. Treating each bin as a weighted example, a SVM builds a model using the reduced-set of weighted examples.

Recently short word-length (normally 1 bit or bits) processing has become a promising technique. However, there are unresolved issues in sigma-delta modulation, which is the basis for 1b/2b systems. These issues hindered the full adoption of single-bit techniues in industry. Among these problems is the stability of high-order modulators and the limit cycle behaviour. More importantly, there is no adaptive LMS structure of any kind in 1b/2b domain. The challenge in this problem is the harsh quantization that prevents straightforward LMS application. In this thesis, the focus has been made on three axes: designing new single-bit DSP applications, proposing novel approaches for stability analysis, and tacking the unresolved problems of 1b/2b adaptive filtering. Two structures for 1b digital comb filtering are proposed. A ternary DC blocker structure is also presented and performance is tested. We also proposed a single-bit multiplierless DC-blocking structure. The s tability of a single-bit high-order signma-delta modulator is studied under dc inputs. A new approach for stability analysis is proposed based on analogy with PLL analysis. Finally we succeeded in designing 1b/2b Wiener-like filtering and introduced (for the first time) three 1b/2b adaptive schemes.

<p>Test Tools are very important in the design of a system. They generally simulate a working environment, only at a higher</p><p>speed, or with less frequently occurring test cases. In the verification of protocols based on the Fibre Channel physical layer,</p><p>this becomes a necessity, as errors can be non-existent or very unusual in normal operating environments. Most systems need</p><p>to be able to handle these unexpected events nonetheless. Therefore, there is a need for a method of introducing these errors</p><p>in a controlled way.</p><p>A bit error generation and logging tool for two proprietary protocols based on the Fibre Channel physical layer has been</p><p>developed. The hardware platform consists mainly of a Virtex II Pro FPGA with accompanying I/O support. Control of the</p><p>hardware is handled by a graphical user interface residing on a PC. Communication between the hardware and the PC is</p><p>handled with a UART. The final implementation can handle four parallel one way links, or two full duplex links,</p><p>independently. This report describes the implementation and the necessary theoretical background for this.</p>

<p>This thesis is one part of a overall task of designing a module for frequency shift keying (FSK) to be used in an Ultra Wide Band (UWB) system. The FSK system has a Direct Digital Synthesizer (DDS) and Digital-to-Analog (DAC). The DACs differential current signals are directly fed to a RF (Radio Frequency) unit that generates the UWB RF signal.</p><p>The focus of this thesis is on DAC while the DDS is developed in VHDL as another thesis work. This thesis demonstrates a low-power, ultra wide band 10 bit DAC with an update frequency of 24 MSPS(Mega Samples Per Second). The DAC uses a L-fold linear interpolation architecture. It includes a 16-tap voltage controlled delay line and a 10 bit binary-weighted DAC with a time interleaved structure. The linear interpolation technique improves the attenuation of mirror components and also reduces the glitch. This helps to relax the analog filter requirements and sometimes an off chip capacitor is enough as low pass filter. The attenuation of image components is doubled in decibels(dB) compared with that of conventional DAC.</p><p>In this work various DAC architectures are studied. The current-steering DAC is chosen due to its high speed and high resolution. A binary weighted architecture is chosen to reduce the digital circuits. This helped in reducing the power consumption. The design and simulation is done with help of Cadence. The layout is done in Cadence Virtuoso and the DDS is integrated with the DAC. The chip is to be manufactured in 130 nm CMOS process.</p>

<p>This thesis is divided into two parts. In the first part we focus mainly on certain aspects of the AdS/CFT correspondence. The AdS/CFT correspondence is a proposed duality between Type IIB superstring theory on AdS₅ xS⁵ and N = 4 supersymmetric Yang-Mills theory. In the BMN limit string states located in the center of AdS₅ rotate quickly around the equator of the S⁵ and correspond, in the dual theory, to operators constructed as long chains of sub-operators. This structure of the operators can be formulated as a spin chain and by using the Bethe ansatz their properties can be obtained by solving a set of Bethe equations. Having infinitely many sub-operators, there are methods for solving the Bethe equations in certain sectors. In paper III finite size corrections to the anomalous dimensions in the SU(2) sector are calculated to leading order.</p><p>Inspired by the chain structure of the corresponding operators, the theory of string bits treats the strings as a discrete sets of points. This theory suffers from the problem of fermion doubling, a general pathology of fermions on a lattice. In paper II we show how to adjust the theory in order to avoid this problem and, in fact, use the fermion doubling to our advantage. The second part of the thesis studies the low energy behaviour of SU(2) Yang-Mills theory in 4 space-time dimensions. In paper I we perform numerical calculations on an effective action for this theory. We propose the existence of a knotted trajectory within the dynamics of this effective action.</p>

In this study, an improved bit-array representation method for structural topology optimization using the Genetic Algorithm (GA) is proposed. The issue of representation degeneracy is fully addressed and the importance of structural connectivity in a design is further emphasized. To evaluate the constrained objective function, Deb's constraint handling approach is further developed to ensure that feasible individuals are always better than infeasible ones in the population to improve the efficiency of the GA. A hierarchical violation penalty method is proposed to drive the GA search towards the topologies with higher structural performance, less unusable material and fewer separate objects in the design domain in a hierarchical manner. Numerical results of structural topology optimization problems of minimum weight and minimum compliance designs show the success of this novel bit-array representation method and suggest that the GA performance can be significantly improved by handling the design connectivity properly. / Singapore-MIT Alliance (SMA)

In this paper, we develop a novel index structure to support efficient approximate k-nearest neighbor (KNN) query in high-dimensional databases. In high-dimensional spaces, the computational cost of the distance (e.g., Euclidean distance) between two points contributes a dominant portion of the overall query response time for memory processing. To reduce the distance computation, we first propose a structure (BID) using BIt-Difference to answer approximate KNN query. The BID employs one bit to represent each feature vector of point and the number of bit-difference is used to prune the further points. To facilitate real dataset which is typically skewed, we enhance the BID mechanism with clustering, cluster adapted bitcoder and dimensional weight, named the BID⁺. Extensive experiments are conducted to show that our proposed method yields significant performance advantages over the existing index structures on both real life and synthetic high-dimensional datasets. / Singapore-MIT Alliance (SMA)