With rising fuel prices, increasing electrification, and imminent fines on CO2 emission within the EU, the requirement for energy and cost efficient supply concepts is becomingmore and more important in the automotive industry. This thesis presents an assessmentof, and improvement for energy and cost efficient power supply concepts for low-end automotiveand light e-mobility electronic control units, containing small µCs, and analogand logic components. Specifically, linear regulators, synchronous and non-synchronous buck converters, andswitched capacitor converters are investigated and assessed theoretically. The mostpromising concept, namely a discrete buck converter, is further studied using theoreticalassessment, experiment, and simulations. The key result of this work is a concept for replacing commonly used linear regulatorsin small electronic control units (ECUs) by a more efficient supply with only a smallcost adder. Specifically, since no low-end switched converter ICs are available today, wedeveloped a buck converter with discrete control circuit. This concept provides a cheap,yet efficient alternative to linear regulators for a wide range of applications. In addition,the application of this concept is supported by component selection criteria, and also bythe developed simulation models.

In variable speed motor drive and uninterruptible power supply (UPS) applications, taditional method is to employ some kind of a modulation technique at a high frequency typically 6 kHz to 20 kHz range. In these modulation techniques, the switches are hard switched. The result is application of a series of pulses to the load, and if the load is inductive, sine wave current flows into the load. Hard and rapid switching causes a voltage waveform with a very high dv/dt (rate of change in voltage) causing high EMI problems, reduced life expectancy of the motor and additional losses. So a power supply generating pure sinusoidal voltage waveform is very desirable. In industry some low pass filters called sinusoidal filters, are used at the output of the inverters but this comes with additional cost and bulky filter elements. In this study, a novel approach for generating power level sinusoidal waveforms is proposed. The basic structure is a DC-DC converter that produces a rectified DC-link at its output and an H-bridge inverter that inverts the rectified sinusoids to form a sinusoidal voltage. Main advantages of the circuit are that the H-bridge inverter switches have no switching stresses, they are switched at low frequency so the reliability is increased. Throughout the study different circuit topologies have been investigated and the analysis of the chosen topologies is supported with computer simulations. The system is then set up in the laboratory. In order to prove of the concept, only a single phase inverter has been investigated at steady state conditions. Efficiency, distortion level, magnitude error and device stresses have been obtained. The results indicate that the proposed configuration is very promising.

Renewable power systems are becoming more affordable and provide better options than fossil-fuel generation, for not only the environment, but a benefit of a reduced cost of operation. Methods to optimize charging batteries from renewable technologies is an important subject for off-grid and micro-grids, and is becoming more relevant for larger installations. Overcharging or undercharging the battery can result in failure and reduction of battery life. The Arduino hybrid MPPT controller takes the advantage of solar and wind energy sources by controlling two systems simultaneously. The ability to manage two systems with one controller is better for an overall production of energy, cost, and manageability, at a minor expense of efficiency. The hybrid MPPT uses two synchronous buck DC-DC converters to control both wind and solar. The hybrid MPPT performed at a maximum of 93.6% efficiency, while the individual controller operated at a maximum 97.1% efficiency when working on the bench test. When designing the controller to manage power production from a larger generator, the inductor size was too large due to the frequency provided by the Arduino. A larger inductor means less allowable current to flow before the inductor becomes over saturated, reducing the efficiency of the controller. Utilizing a different microcontroller like the PIC16C63A produces a much faster frequency, which will reduce the inductor size needed and allow more current before over saturation.

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Cette thèse s'intéresse au pilotage des cycles limites pour une classe particulière de systèmes hybrides (SDH): les systèmes commutés cycliques. La thématique des SDH est née du constat d'insuffisance des modèles dynamiques classiques pour décrire les comportements lorsque des aspects évènementiels interviennent. Une classe particulièrement importante de SDH est formée par celle qui présente un régime permanent cyclique. Ces systèmes ont des points de fonctionnement non auto-maintenables: il n'existe pas de commande qui maintienne le système sur ce point. Le maintien n'est assuré qu'en valeur moyenne, en effectuant un cycle dans un voisinage du point par commutation des sous systèmes. L'établissement d'une loi de commutation pour cette classe de systèmes doit répondre aux objectifs de stabilité et de performance dynamique, mais doit également garantir la satisfaction de critères liés à la forme d'onde. A l'heure actuelle, peu de méthodes de commande prennent en compte le caractère cyclique du système. Les travaux de cette thèse ont pour objectif de développer des méthodes génériques et robustes pour piloter cette classe de systèmes. Les algorithmes proposés doivent également pouvoir être implémenté en temps réels. On modélise le système comme un système non - linéaire affine en la commande dont la loi de commande apparait dans le modèle. Ce type de modélisation permet d'envisager deux types de synthèse: l'une à base de commande prédictive et l'autre à base de commande optimale. Ce travail est validé par une partie applicative sur des manipulations dans le CRAN et dans des laboratoires du réseau d'excellence européenne HYCON dans le cadre duquel s'est déroulé cette étude / This work deals with limit cycle control for one particular class of hybrid dynamical systems (HDS): The cyclic switched systems. The HDS were born because the traditional dynamical models were not able to describe complex behaviors and most of all, behaviors with discontinuities. From an application point of view, one important class of HDS depicts a cyclic behavior in steady state. The main characteristic of these systems is that the operation point cannot be maintained: It does not exist a control that maintains the system on a desired operation point. However, this point can be obtained in average by turning into its neighborhood. Thus, a cycle is produced by switching among the system modes. A switched control law must satisfy stability and dynamic performance. Moreover, criteria related to the waveform must be verified. Nowadays, few methods take into account the cyclic behavior of the system. In this research, some generic methods are studied. They show good performance for controlling the cyclic switched systems. The proposed algorithms can be implemented in real-time. The approaches are based on an affine non-linear model of the system whose control explicitly appears. Two control methods are considered: i) A predictive control, ii) An optimal control. Since the predictive control is a good choice for tracking, it will be able to maintain the system in a cycle. The optimal control yields solutions that can be applied to the transients. Some experiments with both control methods applied to the power converters are shown. These tests were carried out not only in our laboratory (CRAN), but also in other laboratories as part of the HYCON excellence network

La sophistication grandissante des dispositifs intelligents ultra-portatifs, tels que les smartphones ou les tablettes,crée un besoin d'amélioration des performances des organes de conversion de puissance.La tendance des technologies d'acheminement de puissance évolue progressivement vers une fréquence plus élevée, une meilleure densité d'intégration et une plus grande flexibilité dans les schémas d'asservissement. La modulation dynamique de tension est utilisée dans les circuits intégrés de gestion de puissances(DVS PMICs)des transmetteurs RF alors que la modulation DVFS est utilisée dans les PMICs dédiées au CPUs et GPUs. Des DCDC flexibles et fonctionnant à haute fréquence constituent aujourd'hui la solution principale en conjonction avec des régulateurs à faible marge de tension (LDO).L'évolution vers des solutions à base de HFDCDC de faibles dimensions pose un défi sérieux en matière de 1)stabilité des boucles d'asservissement,2)de complexité des architectures de contrôle imbriquant des machines d'état asynchrones pour gérer une large dynamique de puissance de sortie et 3)de portabilité de la solutions d'une technologie à une autre.Les solutions les plus courantes atteignent aujourd'hui une gamme de 2 à 6 Mhz de fréquence de découpage grâce à l'usage de contrôleurs à hystérésis qui souffrent de la difficulté à contenir la fréquence de découpage lors des variations de la tension ou du courant en charge.Nous avons voulu dans ce travail étendre l'usage des méthodes de conception et de modélisation conventionnelles comme le modèle petit signal moyen, dans une perspective de simplification et de création de modèles paramétriques. L'objectif étant de rendre la technique de compensation flexible et robuste aux variations de procédés de fabrication ou bien aux signaux parasités inhérents à la commutation de puissance.Certes, le modèle moyen petit signal, au demeurant bien traité dans la littérature, réponds amplement à la problématique de compensation des DCDCs notamment quand la stabilité s'appuie sur le zéro naturel à haute fréquence inhérent à la résistance série ESR de la capacité de sortie, mais les HFDCDC actuels utilisent des capacités MLCC ayant une très faible ESR et font appel à des techniques de compensation paramétriques imbriquant le schéma de compensation dans la génération même du rapport cyclique. La littérature existante sur le fonctionnement de la machine d'état, se contente d'une description simpliste de convertisseurs PWM/PFM mais ne donne que très peu d'éléments sur la gestion des opérations synchrones/asynchrones alternant PWM,PFM,écrêtage de courant, démarrage ou détection de défaillance. Dans ce travail, notre études est axée sur les deux aspects suivants:1)La modélisation paramétrique et la compensation de la boucle d'asservissement de HFDCDC et 2)la portabilité de la conception de la machine d'états du contrôleur notamment lorsqu'elle intègre des transitions complexes entre les modes.Dans la première section, nous avons développé un modèle petit signal moyen d'un convertisseur Buck asservi en mode courant-tension et nous l'avons analysé pour faire apparaitre les contributions proportionnelle, intégrale et dérivé dans la boucle. Nous avons démontré la possibilité d'utiliser le retour en courant pour assurer l'amortissement nécessaire et la stabilité de la boucle pour une large dynamique de variations des conditions de charge.Dans la seconde section, nous avons développé une architecture de machine d'états sophistiquée basé sur la méthode d'Huffman avec un effort substantiel d'abstraction que nous a permis de la concevoir en description RTL pour une gestion fiable du fonctionnement asynchrone et temps réel.Notre contribution théorique a fait l'objet d'une réalisation d'un PMIC de test comportant deux convertisseurs Buck cadencés à 12MHz en technologie BiCMOS 0.5um/0.18um. Les performances clefs obtenues sont:une surtension de 50mV pendant 2us suite à l'application d'un échelon de courant de 300mA. / The continuous sophistication of smart handheld devices such as smartphones and tablets creates an incremental need for improving the performances of the power conversion devices. The trend in power delivery migrates progressively to higher frequency, higher density of integration and flexibility of the control scheme. Dynamic Voltage Scaling Power Management ICs (DVS PMIC) are now systematically used for powering RF Transmitters and DVFS PMICS using Voltage and Frequency scaling are used for CPUs and GPUs. Flexible High frequency (HF) DC/DC converters in conjunction with low dropout LDOs constitute the main solution largely employed for such purposes. The migration toward high frequency/small size DCDC solutions creates serious challenges which are: 1) the stability of the feedback loop across a wide range of loading voltage and current conditions 2) The complexity of the control and often-non-synchronous state machine managing ultra large dynamics and bridging low power and high power operating modes, 3) The portability of the proposed solution across technology processes.The main stream solutions have so far reached the range of 2 to 6 MHz operation by employing systematically sliding mode or hysteretic converters that suffer from their variable operating frequency which creates EMI interferences and lead to integration problems relative to on-chip cross-talk between converters.In this work we aim at extend the use of traditional design and modeling techniques of power converters especially the average modeling technique by putting a particular care on the simplification of the theory and adjunction of flexible compensation techniques that don't require external components and that are less sensitive to process spread, or to high frequency substrate and supply noise conditions.The Small Signal Average Models, widely treated in the existing literature, might address most needs for system modeling and external compensation snubber design, especially when aiming on the high frequency natural zero of the output capacitor. However, HFDCDC converters today use small size MLCC capacitors with a very low ESR which require using alternative techniques mixing the compensation scheme with the duty cycle generation itself. The literature often provides a simplistic state machine description such as PWM/PFM operations but doesn't cover combined architectures of synchronous / non synchronous mode operations such as PWM, PFM, Current Limit, Boundary Clamp, Start, Transitional and finally Fault or Protection modes.In our work, we have focused our study on two main axes: 1) The parametric modeling and the loop compensation of HFDCDC and 2) the scalability of the control state machine and mode inter-operation. In the first part, we provided a detailed small signal averaged model of the “voltage and current mode buck converter” and we depicted it to emphasize and optimize the contributions of the Proportional, Integral and Derivative feedback loops. We demonstrated the ability to use the current feedback to damp and stabilize the converter with a wide variety of loading conditions (resistive or capacitive). In the second part, we provided architecture of the mode control state machine with different modes like the PWM, PFM, soft-start, current limit,… .The technique we have used is inspired by Huffman machine with a significant effort to make it abstract and scalable. The state machine is implemented using RTL coding based on a generic and scalable approach.The theoretical effort has been implemented inside a real PMIC test-chip carrying two 12MHz buck converters, each employing a voltage and current mode feedback loop. The chip has been realized in a 0.5um / 0.18um BiCMOS technology and tested through a dedicate Silicon validation platform able to test the analog, digital and power sections. The key performance obtained is a 50mV load transient undershoot / overshoot during 2us following a load step of 300mA (slope 0.3A/ns).

In the fast growing field of Telecommunications, the back up DC power supply plays a vital role in powering the telecom equipment. This DC power supply is a combination of AC-DC Rectifier coupled with a battery bank to support the load when AC input is not available. Figures 0.1 and 0.2 show the line diagram of the DC power supply. The power supply is the most critical element in a telecom installation and it should be highly reliable in order to have un-interrupted service. (Fig) Besides reliability, power density and cost are the driving forces behind the success of a power supply in the market. Off late, the reach of telecom in the society is very wide covering remote villages and major metros. Given this environment, the power supply is exposed to extreme input conditions. It is desirable to design the power supply capable of withstanding wide AC input conditions. Another advantage is that the rectifier unit will keep the battery charged so that the battery will have long life. This thesis is aimed at designing a 1400W (56V/25A) telecom power supply, keeping in view of the issues expressed above. The aim is to design a Switched Mode Rectifier (SMR) that tolerate wide input voltage variations (90Vac to 300Vac). In addition, the design covers unity input power factor, high efficiency (> 90%), high power density ( ), parallel operation and low cost ( ). Chapter 1 of this thesis covers the context and motivation of the work. Chapter 2 presents the design issues pertaining to power supplies. The normalized description of the power converters is presented. Such a description enables one to compare several circuit topologies in order to make effective design decisions. In a similar way the effectiveness of the switches and mgnetics are presented to enable design decisions in the output stage of the rectifier. Chapter 3 presents the design of the 1400W telecom power supply, keeping in view of the stated specifications. The performance results of the converter are presented in Chapter 4. All the design goals have been met. The design exercise has also given insights into possible further improvements. Contributions from this work and course of future development work are indicated in the concluding chapter.