One of the fundamental characteristics of the microprocessor application is its property of dynamic load change. Although idle most of the time, it wakes up in nanoseconds to support sudden workload demands, which are becoming increasingly severe in today's multi-core processors with large core count. From the standpoint of its voltage regulator (VR) design, it must have very good efficiency at light loads, while also supporting a very fast transient response. Thus, the variable-frequency constant on-time current-mode (COTCM) control scheme is widely used in the VRs, as it can automatically reduce its switching frequency during light-load conditions. But, from transient point of view, it has some limitations in response to heavy-load demands by microprocessors; this is resolved by adding different nonlinear controls in state-of-the-art control schemes. These nonlinear controls are difficult to optimize for the widely variable transient conditions in processors. Another major issue for this ripple-based COTCM control is that when the combined inductor-current ripple in multiphase operation becomes zero because of the ripple-cancellation effect, COTCM loses its controllability. Therefore, the goal of this research is to discover a new adaptive COT control scheme that is concurrently very efficient at light-load conditions and also provides a fast and optimized transient response without adding any nonlinear control; hence providing a complete solution for today's high-performance microprocessors. Firstly, the overview of state-of-the-art COTCM control is discussed in detail, and its limitations are analyzed. Analysis shows that one issue plaguing the COTCM control is its slow transient response in both single and multiphase operation. In this context, two methods have been proposed to improve the transient performance of conventional COTCM control in single and multiphase operations. These two methods can effectively reduce the output capacitor count in system, but the ripple-cancellation and phase overlapping issues in multiphase operation are yet to be improved. This provides motivation to search for a new COT control technique that can resolve all these problems together. Therefore, a new concept of inverse charge constant on-time (IQCOT) control is proposed to replace the conventional ripple-based COTCM; the goals are to improve noise immunity at the ripple-cancellation point without adding any external ramp into the system, and to improve the load step-up transient performance in multiphase operation by achieving natural and linear pulse overlapping without adding any nonlinear control. Additionally, the transient performance of the proposed IQCOT has been further improved by naturally increasing or decreasing the TON time during the load step-up or step-down transient period without adding any nonlinear control. As this transient property is inherent in proposed IQCOT control, it is adaptive to the widely variable transient requirements of processors, and always produces an optimized transient response. In order to design the proposed control with high bandwidth for supporting fast transient response, an accurate high-frequency small-signal model needs to be derived. Therefore, a high-frequency model for the proposed IQCOT control is derived using the describing function method. The model is also verified by simulation and hardware results in different operating conditions. From the derived model it is found that the quality factor (Q) of one double-pole set varies with changes in duty cycle. To overcome this challenge, an auto-tuning method for Q-value control is also proposed in this dissertation. / Ph. D.

Power consumption of smart cameras varies significantly between sleep mode and active mode, and a smart camera operates in sleep mode for 80 — 90% of time for typical use. To prolong the battery life of smart cameras, it is essential to increase the power converter efficiency for light load, while being able to manage heavy load. The power stage of traditional buck converter is optimized for maximum load, at the cost of light-load efficiency. Wei proposed a multiphase buck converter incorporating the baby-buck concept and optimum number of phases (ONP) control. This thesis research investigated Wei's multiphase buck converter to improve the light-load efficiency for smart cameras as the target application. The proposed two-phase buck converter aims to provide power for microprocessors of smart cameras. The input voltage of the converter is 5 V DC, and the output voltage is 1.2 V DC with power dissipation range of 25 mA (30 mW) for light load and 833 mA (1 W) for heavy load. Three methods are considered to improve light-load efficiency: adopting baby-buck concept, adapting ONP control for low-power range, and implementing a pulse frequency modulation (PFM) control scheme with discontinuous conduction mode (DCM) to lower switching frequency. The first method is to adopt the baby-buck concept through power stage design of each phase to optimize efficiency for a specific load range. The baby-buck phase is optimized for light load and the heavy-load phase is designed to handle the processors maximum power consumption. The second method performs phase selection from sensed load current information. Rather than have all phases active for heavy-load as in ONP control, optimum phase selection (OPS) control is introduced to adaptively select between phases based on load current. Due to low-power constraints, OPS is more efficient for the medium to heavy-load range. The transition between phases due to load change is also investigated. The third and final method implements PFM control with DCM to lower switching frequency and reduce switching and driving losses under light load. PFM is accomplished with a constant on-time (COT) valley current mode controller, which uses the inductor current information and output voltage to generate switching signals for both the top and bottom switches. The baby-buck phase enters DCM to lower switching frequency under very light load, while the heavy-load phase remains in continuous conduction mode (CCM) throughout its load range. The proposed two-phase buck converter is designed and prototyped using discrete components. Efficiency of the two-phase converter and a power loss breakdown for each block in the control scheme were measured. The efficiency ranges from 64% to 81% for light load ranging of 30 mW to 200 mW, and the efficiency ranges from 81% to 88% for heavy load ranging from 200 mW to 1 W. The majority loss is due to controllers, which are responsible for 37 % (8.6 mW) for light load of 60 mW and for 10.9 % (9 mW) for heavy load of 600 mW. The gate driver loss is considerable for heavy load of 600 mW, consuming 11.9% (9.8mW). The converter has a 10 mV overshoot voltage for a load step-down from 225 mA to 25 mA, and it has 65 mV overshoot voltage for a load step-up from 25 mA to 225 mA. Although, a fair comparison is difficult due to use of discrete parts for OPS control, the proposed converter shows reasonably good efficiency and performance. / Master of Science

In order to extend the battery life of smart cameras, it is essential to increase the efficiency of power converters, especially at light load. This thesis research investigated a power converter to supply power for the microprocessor of a smart camera. The input voltage of the converter is 5 V, and the output voltage is 1.2 V with the load ranging from 10 mA (12 mW) to 1200 mA (1440 mW). The conventional buck converter is typically optimized for high efficiency at maximum load at the cost of light-load efficiency. A converter is investigated in this thesis to improve light load efficiency, while being able to handle heavy load, to prolong the battery life of smart cameras. The proposed converter employs two modes, a baby-buck mode and a heavy-load mode, in which each mode is optimized for its respective load range to achieve high efficiency throughout entire range. The heavy-load mode converter adopts the conventional synchronous buck approach, as it generally achieves high efficiency at heavy load. However, the synchronous buck approach is inefficient at light load due to the large switching, driving, and controller losses. The proposed baby-buck mode converter employs the following schemes or technique to reduce those losses. First, the baby buck mode converter adopts pulse frequency modulation (PFM) with discontinuous conduction mode (DCM) to lower the switching frequency at light load, so frequency-dependent switching and driving losses are reduced. Second, a simple control scheme, constant on-time V2 control, is adopted to simplify the controller and hence minimize the controller power dissipation. Third, the top switch of the baby-buck mode uses a small MOSFET, which is optimized for light load, and the bottom switch uses Schottky diode in lieu of a MOSFET to simplify the COT V2 controller. Fourth, the proposed converter combines the heavy-load and baby-buck mode converter into a single converter with a shared inductor, capacitors, and the feedback controller to save space. Finally, a simple and low power feedback controller with an optimum mode selector, a COT V 2 controller, and gate drivers are designed. The optimum mode selector selects an appropriate mode based on the load condition, while shutting down the opposing mode. The proposed converter was fabricated in CMOS 0.25 µm technology in two phases. Phase 1 contains design of the proposed converter with open loop, and its functionality is verified through measurements of test chips. Phase 2 includes the entire converter design with the feedback controller. Since the test chips of phase 2 are not delivered, yet, its functionality during the steady state and transient responses are verified through simulations. Simulation results indicate that the efficiency of the proposed converter ranges from 74% to 93% at 12 mW and 1440 mW, respectively. This result demonstrates that the proposed converter can achieve higher efficiency for the entire load range when compared to an off-the-shelf synchronous buck converters. / Master of Science

This dissertation focuses on the development of low-temperature co-fired ceramics (LTCC) technology for power converter magnetics integration. Because magnetic samples must be fabricated with thick conductors for power applications, the conventional LTCC process is modified by cutting trenches in the LTCC tapes where conductive paste is filled to produce thick conductors to adapt to this requirement. Characterization of the ceramic magnetic material is performed, and an empirical model based on the Steinmetz equation is developed to help in the estimation of losses at frequencies between 1 MHz to 4 MHz, operating temperature between 25 °C and 70 °C, DC pre-magnetization from 0 A/m to 1780 A/m, and AC magnetic flux densities between 5 mT to 50 mT. Temperature and DC pre-magnetization dependence on Steinmetz exponents are included in the model to describe the loss behavior. In the development of the LTCC chip inductor, various geometries are evaluated. Rectangular-shaped conductor geometry is selected due to its potential to obtain a much smaller footprint, as well as the likelihood of having lower losses than almond-shaped conductors with the same cross-sectional area, which are typically a result of screen printing. The selected geometry has varying inductance with varying current, which helps improve converter efficiency at light load. The efficiency at a light-load current of 0.5 A can be improved by 30 %. Parametric variation of inductor geometry is performed to observe its effect on inductance with DC current as well as on converter efficiency. An empirical model is developed to describe the change in inductance with DC current from 0 A to 16 A for LTCC planar inductors fabricated using low-permeability tape with conductor widths between 1 mm to 4 mm, conductor thickness 180 μm to 550 μm, and core thickness 170 μm to 520 μm. An inductor design flow diagram is formulated to help in the design of these inductors. Configuring the inductor as the substrate carrying the semiconductor and the other electronic components is a next step to freeing the surface area of the bulky component and improving the power density. A conductive shield is introduced between the circuitry and the magnetic substrate to avoid adversely affecting circuit operation by having a magnetic substrate in close proximity to the circuitry. The shield helps reduce parasitic inductances when placed in close proximity to the circuitry. A shield thickness in the range of 50 μm to 100 μm is found to be a good compromise between power loss and parasitic inductance reduction. The shield is effective when its conductivity is above 10⁷ S/m. When a shield is introduced between the inductor substrate and the circuitry, the sample exhibits a lower voltage overshoot (47 % lower) and an overall higher efficiency (7 % higher at 16 A), than an inductor without a shield. A shielded active circuitry placed on top of an inductive substrate performs similarly to a shielded active circuitry placed side-by-side with the inductor. Using a floating shield for the active circuitry yields a slightly better performance than using a grounded shield. / Ph. D.

The need for high performance circuits in systems with low-voltage and low-power requirements has exponentially increased during the few last years due to the sophistication and miniaturization of electronic components. Most of these circuits are required to have a very good efficiency behavior in order to extend the battery life of the device. This dissertation addresses two important topics concerning very high efficiency circuits with very high performance specifications. The first topic is the design and implementation of class D audio power amplifiers, keeping their inherent high efficiency characteristic while improving their linearity performance, reducing their quiescent power consumption, and minimizing the silicon area. The second topic is the design and implementation of switching voltage regulators and their controllers, to provide a low-cost, compact, high efficient and reliable power conversion for integrated circuits. The first part of this dissertation includes a short, although deep, analysis on class D amplifiers, their history, principles of operation, architectures, performance metrics, practical design considerations, and their present and future market distribution. Moreover, the harmonic distortion of open-loop class D amplifiers based on pulse-width modulation (PWM) is analyzed by applying the duty cycle variation technique for the most popular carrier waveforms giving an easy and practical analytic method to evaluate the class D amplifier distortion and determine its specifications for a given linearity requirement. Additionally, three class D amplifiers, with an architecture based on sliding mode control, are proposed, designed, fabricated and tested. The amplifiers make use of a hysteretic controller to avoid the need of complex overhead circuitry typically needed in other architectures to compensate non-idealities of practical implementations. The design of the amplifiers based on this technique is compact, small, reliable, and provides a performance comparable to the state-of-the-art class D amplifiers, but consumes only one tenth of quiescent power. This characteristic gives to the proposed amplifiers an advantage for applications with minimal power consumption and very high performance requirements. The second part of this dissertation presents the design, implementation, and testing of switching voltage regulators. It starts with a description and brief analysis on the power converters architectures. It outlines the advantages and drawbacks of the main topologies, discusses practical design considerations, and compares their current and future market distribution. Then, two different buck converters are proposed to overcome the most critical issue in switching voltage regulators: to provide a stable voltage supply for electronic devices, with good regulation voltage, high efficiency performance, and, most important, a minimum number of components. The first buck converter, which has been designed, fabricated and tested, is an integrated dual-output voltage regulator based on sliding mode control that provides a power efficiency comparable to the conventional solutions, but potentially saves silicon area and input filter components. The design is based on the idea of stacking traditional buck converters to provide multiple output voltages with the minimum number of switches. Finally, a fully integrated buck converter based on sliding mode control is proposed. The architecture integrates the external passive components to deliver a complete monolithic solution with minimal silicon area. The buck converter employs a poly-phase structure to minimize the output current ripple and a hysteretic controller to avoid the generation of an additional high frequency carrier waveform needed in conventional solutions. The simulated results are comparable to the state-of-the-art works even with no additional post-fabrication process to improve the converter performance.

Synchronous buck converter based multiphase architectures are evaluated to determine whether or not the most widespread voltage regulator topology can meet the power delivery requirements of next generation computer microprocessors. According to the prognostications, the load current will rise to 200A along with the decrease of the supply voltage to 0.5V and staggering tight dynamic and static load line tolerances. In view of these demands, researchers face serious challenges to bring forth compliant solutions that can further offer acceptable conversion efficiencies and minimum mainboard area occupancy. Among the most prominent investigation fronts are those surveying fundamental technology improvements aiming at making power semiconductor devices more effective at high switching frequency. The latter is of critical importance as the increase of the switching frequency is fundamentally recognized as the way forward to enhance power density conversion. Provided that switching losses must be kept low to enable the miniaturization of the filter components, one primary goal is to cope with semiconductor and system integration technologies enabling fast dynamic operation of ultra-low ON resistance power switches. This justifies the main focus of this thesis work, centered around a comprehensive analysis of the MOSFET switching behavior in the synchronous buck converter. The MOSFETs dynamic operation, far from being well describable with the traditional clamped inductive hard-switching mode, is strongly influenced by a number of frequently ignored linear and nonlinear parasitic elements that must be taken into account in order to fully predict real switching waveforms, understand their dynamics, and most importantly, identify and quantify the related mechanisms leading to heat generation. This will be revealed from in-depth investigations of the switched converter under fast switching speeds and heavy load. Recognizing the key relevance of appropriate modeling tools that support this task, the second focal point of the thesis aims at developing a number of suitable models for the switching analysis of power MOSFETs. Combined with a series of design guidelines and optimization procedures, these models form the basis of a proposed methodological approach, where numerical computations replace the usually enormous experimental effort to elucidate the most effective pathways towards reducing power losses. This gives rise to the concept referred to as virtual design loop, which is successfully applied to the development of a new power MOSFET technology offering outstanding dynamic and static performance characteristics. From a system perspective, the limits of the power density conversion will be explored for this and other emerging technologies that promise to open up a new paradigm in power integration capabilities.

In the thesis, we apply the state average method to model the time-average linear dynamic equation, which is used to design a gain scheduled linear quadratic optimal controller. Because the standard modulation method of the twin-buck converter is PFM(Pulse-Frequency Modulation) and twin-buck converter owns the soft-switching characteristic, the voltage step-down ratio, that is, control force can not be lowered less than 0.5. For expanding the range of control force of converter, we modulate the converter by means of mixed modulation of PWM/PFM. With the former odulation method, we have to calculate the discharging time of synchronous switch taken by controller to achieve zero-voltage-transition (ZVT). In the last part of this thesis, we verify the practicability of the controller and modulation method through soft simulation coded by MATLAB and hardware implementation of FPGA driven by Verilog.

In the current and next generation automotive telematic platforms, high demands are put on high efficiency power supplies. This thesis investigates different switch mode power converter solutions that operates with high efficiency for both low and high power loads. A market survey was conducted alongside meetings with ACTIA Nordic and their subcontractors. Three solutions from the market survey were selected for further investigation. One solution from the investigation was selected and implemented as a demonstration platform for further testing. The result shows a full test sequence for the designed power supply solution.

This thesis evaluate the state of art ROHM SCT3080KR silicon carbide mosfet in a synchronous buck converter. The converter was using the ROHM P02SCT3040KR-EVK-001 evaluation board for driving the mosfets in a half bridge configuration. Evaluation of efficiency, waveforms, temperature and a theoretical comparison between a silicon mosfet (STW12N120K5) is done. For the efficiency test the converter operate at 200 V input voltage and 100 V output voltage at output currents of 7 A to 12 A, this operation was tested at switching frequencies of 50 kHz, 80 kHz and 100 kHz. The result of the efficiency test showed an efficiency of 98-97 % for 50 kHz, 97.7-96.4 % for 80 kHz and 97-96.2 % for the 100 kHz test. The temperature test shows a small difference in comparison of the best case scenario and the worst case scenario, temperature ranges from 25.5 to 33.5 °C for the high side mosfet while the low side mosfet temperature ranges from 29.8 to 35 °C. The waveform test was conducted at 50 kHz and 100 kHz for output currents of 4 A and 12 A (at 200 V input and 100 V output). The result of the waveform test shows a rise and fall time of the voltages in range of 10-12 ns while the current rise and fall time was 16 ns for the 4 A test and 20 ns for the 12 A test. Overall SiC mosfet show a clear advantage over silicon mosfet in terms of efficiency and high power capabilities.

This paper presents the design and development of a novel Arc Welding Power Supply utilizing a modified two-switch forward converter topology. The proposed design improves the power quality by improving power factor to near unity and reducing total harmonic distortion. State space analysis of the proposed circuit showed that the circuit followed a boost-buck input output relationship. Simulation of the circuit was first implemented in LTspice to verify the functionality of the new topology. Hardware implementation of the proposed design was built on a scaled-down prototype for a proof-of-concept of the new topology. The prototype specifications were created for a 5A, 20V output with a 20-24V, 60Hz input. This project demonstrated that the proposed new topology was successful in obtaining a near unity power factor and a total harmonic distortion of less than 2%. Additionally, the prototype followed the simulation and calculations of a boost-buck function while varying duty cycle, and the final measurements aligned well with waveforms from the simulation.