The bandwidth demands of modern computing systems have been continually increasing and the recent focus on parallel processing will only increase the demands placed on data communication circuits. As data rates enter the multi-Gb/s range, serial data communication architectures become attractive as compared to parallel architectures. Serial architectures have long been used in fibre optic systems for long-haul applications, however, in the past decade there has been a trend towards multi-Gb/s backplane interconnects. The integration of clock and data recovery (CDR) circuits into monolithic integrated circuits (ICs) is attractive as it improves performance and reduces the system cost, however it also introduces new challenges, one of which is robustness. In serial data communication systems the CDR circuit is responsible for recovering the data from an incoming data stream. In recent years there has been a great deal of research into integrating CDR circuits into monolithic ICs. Most research has focused on increasing the bandwidth of the circuits, however in order to integrate multi-Gb/s CDR circuits robustness, as well as performance, must be considered. In this thesis CDR circuits are analyzed with respect to their robustness. The phase detector is a critical block in a CDR circuit and its robustness will play a significant role in determining the overall performance in the presence of process non-idealities. Several phase detector architectures are analyzed to determine the effects of process non-idealities. Static phase offsets are introduced as a figure of merit for phase detectors and a mathematical framework is described to characterize the negative effects of static phase offsets on CDR circuits. Two approaches are taken to improve the robustness of CDR circuits. First, calibration circuits are introduced which correct for static phase offsets in CDR circuits. Secondly, phase detector circuits are introduced which have been designed to optimize both performance and robustness. Several prototype chips which implement these schemes will be described and measured results will be presented. These results show that while CDR circuits are vulnerable to the effects of process non-idealities, there are circuit techniques which can mitigate many of these concerns.

In today’s communication devices, the need for high performance inductors is increasing as they are extensively used in RF integrated circuits (RFICs). This need is even more pronounced for variable inductors as they are widely required in tunable filters, voltage controlled amplifiers (VCO) and low noise amplifiers (LNA). For RFICs, the main tuning elements are solid state varactors that are used in conjunction with invariable inductors. However, they have limited linearity, high resistive losses, and low self resonant frequencies. This emphasizes the need for developing another tuning element that can be fabricated monolithically with ICs and can offer high range of tuning. Due to the ease of CMOS integration and low cost silicon based IC fabrication, the inductors currently used are a major source of energy loss, therefore driving the overall quality factor and performance of the chip down. During the last decade there has been an increase in research in RF MicroelectroMechanical Systems (RF MEMS) to develop high quality on chip tunable RF components. MEMS capacitors were initially proposed to substitute the existing varactors, however they can not be easily integrated on top of CMOS circuits. RF MEMS variable inductors have recently attracted attention as a better alternative. The research presented here explores using porous anodic alumina (PAA) in CMOS and MEMS fabrication. Due to its low cost and low temperature processing, PAA is an excellent candidate for silicon system integration. At first, PAA is explored as an isolation layer between the inductor and the lossy silicon substrate. Simulations show that although the dielectric constant of the PAA is tunable, the stress produced by the required thicker layers is problematic. Nevertheless, the use of PAA as a MEMS material shows much more promise. Tunable RF MEMS inductors based on bimorph sandwich layer of aluminum PAA and aluminum are fabricated and tested. A tuning range of 31% is achieved for an inductance variation of 5.8 nH to 7.6 nH at 3 GHz. To further improve the Q, bimorph layers of gold and PAA are fabricated on Alumina substrates. A lower tuning range is produced; however the quality factor performance is greatly improved. A peak Q of over 30 with a demonstrated 3% tuning range is presented. Depending on the need for either high performance or tunability, two types of tunable RF MEMS inductors are presented. Although PAA shows promise as a mechanical material for MEMS, the processing parameters (mainly stress and loss tangent) need to be improved if used as an isolation layer. To our knowledge, this is the first time this material has been proposed and successfully used as a structural material for MEMS devices and CMOS processes.

In the European research projects SIAM and 100GET, building blocks for 100Gbit Ethernet optical link have been implemented. Data are sent from a computer, modulated, converted to analog, mixed onto the RF-band, sent through an optical link, down-mixed, converted back to digital, demodulated and sent to a receiving computer. Signal Processing Devices Sweden AB is contributing to this project by their implementation PANDA. This thesis has been to study, as a proof of concept, and implement a prototype of PANDA as the component converting from digital to analog signal, the DAC, in 65nm SOI CMOS technology. The idea of the system is to use the concept of time interleaving, where two or more components interact by performing the same operations on a different set of data, ideally scaling the performance linearly with the amount of components used. This report presents design, implementation and verification at simulation level. It includes interfacing with off-chip components in low voltage specifications, clock generation, filtering and current-steered switches.

I 0.18 µm CMOS process har ett standardcells bibliotek med låg effektförbrukning implementerats. Cellerna har konstruerats och simulerats i Cadence och ett layoutprogram. Vid simulering av heladderare och D-vippor har effektförbrukningen och tider mätts upp och jämförts med varandra. Matningsspänningen varierade mellan 1 V och 1.8 V. In 0.18 µm CMOS process has a standard cell library with low power consumption been implemented. The cells have been made and simulated in Cadence and a layout program. At the simulation of the full adders and the D flip flops the power consumption and time have been estimated and compared. The power supply voltage varied between 1 V and 1.8 V. / A standard cell library with low power consumption has been implemented in a 0.18 mm CMOS process. The cells have been designed and simulated in Cadence and a layout program. During the simulation of the full adders and the D flip flops the power consumption and time have been estimated and compared. The power supply voltage varied between 1 V and 1.8 V.

This thesis investigates the possibility of realizing bandgap reference crcuits for processes having sub-1V supply voltage. With the scaling of gate oxide thickness supply voltage is getting reduced. But the threshold voltage of transistors is not getting scaled at the same rate as that of the supply voltage. This makes it difficult to incorporate conventional designs of bandgap reference circuits to processeshaving near to 1V supply voltage. In the first part of the thesis a comprehensive study on existing low voltage bandgap reference circuits is done. Using these ideas a low-power, low-voltage bandgap reference circuit is designed in the second part of the thesis work. The proposed bandgap reference circuit is capable of generating a reference voltage of 0.730V. The circuit is implemented in 0.18µm standard CMOS technology and operates with 0.9V supply voltage, consuming 5µA current. The circuit achieves 7 ppm/K of temperature coefficient with supply voltage range from 0.9 to 1.5V and temperature range from 0 to 60C.

The bandwidth demands of modern computing systems have been continually increasing and the recent focus on parallel processing will only increase the demands placed on data communication circuits. As data rates enter the multi-Gb/s range, serial data communication architectures become attractive as compared to parallel architectures. Serial architectures have long been used in fibre optic systems for long-haul applications, however, in the past decade there has been a trend towards multi-Gb/s backplane interconnects. The integration of clock and data recovery (CDR) circuits into monolithic integrated circuits (ICs) is attractive as it improves performance and reduces the system cost, however it also introduces new challenges, one of which is robustness. In serial data communication systems the CDR circuit is responsible for recovering the data from an incoming data stream. In recent years there has been a great deal of research into integrating CDR circuits into monolithic ICs. Most research has focused on increasing the bandwidth of the circuits, however in order to integrate multi-Gb/s CDR circuits robustness, as well as performance, must be considered. In this thesis CDR circuits are analyzed with respect to their robustness. The phase detector is a critical block in a CDR circuit and its robustness will play a significant role in determining the overall performance in the presence of process non-idealities. Several phase detector architectures are analyzed to determine the effects of process non-idealities. Static phase offsets are introduced as a figure of merit for phase detectors and a mathematical framework is described to characterize the negative effects of static phase offsets on CDR circuits. Two approaches are taken to improve the robustness of CDR circuits. First, calibration circuits are introduced which correct for static phase offsets in CDR circuits. Secondly, phase detector circuits are introduced which have been designed to optimize both performance and robustness. Several prototype chips which implement these schemes will be described and measured results will be presented. These results show that while CDR circuits are vulnerable to the effects of process non-idealities, there are circuit techniques which can mitigate many of these concerns.

In today’s communication devices, the need for high performance inductors is increasing as they are extensively used in RF integrated circuits (RFICs). This need is even more pronounced for variable inductors as they are widely required in tunable filters, voltage controlled amplifiers (VCO) and low noise amplifiers (LNA). For RFICs, the main tuning elements are solid state varactors that are used in conjunction with invariable inductors. However, they have limited linearity, high resistive losses, and low self resonant frequencies. This emphasizes the need for developing another tuning element that can be fabricated monolithically with ICs and can offer high range of tuning. Due to the ease of CMOS integration and low cost silicon based IC fabrication, the inductors currently used are a major source of energy loss, therefore driving the overall quality factor and performance of the chip down. During the last decade there has been an increase in research in RF MicroelectroMechanical Systems (RF MEMS) to develop high quality on chip tunable RF components. MEMS capacitors were initially proposed to substitute the existing varactors, however they can not be easily integrated on top of CMOS circuits. RF MEMS variable inductors have recently attracted attention as a better alternative. The research presented here explores using porous anodic alumina (PAA) in CMOS and MEMS fabrication. Due to its low cost and low temperature processing, PAA is an excellent candidate for silicon system integration. At first, PAA is explored as an isolation layer between the inductor and the lossy silicon substrate. Simulations show that although the dielectric constant of the PAA is tunable, the stress produced by the required thicker layers is problematic. Nevertheless, the use of PAA as a MEMS material shows much more promise. Tunable RF MEMS inductors based on bimorph sandwich layer of aluminum PAA and aluminum are fabricated and tested. A tuning range of 31% is achieved for an inductance variation of 5.8 nH to 7.6 nH at 3 GHz. To further improve the Q, bimorph layers of gold and PAA are fabricated on Alumina substrates. A lower tuning range is produced; however the quality factor performance is greatly improved. A peak Q of over 30 with a demonstrated 3% tuning range is presented. Depending on the need for either high performance or tunability, two types of tunable RF MEMS inductors are presented. Although PAA shows promise as a mechanical material for MEMS, the processing parameters (mainly stress and loss tangent) need to be improved if used as an isolation layer. To our knowledge, this is the first time this material has been proposed and successfully used as a structural material for MEMS devices and CMOS processes.

X-ray imaging has become one of the most pervasive and effective means of diagnosis in medical clinics today. As more imaging systems transition to digital modes of capture and storage, new applications of x-ray imaging, such as tomosynthesis, become feasible. These new imaging modalities have the potential to expose patients to large amounts of radiation so the necessity to use sensitive imagers that reduce dose and increase contrast is essential. An experimental design that utilizes laterally oriented detectors and amorphous semiconductors on crystalline silicon substrates has been undertaken in this study. Emphasis on fabricating a device suitable for medical x-ray imaging is the key principle throughout the design process. This study investigates the feasibility and efficiency of a new type of x-ray imager that combines the high speed, low noise, and potential complexity of CMOS circuit design with the high responsivity, large area uniformity, and flexibility of amorphous semiconductors. Results show that the design tradeoffs made in order to create a low cost, high fill factor, and high speed imager are realistic. The device exhibits good responsively to optical light, possesses a sufficient capacitive well, and maintains CMOS characteristics. This study demonstrates that with sufficient optimization it may be possible to design and deploy real time x-ray system on chip imagers similar to those used in optical imaging.

CMOS imagers are replacing CCD imagers in many applications and will continue to make new applications possible. CMOS imaging offers lower cost implementations on standard CMOS processes which allow for mixed signal processing on-chip. A system-on-a-chip approach offers the ability to perform complex algorithms faster, in less space, and with lower power and noise. Our transform imager is an implementation of a mixed focal plane and peripheral computation imager which allows high fill factor with high computational rates at low power. However, in order to use the technology effectively a need to verify and further understand the behavior and of the pixel elements in this transform imager was needed. This thesis presents a study of the pixel elements and mismatches and errors in the pixel array of this imager. From there, a discussion about removing offsets and an implementation of a circuit to remove the largest offsets is shown. To further enhance performance, initial work to develop light adaptive readout circuits is presented. Finally, an overview is given of a newly designed one-megapixel transform imager with many design improvements.

Operation of SiGe BiCMOS Technology Under Extreme Environments Tianbing Chen 96 pages Directed by Dr. John D. Cressler "Extreme environment electronics" represents an important niche market and spans the operation of electronic components in surroundings lying outside the domain of conventional commercial, or even military specifications. Such extreme environments would include, for instance, operation to very low temperatures (e.g., to 77 K or even 4.2 K), operation to very high temperatures (e.g., to 200 C or even 300 C), and operation in a radiation-rich environment (e.g., space). The suitability of SiGe BiCMOS technology for extreme environment electronics applications is assessed in this work. The suitability of SiGe HBTs for use in high-temperature electronics applications is first investigated. SiGe HBTs are shown to exhibit sufficient current gain, frequency response, breakdown voltage, achieve acceptable device reliability, and improved low-frequency noise, at temperatures as high as 200-300 C. A comprehensive investigation of substrate bias effects on device performance, thermal properties, and reliability of vertical SiGe HBTs fabricated on CMOS-compatible, thin-film SOI, is presented. The impact of 63 MeV protons on these vertical SiGe HBTs fabricated on a CMOS-compatible SOI is then investigated. Proton irradiation creates G/R trap centers in SOI SiGe HBTs, creating positive charge at the buried oxide interface, effectively delaying the onset of the Kirk effect at high current density, which increases the frequency response of SOI SiGe HBTs following radiation. The thermodynamic stability of device-relevant epitaxial SiGe strained layers under proton irradiation is also investigated using x-ray diffraction techniques. Irradiation with 63 MeV protons is found to introduce no significant microdefects into the SiGe thin films, regardless of the starting stability condition of the SiGe film, and thus does not appear to be an issue for the use of SiGe HBT technology in emerging space systems. CMOS device reliability for emerging cryogenic space electronics applications is also assessed. CMOS device performance improves with cooling, however, CMOS device reliability becomes worse at decreased temperatures due to aggravated hot-carrier effects. The device lifetime is found to be a strong function of gate length, suggesting that design tradeoffs are inevitable.