Estructures ressonants en forma de biga (p.e. ponts o palanques) són molt interessants com a element transductor en sensors físics, químics i biològics basats en sistemes micro-/nanoelectromecànics (M-/NEMS) degut a la seva simplicitat, al gran rang de dominis que poden sensar, i a la seva extremada alta sensibilitat. Aquesta tesis està focalitzada en el disseny, fabricació i caracterització de CMOS-MEMS monolítics basats en bigues ressonants a escala sub-micromètrica per a la seva utilització en la detecció ultra sensible de massa amb un dispositiu portable. Els ressonadors operen en mode dinàmic on la massa es mesurada com un canvi de la seva freqüència de ressonància que és induïda electrostàticament i llegida d'una forma capacitiva mitjançant un circuit CMOS integrat monolíticament. Dues aproximacions tecnològiques diferents són considerades per tal de fabricar bigues ressonants a escala sub-micromètrica sobre xips CMOS prèviament processats, possibilitant una integració monolítica: (i) post processant els xips CMOS amb tècniques de nano fabricació per obtenir les estructures ressonants o (ii) definint els ressonadors al mateix temps que els circuits CMOS. Per les dues aproximacions, es presenten dispositius de metall i de polysilici amb sensibilitats de massa sense precedents (per a sensors CMOS monolítics) dins el rang dels atto-/zeptograms. Es presenta una comparativa dels resultats aconseguits mitjançant les dues aproximacions tecnològiques.Es dissenyen circuits de lectura CMOS d'alta sensibilitat per amplificar el corrent capacitiu amb guanys de transimpedància (utilitzant una tecnologia comercial CMOS 0.35-μm) de fins a 120 dBΩ a 10 MHz possibilitant la detecció del desplaçament del ressonador amb resolucions de fins a ~10 fm/√Hz semblants a les obtingudes pels millors sistemes de detecció òptics reportats i sense la necessitat d'un equipament complexa. Es presenta la caracterització elèctrica, a l'aire i al buit, de dispositius CMOS-MEMS fabricats que corroboren la capacitat de l'aproximació monolítica presentada per mesurar la característica freqüencial de ressonadors a escala sub-micromètrica. S'aconsegueix una transducció electrostàtica òptima i es mesuren respostes freqüencials elèctriques amb pics elevats (fins a 20 dB o més) i grans canvis de fase (fins a 160º) al voltant de la freqüència de ressonància. També es reporten mesures on s'observen efectes de softening/harderning de la constant de molla i d'histèresis produïts per les no linealitats així com la detecció del moviment Brownià intrínsec demostrant el bon matching de soroll entre el ressonador i el circuit de lectura. També es presenten els resultats de calibració, de mesures en temps real, i d'anàlisi de la resolució dels dispositius fabricats obtenint valors de fins a ~30 zg/√Hz (equivalent a ~6 pg/cm2√Hz) en condicions de buit que indiquen la millora respecte a treballs anteriors en termes de sensibilitat, resolució i procés de fabricació.Es presenta i es testeja un circuit oscil·lador Pierce CMOS adaptat per a treballar amb ressonadors de ~10 MHz i amb resistències mecàniques equivalents de fins a 100 MΩ demostrant que és factible la detecció d'attograms amb un dispositiu sensor completament portable. / Resonant beams structures are very attractive transducers for physical, chemical and biological sensors based on micro-/nanoelectromechanical systems (M-/NEMS) due to its simplicity, wide range of sensing domains, and extremely high sensitivity. This Ph.D. thesis is focused on the design, fabrication and characterization of monolithic CMOS-MEMS based on sub-micrometer scale resonant beams for its application in ultrasensitive mass detection with a portable device. The resonators operate in dynamic mode where the mass is measured as a change of its resonant frequency which is electrostatically induced and capacitive readout by means of a monolithically integrated CMOS circuitry. Two different technological approaches are considered to fabricate sub-micrometer scale resonant beams on pre-processed CMOS chips allowing a monolithic integration: (i) nano post-processing of the CMOS chip to obtain the resonant beams or (ii) definition of the resonant beams at the same time that the CMOS circuits. From both approaches, metal and polysilicon devices exhibiting unprecedented mass sensitivities (for monolithic CMOS sensors) in the atto-/zeptogram range are reported. Comparison of the results following both approaches is given.High-sensitivity readout CMOS circuits are specifically designed to amplify the capacitive current with transimpedance gains (using a commercial 0.35-μm CMOS technology) up to 120 dBΩ at 10 MHz allowing to detect the resonator displacement with resolutions up to ~10 fm/√Hz which are similar than the best reported optical readout systems without the need of a bulky setup.Electrical characterization, in air and in vacuum conditions, of fabricated CMOS-MEMS devices is presented corroborating the ability of the presented monolithic approach in measuring the frequency characteristics of sub-micrometer scale beam resonators. Optimal electrostatic transduction is achieved measuring electrical frequency responses with high peaks (up to 20 dB or more) and large phase shifts (up to 160º) around the resonance frequency. Measurements showing soft/hard-spring effect and hysteretic performance due to nonlinearities are also reported as well as the detection of intrinsic Brownian motion demonstrating the noise-matching between the resonator and the readout circuit. Results from calibration, real time mass measurements, and resolution analysis on fabricated devices obtaining values down to ~30 zg/√Hz (equivalent to ~6 pg/cm2√Hz) in vacuum conditions are also reported indicating the improvement from previous works in terms of sensitivity, resolution, and fabrication process.A specific CMOS Pierce oscillator circuit adapted to work with ~10 MHz beam resonators showing motional resistance up to 100 MΩ is presented and tested demonstrating the feasible attogram detection with a completely portable sensor device.

Reconfigurable impedance matching networks are an integral part of multiband radio-frequency (RF) transceivers. They are used to compensate for the input/output impedance variations between the different blocks caused by switching the frequency band of operation or by adjusting the output power level. Various tuning techniques have been developed to construct tunable impedance matching networks employing solid-state p-i-n diodes and varactors. At millimeter-wave frequencies, the increased loss due to the low quality factor of the solid-state devices becomes an important issue. Another drawback of the solid-state tuning elements is the increased nonlinearity and noise at higher RF power levels. The objective of the research described in this thesis is to investigate the feasibility of using RF microelectromechanical systems (RF-MEMS) technology to develop reconfigurable impedance matching networks. Different types of tunable impedance matching networks with improved impedance tuning range, power handling capability, and lower insertion loss have been developed. Another objective is to investigate the realization of a fully integrated one-chip solution by integrating MEMS devices in standard processes used for RF integrated circuits (RFICs). A new CMOS-MEMS post-processing technique has been developed that allows the integration of tunable RF MEMS devices with vertical actuation within a CMOS chip. Various types of CMOS-MEMS components used as tuning elements in reconfigurable RF transceivers have been developed. These include tunable parallel-plate capacitors that outperform the available CMOS solid-state varactors in terms of quality factor and linearity. A tunable microwave band-pass filter has been demonstrated by employing the proposed RF MEMS tunable capacitors. For the first time, CMOS-MEMS capacitive type switches for microwave and millimeter-wave applications have been developed using TSMC 0.35-µm CMOS process employing the proposed CMOS-MEMS integration technique. The switch demonstrates an excellent RF performance from 10-20 GHz. Novel MEMS-based reconfigurable impedance matching networks integrated in standard CMOS technologies are also presented. An 8-bit reconfigurable impedance matching network based on the distributed MEMS transmission line (DMTL) concept operating at 13-24 GHz is presented. The network is implemented using standard 0.35-µm CMOS technology and employs a novel suspended slow-wave structure on a silicon substrate. To our knowledge, this is the first implementation of a DMTL tunable MEMS impedance matching network using a standard CMOS technology. A reconfigurable amplifier chip for WLAN applications operating at 5.2 GHz is also designed and implemented. The amplifier achieves maximum power gain under variable load and source impedance conditions by using the integrated RF-MEMS impedance matching networks. This is the first single-chip implementation of a reconfigurable amplifier using high-Q MEMS impedance matching networks. The monolithic CMOS implementation of the proposed RF MEMS impedance matching networks enables the development of future low-cost single-chip RF multiband transceivers with improved performance and functionality.

Reconfigurable impedance matching networks are an integral part of multiband radio-frequency (RF) transceivers. They are used to compensate for the input/output impedance variations between the different blocks caused by switching the frequency band of operation or by adjusting the output power level. Various tuning techniques have been developed to construct tunable impedance matching networks employing solid-state p-i-n diodes and varactors. At millimeter-wave frequencies, the increased loss due to the low quality factor of the solid-state devices becomes an important issue. Another drawback of the solid-state tuning elements is the increased nonlinearity and noise at higher RF power levels. The objective of the research described in this thesis is to investigate the feasibility of using RF microelectromechanical systems (RF-MEMS) technology to develop reconfigurable impedance matching networks. Different types of tunable impedance matching networks with improved impedance tuning range, power handling capability, and lower insertion loss have been developed. Another objective is to investigate the realization of a fully integrated one-chip solution by integrating MEMS devices in standard processes used for RF integrated circuits (RFICs). A new CMOS-MEMS post-processing technique has been developed that allows the integration of tunable RF MEMS devices with vertical actuation within a CMOS chip. Various types of CMOS-MEMS components used as tuning elements in reconfigurable RF transceivers have been developed. These include tunable parallel-plate capacitors that outperform the available CMOS solid-state varactors in terms of quality factor and linearity. A tunable microwave band-pass filter has been demonstrated by employing the proposed RF MEMS tunable capacitors. For the first time, CMOS-MEMS capacitive type switches for microwave and millimeter-wave applications have been developed using TSMC 0.35-µm CMOS process employing the proposed CMOS-MEMS integration technique. The switch demonstrates an excellent RF performance from 10-20 GHz. Novel MEMS-based reconfigurable impedance matching networks integrated in standard CMOS technologies are also presented. An 8-bit reconfigurable impedance matching network based on the distributed MEMS transmission line (DMTL) concept operating at 13-24 GHz is presented. The network is implemented using standard 0.35-µm CMOS technology and employs a novel suspended slow-wave structure on a silicon substrate. To our knowledge, this is the first implementation of a DMTL tunable MEMS impedance matching network using a standard CMOS technology. A reconfigurable amplifier chip for WLAN applications operating at 5.2 GHz is also designed and implemented. The amplifier achieves maximum power gain under variable load and source impedance conditions by using the integrated RF-MEMS impedance matching networks. This is the first single-chip implementation of a reconfigurable amplifier using high-Q MEMS impedance matching networks. The monolithic CMOS implementation of the proposed RF MEMS impedance matching networks enables the development of future low-cost single-chip RF multiband transceivers with improved performance and functionality.

Zugl.: Freiburg (Breisgau), University, Diss., 2006.

Scanning probe microscopy (SPM) tip-based nanofabrication (TBN) is a technique that directly creates a variety of nanostructures on a substrate using the nanoscale probe tips. SPM TBN possesses superior resolution and flexibility: nanostructures with feature size under 5 nm have been achieved via SPM TBN, which is beyond what the state-of-the art optical-based lithography technique can provide. However, the inherent serial nature of SPM TBN makes it a low throughput process. Multi-probe SPM systems have therefore been developed to increase the nanofabrication efficiency. Atomic force microscopy (AFM) and scanning tunneling microscopy (STM) are two most commonly used SPM TBN techniques. Most of prior work has focused on contact-mode AFM-based TBN. This work, using CMOS MEMS technology as the design and fabrication platform, develops an active conductive probe array that aims to perform parallel surface imaging and nanofabrication in non-contact STM mode. The CMOS-MEMS process provides a monolithic integration of MEMS devices with CMOS electronics that can facilitate future automation and parallel probe operation. The CMOS-MEMS probe adopts a micro-cantilever structure and applies bimorph electrothermal actuation to control the vertical displacement of the probe tips. The cantilever is designed to be stiff, with a spring constant of 36 N/m that is larger than the force gradient of the cantilever tip-sample interaction forces in the working distance regime of STM in order to avoid the tip-to-sample “snap-in” and ensure the stability of the STM feedback system. A modified Spindt tip process, compatible with post-CMOS MEMS processing, is developed to batch fabricate Ni/Pt composite tips on CMOS-MEMS probe arrays that are used as STM end-effectors. The integrated Ni/Pt tips on the MEMS probes have a tip radius down to 50 vii nm. The Spindt tip demonstrates the capability of both imaging and nanowire fabrication in STM mode. A hierarchical dual-servo STM system is constructed for the parallel STM imaging using two CMOS-MEMS probes. The system consists of a piezoelectric actuator-driven servo and an electrothermal actuator-driven servo to control the vertical displacement of two probe tips and maintain a constant current between the tips and the sample. Both servos use a proportionalintegral controller. The dual-servo STM system is capable of parallel STM image acquisition using CMOS MEMS probe arrays. An on-chip electrothermal proximity sensor pair and probes with embedded microgoniometers are designed to assist the alignment between the CMOS-MEMS probe array and the examined sample surface. The electrothermal proximity sensor pair is used to measure the separation and the non-parallelism between the probe chip and the sample. The electrothermal proximity sensor has a positioning accuracy of around 1 μm. An electrothermal microgoniometer platform is developed to hold a one-dimensional array of active CMOS-MEMS probes and serves to provide the in situ fine adjustment of relative height among these probes. The micro-goniometer has a maximum tilt of 1.2°, which is sufficient to compensate the probe chip-sample misalignment and the possible height difference among array probes introduced by process variations.

Ces dernières années la miniaturisation des microsystèmes atteint la limite physique de leur développement. Ainsi une de voie d’innovation dans l’industrie des semiconducteurs est l’intégration des fonctionnalités supplémentaires au sein des composants déjà existants.Le projet consiste à intégrer, dans une même couche métallique d’interconnexion CMOS, un MEMS capable, par sa rotation, d’établir un contact électrique.Les verrous se situent dans la libération des parties mobiles par dissolution de l’oxyde environnant (déformation hors plan sous l’effet des contraintes résiduelles, stiction, présence de résidus qui empêchent le contact), dans l’actionnement (densité de courant, répétabilité, durabilité, fiabilité) ainsi que, la capacité d’établir un vrai contact électrique à faible résistance (aire réelle / apparente du contact des surfaces rugueuses, pollution du contact).Le travail réalisé a porté sur la conception, le design et la simulation des microsystèmes afin de surmonter ces difficultés et / ou d’étudier le comportement et mesurer les effets. / In recent years the miniaturization of microsystems is reaching the physical limit of its development. Thus, a path of innovation in the semiconductor industry is additional functionalities in existing components.The project consists to integrate a MEMS, within the same metal interconnect of CMOS layer which, by rotating, can establish an electrical contact.The obstacles are in the release of the moving parts by dissolution of the surrounding oxide (out of plane deformation under the effect of residual stress, stiction, residues which prevent contact), in the actuation (current density repeatability, durability, reliability) and, for ohmic switches, the ability to establish a real electrical contact with low resistance (real / apparent area of contact with rough surfaces, contact pollution).The work carried out has focused on conception (design) and simulation of microsystems to overcome these difficulties and / or to study the behavior and measure the effects.

Les capteurs M/NEMS résonants, grâce à leur petite taille, faible consommation, et caractère quasi-numérique (leur grandeur de sortie est une fréquence la plupart du temps), sont des outils incontournables dans les systèmes embarqués modernes, des objets connectés simples à l’industrie aérospatiale et militaire.Cependant, ils sont soumis aux dérives environnementales, et malgré la possibilité d’en diminuer l’effet par différentes techniques de conception, parfois l’association de deux capteurs en mode différentiel est nécessaire pour assurer la fiabilité de l’information en environnement difficiles. Dans cette thèse, une technique particulière de mesure différentielle est étudiée, qui consiste à synchroniser deux résonateurs, dont l’un est une référence et l’autre soumis à la grandeur physique à mesurer. Placés dans une seule boucle de rétroaction, les deux résonateurs oscillent à la même fréquence, et un désaccord entre les deux, issu de la grandeurphysique à mesurer entraine un déphasage. La mesure de ce déphasage est un moyen simple de remonter à l’information à mesurer, théoriquement insensible aux variations environnementales identiquement appliquées aux deux résonateurs. Cette technique bénéficie est également peu complexe au niveau de son implémentation, donc adapté à l’intégration à grande échelle. Après avoir étudié le cadre théorique de la synchronisation de résonateurs par verrouillage par injection, on dégage des contraintes d’implémentation, qui servent de ligne directrice dans la fabrication d’un démonstrateur. On dégage également des performances théoriques, qui sont comparées aux performances du démonstrateur. / M/NEMS resonant sensors, due to their small size, consumption and quasi-digital output (a frequency most of the time) are unavoidable tools for on-board systems, from smartphones to aeronautic technology. However, they suffer from environmental drifts, and even though the effect of these drifts can be limited by the design, it is sometimes necessary to use differential architectures to properly remove the drifts from the measurements and ensure the output reliability even in harsh environments. In this work, a special technique for differential measurement is studied, consisting in the synchronization of two resonators, one reference and one sensor. Placed in a single feedback loop, they oscillate at the same frequency and eventual phase shift when the physical quantity to be sensed is applied. This phase shift is a theoretically drift-free way to measure this physical quantity. This technique also benefits from its ease of integration, making it a good candidate for large scale integration. After studying the theoretical framework, several design guidelines are found, which are used in the fabrication of a proof of concept. The theoretical performances are found as well, and compared to the experimental ones.

Micro-Electro-Mechanical Systems (MEMS) varactors have the potential to replace conventional varactor diodes, due to their high loss and non-linearity, in many applications such as phase shifters, oscillators, and tunable filters. The objective of this thesis is to develop novel MEMS varactors to improve the capacitance tuning ratio, linearity, and quality factor. Several novel varactor configurations are developed, analyzed, fabricated and tested. They are built by using standard MEMS fabrication processes, as well as monolithic integration techniques in CMOS technology. The first capacitor consists of two movable plates, loaded with a nitride layer that exhibits an analog continuous capacitance tuning ratio. To decrease the the parasitic capacitance, a trench in the silicon substrate under the capacitor is adopted. The use of an insulation dielectric layer on the bottom plate of the MEMS capacitor increases the capacitors’ tuning ratio. Experimental and theoretical results are presented for two versions of the proposed capacitor with different capacitance values. The measured capacitance tuning ratio is 280% at 1 GHz. The proposed MEMS vararctor is built using the MetalMUMPs process. The second, third, and fourth capacitors have additional beams that are called carrier beams. The use of the carrier beams makes it possible to obtain an equivalent nonlinear spring constant, which increases the capacitors’ analog continuous tuning ratio. A lumped element model and a continuous model of the proposed variable capacitors are developed. The continuous model is simulated by commercial software. A detailed analysis for the steady state of the capacitors is presented. The measured capacitance tuning ratios of these three capacitors are 410%, 400% and 470%, respectively at 1 GHz. Also, the selfresonance frequency is measured and found to exceed 11 GHz. The proposed MEMS variable capacitors are built by the PolyMUMPs process. The fifth novel parallel-plate MEMS varactor has thin-film vertical comb actuators as its driver. Such an actuator can vertically displace both plates of the parallel-plate capacitor. By making use of the fringing field, this actuator exhibits linear displacement behavior, caused by the induced electrostatic force of the actuator’s electrodes. The proposed capacitor has a low parasitic capacitance and linear deflection due to the mechanically connected and electrically isolated actuators to the capacitor’s parallel-plates. The measured tuning capacitance ratio is 7:1 (600%) at 1 GHz. The fabricated MEMS varactor exhibits a self resonance frequency of 9 GHz and built by MetalMUMPs process. The sixth parallel-plate MEMS varactor exhibits a linear response and high tuning capacitance ratio. The capacitor employs the residual stress of the chosen bi-layer, and the non-linear spring constants from the suspended cantilevers to obtain a non-linear restoring force that compensates for the nonlinear electrostatic force induced between the top and bottom plates. Two existing techniques are used to widen the tuning range of the proposed capacitor. The first technique is to decrease the parasitic capacitance by etching the lossy substrate under the capacitor’s plates. The second technique is employed to increase the capacitance density, where the areas between the top and bottom plates overlap, by applying a thin film of dielectric material, deposited by the atomic layer deposition (ALD) technique. The measured linear continuous tuning ratio for the proposed capacitor, built in the PolyMUMPs process, is 5:1 (400%). The seventh and eighth MEMS variable capacitors have plates that curl up. These capacitors are built in 0.35 μm CMOS technology from the interconnect metallization layers. The plates of the presented capacitors are intentionally curled upward to control the tuning performance. A newly developed maskless post-processing technique that is appropriate for MEMS/CMOS circuits is proposed. it consists of dry and wet etching steps, developed to integrate the proposed MEMS varactors in CMOS technology. Mechanically, the capacitors are simulated by the finite element method in ANSYS, and the results are compared with the measured results. The seventh capacitor is a tri-state structure that exhibits a measured tuning range of 460% at 1 GHz with a flat capacitance response that is superior to that of conventional digital capacitors. The proposed capacitor is simulated in HFSS and the extracted capacitance is compared with the measured capacitance over a frequency range of 1 GHz to 5 GHz. The eighth capacitor is an analog continuous structure that demonstrates a measured continuous tuning range of 115% at 1 GHz with no pull-in. The measured quality factor for both CMOSbased capacitors is more than 300 at 1.5 GHz. The proposed curled-plate capacitors have a small area and can be realized to build a System-on-Chip (SoC). Finally, a tunable band pass filter that utilizes the MEMS variable capacitors in 0.18 μm CMOS technology from TSMC is designed, modeled and fabricated.

Micro-Electro-Mechanical Systems (MEMS) varactors have the potential to replace conventional varactor diodes, due to their high loss and non-linearity, in many applications such as phase shifters, oscillators, and tunable filters. The objective of this thesis is to develop novel MEMS varactors to improve the capacitance tuning ratio, linearity, and quality factor. Several novel varactor configurations are developed, analyzed, fabricated and tested. They are built by using standard MEMS fabrication processes, as well as monolithic integration techniques in CMOS technology. The first capacitor consists of two movable plates, loaded with a nitride layer that exhibits an analog continuous capacitance tuning ratio. To decrease the the parasitic capacitance, a trench in the silicon substrate under the capacitor is adopted. The use of an insulation dielectric layer on the bottom plate of the MEMS capacitor increases the capacitors’ tuning ratio. Experimental and theoretical results are presented for two versions of the proposed capacitor with different capacitance values. The measured capacitance tuning ratio is 280% at 1 GHz. The proposed MEMS vararctor is built using the MetalMUMPs process. The second, third, and fourth capacitors have additional beams that are called carrier beams. The use of the carrier beams makes it possible to obtain an equivalent nonlinear spring constant, which increases the capacitors’ analog continuous tuning ratio. A lumped element model and a continuous model of the proposed variable capacitors are developed. The continuous model is simulated by commercial software. A detailed analysis for the steady state of the capacitors is presented. The measured capacitance tuning ratios of these three capacitors are 410%, 400% and 470%, respectively at 1 GHz. Also, the selfresonance frequency is measured and found to exceed 11 GHz. The proposed MEMS variable capacitors are built by the PolyMUMPs process. The fifth novel parallel-plate MEMS varactor has thin-film vertical comb actuators as its driver. Such an actuator can vertically displace both plates of the parallel-plate capacitor. By making use of the fringing field, this actuator exhibits linear displacement behavior, caused by the induced electrostatic force of the actuator’s electrodes. The proposed capacitor has a low parasitic capacitance and linear deflection due to the mechanically connected and electrically isolated actuators to the capacitor’s parallel-plates. The measured tuning capacitance ratio is 7:1 (600%) at 1 GHz. The fabricated MEMS varactor exhibits a self resonance frequency of 9 GHz and built by MetalMUMPs process. The sixth parallel-plate MEMS varactor exhibits a linear response and high tuning capacitance ratio. The capacitor employs the residual stress of the chosen bi-layer, and the non-linear spring constants from the suspended cantilevers to obtain a non-linear restoring force that compensates for the nonlinear electrostatic force induced between the top and bottom plates. Two existing techniques are used to widen the tuning range of the proposed capacitor. The first technique is to decrease the parasitic capacitance by etching the lossy substrate under the capacitor’s plates. The second technique is employed to increase the capacitance density, where the areas between the top and bottom plates overlap, by applying a thin film of dielectric material, deposited by the atomic layer deposition (ALD) technique. The measured linear continuous tuning ratio for the proposed capacitor, built in the PolyMUMPs process, is 5:1 (400%). The seventh and eighth MEMS variable capacitors have plates that curl up. These capacitors are built in 0.35 μm CMOS technology from the interconnect metallization layers. The plates of the presented capacitors are intentionally curled upward to control the tuning performance. A newly developed maskless post-processing technique that is appropriate for MEMS/CMOS circuits is proposed. it consists of dry and wet etching steps, developed to integrate the proposed MEMS varactors in CMOS technology. Mechanically, the capacitors are simulated by the finite element method in ANSYS, and the results are compared with the measured results. The seventh capacitor is a tri-state structure that exhibits a measured tuning range of 460% at 1 GHz with a flat capacitance response that is superior to that of conventional digital capacitors. The proposed capacitor is simulated in HFSS and the extracted capacitance is compared with the measured capacitance over a frequency range of 1 GHz to 5 GHz. The eighth capacitor is an analog continuous structure that demonstrates a measured continuous tuning range of 115% at 1 GHz with no pull-in. The measured quality factor for both CMOSbased capacitors is more than 300 at 1.5 GHz. The proposed curled-plate capacitors have a small area and can be realized to build a System-on-Chip (SoC). Finally, a tunable band pass filter that utilizes the MEMS variable capacitors in 0.18 μm CMOS technology from TSMC is designed, modeled and fabricated.

In this research, wafer-level flexible input/output interconnection technologies, Mechanically Flexible Interconnects (MFIs), have been developed. First, Au-NiW MFIs with 65 µm vertical elastic range of motion are designed and fabricated. The gold passivation layer is experimentally verified to not only lower the electrical resistance but also significantly extend the life-time of the MFIs. In addition, a photoresist spray-coating based fabrication process is developed to scale the in-line pitch of MFIs from 150 µm to 50 µm. By adding a contact-tip, Au-NiW MFI could realize a rematable assembly on a substrate with uniform pads and a robust assembly on a substrate with 45 µm surface variation. Last but not least, multi-pitch multi-height MFIs (MPMH MFIs) are formed using double-lithography and double-reflow processes, which can realize an MFI array containing MFIs with various heights and various pitches. Using these advanced MFIs, large scale heterogeneous systems which can provide high performance system-level interconnections are demonstrated. For example, the demonstrated 3D interposer stacking enabled by MPMH MFIs is promising to realize a low profile and cavity-free robust stacking system. Moreover, bridged multiinterposer system is developed to address the reticle and yield limitations of realizing a large scale system using current 2.5D integration technologies. The high-bandwidth interconnection available within interposer can be extended by using a silicon chip to bridge adjacent interposers. MFIs assisted thermal isolation is also developed to alleviate thermal coupling in a high-performance 3D stacking system.