The purpose of this thesis is to research the possibility of realizing hardware support for hybrid single electron transistor (SET)-CMOS circuits by a systematic approach of design, analysis and simulation. The metallic SET transistors considered in this work are fabricated within the chip interconnect layers using CMOS back-end-of-line (BEOL)-compatible processing. The CMOS process integration can be divided into front-end-of-line (FEOL) and BEOL processes. The FEOL includes processes required to form isolated CMOS transistors whereas BEOL is the second portion of the IC fabrication where the devices get interconnected through the wiring using multiple layers of dielectrics and metals. Therefore, metallic SET circuits can be easily stacked above the CMOS platform presenting a low cost, low thermal budget, improving the overall yield at high-volume production of highly integrated systems. This considerably decreases the interconnect parasitics and increases the density of functions while maintaining the overall acceptable performance. Many problems such as low current drivability, delay and small voltage gain that hinder SET technology for its implementation in integrated circuits can be alleviated by intelligent circuit design. Although a complete replacement of CMOS by SETs is unlikely in the near future, an augmentation of CMOS with SETs is desirable if interfacing from and to CMOS works well. Interfacing from CMOS to SET circuitry is simple as the current and voltage levels are small and in accessible range. But interfacing CMOS from SET circuits is delicate due to SET logic's low current driving capability for CMOS and its interconnect. There is no concrete research on the interface issue wherein a SET-only circuitry drives a CMOS and its interconnects. For such hybridization to become possible, it is necessary to demonstrate the SET logic driving capability for CMOS with sufficient current drive and output voltage. The core SET logic can be designed to operate at low voltage, but at the interface the output of the SET logic must be in a voltage range that can be fed to a CMOS input for proper logic functionality. It is hence necessary to develop and adopt a systematic design methodology for such hybrid circuits at a specific technology node for room temperature operation. In this thesis we will look at a generalized design methodology that can be applied to (a) develop a fabrication model with parasitic effect of a hybrid SET-CMOS and SET-only circuits, (b) design and analyze the SET based fundamental building block in hybrid SET-CMOS or SET-only circuit and (c) simulate such a circuitry to assess its merits. More specifically, we will address the interfacing issue of such hybrid circuits in which we exploit the maximum capability of a SET logic in terms of driving capability, voltage response and power for a room temperature operation. The result of this research motivates the application of SET logic in 2 stages realizing some properties beyond those of CMOS devices. The first stage is the heterogeneous integration at chip level around a CMOS core. In such a circuitry, the SET introduces new functionalities such as reconfigurable logic, random number-based circuits, and multiband filtering circuits that can be combined with CMOS based general purpose processors or I/O signal restoration. The second stage of application is to use a new information processing technology focussed on a "new switch" exploiting a new state variable to provide functional scaling substantially beyond that attainable solely with ultimately scaled CMOS.

Ces dernières années la miniaturisation des microsystèmes atteint la limite physique de leur développement. Ainsi une de voie d’innovation dans l’industrie des semiconducteurs est l’intégration des fonctionnalités supplémentaires au sein des composants déjà existants.Le projet consiste à intégrer, dans une même couche métallique d’interconnexion CMOS, un MEMS capable, par sa rotation, d’établir un contact électrique.Les verrous se situent dans la libération des parties mobiles par dissolution de l’oxyde environnant (déformation hors plan sous l’effet des contraintes résiduelles, stiction, présence de résidus qui empêchent le contact), dans l’actionnement (densité de courant, répétabilité, durabilité, fiabilité) ainsi que, la capacité d’établir un vrai contact électrique à faible résistance (aire réelle / apparente du contact des surfaces rugueuses, pollution du contact).Le travail réalisé a porté sur la conception, le design et la simulation des microsystèmes afin de surmonter ces difficultés et / ou d’étudier le comportement et mesurer les effets. / In recent years the miniaturization of microsystems is reaching the physical limit of its development. Thus, a path of innovation in the semiconductor industry is additional functionalities in existing components.The project consists to integrate a MEMS, within the same metal interconnect of CMOS layer which, by rotating, can establish an electrical contact.The obstacles are in the release of the moving parts by dissolution of the surrounding oxide (out of plane deformation under the effect of residual stress, stiction, residues which prevent contact), in the actuation (current density repeatability, durability, reliability) and, for ohmic switches, the ability to establish a real electrical contact with low resistance (real / apparent area of contact with rough surfaces, contact pollution).The work carried out has focused on conception (design) and simulation of microsystems to overcome these difficulties and / or to study the behavior and measure the effects.

With the continued progression of Moore’s law into the sub-14nm technology nodes, interconnect RC and power dissipation scaling play an increasingly important role in overall product performance. As critical dimensions in the mainstream Cu/ULK interconnect system shrink below 30nm, corresponding increases in relative process variation and decreases in overall process window mandate increasingly complex integrated solutions. Traditional metallization processes, e.g. PVD barrier and seed layers, no longer scale for all layout configurations as they reach physical and geometric limitations. Interactions between design, OPC, and patterning also play more and more critical roles with respect to reliability and yield in volume manufacturing; stated simply, scaling is no longer “business as usual”. Restricted design layouts, prescriptive design rules, novel materials, and holistic integration solutions each therefore become necessary to maximize available process windows, thus enabling new generations of cost-competitive products in the marketplace.

Fluoride based chemical systems are widely used at various stages in microelectronic processing, particularly for wet cleaning and etching applications. Some examples include the use of semi aqueous fluoride (SAF) solutions in back end of line cleaning, the use of dilute HF solutions as etchants for SiO2 and HF-HNO3 or HF-H2O2 solutions as isotropic etchants for silicon. In this work, the use of fluoride based solutions for two applications relevant to semiconductor processing are considered.In the first part of the study, cleaning of post plasma etch residues generated during fabrication of copper damascene structures was investigated in semi aqueous fluoride (SAF) formulations based on dimethyl sulfoxide and ammonium fluoride. Formulations designed for residue removal should be able to remove the residue effectively, without causing critical dimension loss during the process cycle. A systematic evaluation of solution variables (solvent content and pH) was conducted and the extent of removal of model copper oxide films and selectivity over copper and carbon doped oxide (CDO) films were used as metrics to evaluate the formulations. Results of the study indicate that the presence of solvent is necessary to achieve reasonable etch selectivity over dielectric films. Additionally, a removal end point detection technique based on electrochemical impedance spectroscopy was developed, which could potentially help in the optimization of cleaning time with minimal dielectric loss. This method was applied to monitor the removal of copper oxide films as well as residue from patterned test structures.In the second part of the study, electrochemical formation of porous silicon films in hydrofluoric acid (HF) solutions was investigated, for potential applications in advanced packaging. Specifically, porous silicon formation in solution mixtures containing HF, acetic acid and peroxide, was studied. The effect of variables including current density, substrate resistivity, HF, acetic acid and peroxide concentration, on key porous film characteristics such as growth rate, porosity and microstructure, was explored. Addition of peroxide was found to significantly increase the porosity and growth rate of the film, as a result of enhanced chemical dissolution and films with porosities as high as 95% were obtained. Additionally, in solutions containing peroxide, a variety of microstructural features, such as nanopores, micron sized pores, truncated pyramidal structures and silicon needles were observed, under various fabrication conditions.

Interconnection layers fabricated during back end of line processing in semiconductor manufacturing involve dry etching of a low-k material and deposition of copper and metal barriers to create copper/dielectric stacks. After plasma etching steps used to form the trenches and vias in the dielectric, post etch residues (PER) that consist of organic polymer, metal oxides and fluorides, form on top of copper and low-k dielectric sidewalls. Currently, most semiconductor companies use semi aqueous fluoride (SAF) based formulations containing organic solvent(s) for PER removal. Unfortunately, these formulations adversely impact the environmental health and safety (EHS) requirements of the semiconductor industry. Environmentally friendly "green" formulations, free of organic solvents, are preferred as alternatives to remove PER. In this work, a novel low temperature molten salt system, referred as deep eutectic solvent (DES) has been explored as a back end of line cleaning (BEOL) formulation. Specifically, the DES system comprised of two benign chemicals, malonic acid (MA) and choline chloride (CC), is a liquid at room temperature. In certain cases, the formulation was modified by the addition of glacial acetic acid (HAc). Using these formulations, selective removal of three types of PER generated by timed CF₄/O₂ etching of DUV PR films on Cu was achieved. Type I PER was mostly organic in character (fluorocarbon polymer type) and had a measured thickness of 160 nm. Type II PER was much thinner (25 nm) and consisted of a mixture of organic and inorganic compounds (copper fluorides). Further etching generated 17 nm thick Type III PER composed of copper fluorides and oxides. Experiments were also conducted on patterned structures. Cleaning was performed by immersing samples in a temperature controlled (30 or 40° C) double jacketed vessel for a time between 1 and 5 minutes. Effectiveness of cleaning was characterized using SEM, XPS and single frequency impedance measurements. Type II and III residues, which contained copper compounds were removed in CC/MA DES within five minutes through dissolution and subsequent complexation of copper by malonic acid. Removal of Type I PER required the addition of glacial acetic acid to the DES formulation. Single frequency impedance measurement appears to be a good in situ method to follow the removal of the residues. High water solubility of the components of the system in conjunction with their environmental friendly nature, make the DES an attractive alternative to SAF.

<p>Copper (Cu) has been used as the main conductor in interconnects due to its low resistivity. However, because of its high diffusivity, diffusion barriers/liners (tantalum nitride/tantalum; TaN/Ta) must be incorporated to surround Cu wires. Otherwise, Cu ions/atoms will drift/diffuse through the inter-metal dielectric (IMD) that separates two distinct interconnects, resulting in circuit shorting and chip failures. The scaling limit of conventional Cu diffusion barriers/liners has become the bottleneck for interconnect technology, which in turn limits the IC performance. The interconnect half-pitch size will reach ~20 nm in the coming sub-5 nm technology nodes. Meanwhile, the TaN/Ta (barrier/liner) bilayer stack has to be > 4 nm to ensure acceptable liner and diffusion barrier properties. Since TaN/Ta occupy a significant portion of the interconnect cross-section and they are much more resistive than Cu, the effective conductance of an ultra-scaled interconnect will be compromised by the thick bilayer. Therefore, two dimensional (2D) layered materials have been explored as diffusion barrier alternatives owing to their atomically thin body thicknesses. However, many of the proposed 2D barriers are prepared at too high temperatures to be compatible with the back-end-of-line (BEOL) technology. In addition, as important as the diffusion barrier properties, the liner properties of 2D materials must be evaluated, which has not yet been pursued. </p> The objective of the thesis is to develop a 2D barrier/liner that overcomes the issues mentioned. Therefore, we first visit various 2D layered materials to understand their fundamental capability as barrier candidates through theoretical calculations. Among the candidates, hexagonal-boron-nitride (h-BN) and molybdenum disulfide (MoS₂) are selected for experimental studies. In addition to studying their fundamental properties to know their potential, we have also developed techniques that can realize low-temperature-grown 2D layered materials. Metal-organic chemical vapor deposition (MOCVD) is adopted for the synthesis of BEOL-compatible MoS₂. The electrical test results demonstrate the promises of integrating 2D layered materials to the state-of-the-art interconnect technology. Furthermore, by considering not only diffusion barrier properties but also liner properties, we develop another 2D layered material, tantalum sulfide (TaS_x), using plasma-enhanced chemical vapor deposition (PECVD). The TaS_x is promising in both barrier and liner aspects and is BEOL-compatible. Therefore, we believed that the conventional TaN/Ta bilayer stack can be replaced with an ultra-thin TaS_x layer to maximize the Cu volume for ultra-scaled interconnects and improve the performance. Furthermore, Since via resistance has become the bottleneck for overall interconnect performance, we study the vertical conduction of TaS_x. Both the intrinsic and extrinsic properties of this material are investigated and engineering approaches to improve the vertical conduction are also tested. Finally, we explore the possibilities of benefiting from 2D materials in other applications and propose directions for future studies.

Fabrication of current generation integrated circuits involves the creation of multilevel copper/low-k dielectric structures during the back end of line processing. This is done by plasma etching of low-k dielectric layers to form vias and trenches, and this process typically leaves behind polymer-like post etch residues (PER) containing copper oxides, copper fluorides and fluoro carbons, on underlying copper and sidewalls of low-k dielectrics. Effective removal of PER is crucial for achieving good adhesion and low contact resistance in the interconnect structure, and this is accomplished using wet cleaning and rinsing steps. Currently, the removal of PER is carried out using semi-aqueous fluoride based formulations. To reduce the environmental burden and meet the semiconductor industry's environmental health and safety requirements, there is a desire to completely eliminate solvents in the cleaning formulations and explore the use of organic solvent-free formulations.The main objective of this work is to investigate the selective removal of PER over copper and low-k (Coral and Black Diamond®) dielectrics using all-aqueous dilute HF (DHF) solutions and choline chloride (CC) - urea (U) based deep eutectic solvent (DES) system. Initial investigations were performed on plasma oxidized copper films. Copper oxide and copper fluoride based PER films representative of etch products were prepared by ashing g-line and deep UV photoresist films coated on copper in CF4/O2 plasma. PER removal process was characterized using scanning electron microscopy and X-ray photoelectron spectroscopy and verified using electrochemical impedance spectroscopy measurements.A PER removal rate of ~60 Å/min was obtained using a 0.2 vol% HF (pH 2.8). Deaeration of DHF solutions improved the selectivity of PER over Cu mainly due to reduced Cu removal rate. A PER/Cu selectivity of ~20:1 was observed in a 0.05 vol% deaerated HF (pH 3). DES systems containing 2:1 U/CC removed PER at a rate of ~10 and ~20 Å/min at 40 and 70oC respectively. A mixture of 10-90 vol% de-ionized water (W) with 2:1 U/CC in the temperature range of 20 to 40oC also effectively removed PER. Importantly, etch rate of copper and low-k dielectric in DES formulations were lower than that in conventional DHF cleaning solutions.

With the continued progression of Moore’s law into the sub-14nm technology nodes, interconnect RC and power dissipation scaling play an increasingly important role in overall product performance. As critical dimensions in the mainstream Cu/ULK interconnect system shrink below 30nm, corresponding increases in relative process variation and decreases in overall process window mandate increasingly complex integrated solutions. Traditional metallization processes, e.g. PVD barrier and seed layers, no longer scale for all layout configurations as they reach physical and geometric limitations. Interactions between design, OPC, and patterning also play more and more critical roles with respect to reliability and yield in volume manufacturing; stated simply, scaling is no longer “business as usual”. Restricted design layouts, prescriptive design rules, novel materials, and holistic integration solutions each therefore become necessary to maximize available process windows, thus enabling new generations of cost-competitive products in the marketplace.

Pour réduire la taille des dispositifs et les temps de commutation en microélectronique, les lignes d'interconnexions doivent être isolées par du SiOCH poreux. Cependant, la réalisation de tranchées étroites dans le SiOCH poreux nécessite de revoir les différents procédés par plasmas (gravure, traitements post-gravure) et les schémas d'intégration, puisque ce matériau est facilement dégradé lorsqu'il est exposé à un plasma.<br /><br />Cette thèse porte sur les interactions plasmas/matériaux pour l'intégration des SiOCH poreux dans des tranchées très étroites (<100 nm). Les diagnostics des plasmas et l'analyse des matériaux exposés aux plasmas permettent de caractériser et d'optimiser les procédés de transfert de motifs d'un masque métallique ou organique dans un SiOCH poreux ou hybride (rendu poreux en fin d'intégration). La modification des matériaux poreux et hybrides par les plasmas post-gravure est également étudiée.<br /><br />Avec un plasma fluorocarboné, le matériau hybride présente des mécanismes de gravure similaires à ceux d'un SiOCH dense. Le TiN et le matériau organique ont des mécanismes de gravure différents de ceux des diélectriques, ce qui assure une bonne sélectivité. Le procédé de gravure optimisé pour le masque organique permet la gravure de tranchées très étroites avec un profil quasiment vertical. Par contre, le contrôle dimensionnel de tranchées étroites est plus difficile avec un masque en TiN, en raison de dépôts métalliques sur les flancs, de profils en forme de tonneaux, et du flambage des lignes. Après l'étape de gravure, les matériaux poreux et hybrides sont modifiés par les plasmas post-gravure.

Die fortwährende Verkleinerung der Strukturbreiten in der Mikroelektronik erfordert es, herkömmliche SiO2 Dielektrika durch Materialien mit kleinerer Dielektrizitätskonstante zu ersetzen. Dafür sind verschiedene „low-k Materialien“ entwickelt worden. Unter diesen sind die Organosilikatgläser, die aus SiO2 Netzwerken mit eingelagerten Methylgruppen bestehen wegen ihrer ausgezeichneten Eigenschaften besonders interessant als Dielektrika zwischen metallischen Leiterbahnen. In dieser Arbeit sind fünf verschiedene dieser „low-k Materialien“ untersucht worden: ein dichtes und vier poröse Materialien, die alle durch plasmagestützte chemische Gasphasenabscheidung hergestellt wurden. Die strukturellen, chemischen und dielektrischen Eigenschaften der Materialien wurden mit Hilfe der analytischen Durchstrahlungselektronenmikroskopie unter Verwendung eines abbildenden GATAN-Energiespektrometers untersucht. Die Bestimmung der radialen Verteilungsfunktion (RDF) zur Charakterisierung der atomaren Nahordnung ermöglicht uns die Ermittlung mittlerer Bindungslängen und – winkel sowie der mikroskopischen Dichte des Materials. Gegenüber SiO2 wurden in den untersuchten „low-k Materialien“ stark veränderte mittlere Si-O, O-O und Si-Si Bindungslängen gefunden. Dieses wirkt sich natürlich auch auf die mittleren Si-O-Si bzw. O-Si-O Bindungswinkel aus, und wie erwartet war auch die mikroskopische Dichte der „low-k Materialien“ kleiner als die Dichte des SiO2. Elektronen Energieverlustspektroskopie (EELS) und Photoelektronenspektroskopie (XPS) wurden zur Charakterisierung der chemischen Umgebung der Atome in den „low-k Materialien“ herangezogen. Die Energien von Ionisationskanten und die Bindungsenergien der Silizium-2p und Sauerstoff-1s Elektronen waren in den „low-k Materialien“ größer als im SiO2. Die Kohlenstoffatome kamen in den „low-k Materialien“ sowohl sp2 als auch sp3 hybridisiert vor. sp2-Hybridisierung liegt vor, wenn Bindungen wie Si=CH2 und C=C im Netzwerk vorkommen, während sp3 Hybridisierung z.B. dann vorkommt, wenn freie Si-Bindungen durch –CH3 Gruppen abgesättigt werden. Die Anteile an sp2- bzw. sp3-hybridisierten Kohlenstoffatome wurden aus der Feinstruktur der K-Energieverlustkanten des Kohlenstoffs abgeschätzt. Das ergab, daß die meisten Kohlenstoffatome in den „low-k Materialien“ sp2-hybridisiert sind. Die dielektrischen Eigenschaften wurden durch Kramers-Kronig-Transformation einer Energieverlustfunktion ermittelt, die aus dem Niedrigverlust-EELS-Spektrum im Bereich der Plasmonenanregungen gewonnen wurde. Die Bandlücke des SiO2 beträgt ungefähr 9 eV während dichte „low-k Materialien“ aufgrund der Unregelmäßigkeiten in ihrem SiO2-Netzwerk zusätzliche Zustandsdichten innerhalb der Bandlücke aufweisen. Die Erzeugung von Poren im „low-k Material“ vermindert offenbar die Zustandsdichte im Bereich der Bandlücke und erweitert diese im Vergleich zum SiO2. Eine Modellrechnung mit der Dichtefunktionaltheorie für ein Strukturmodell, das den „low-k Materialien“ nahe kommt, ist zum Vergleich mit der experimentell gefundenen kombinierten Zustandsdichte herangezogen worden und zeigt eine gute Übereinstimmung. Die im Standard-Herstellungsprozeß vorkommenden Verfahren des Plasmaätzens und der Plasmaveraschung können die Struktur des „low-k Materials“ z.B. an den Seitenwänden von Ätzgräben verändern. Die gestörten Bereiche wurden mit der energiegefilterten Elektronenmikroskopie untersucht. Dabei wurde gefunden, daß sich die Strukturveränderungen der Seitenwände bis zu einer Tiefe in der Größenordnung von ungefähr 10 Nanometern erstrecken. Diese Bereiche sind verarmt an Kohlenstoff und ähneln folglich mehr einem SiO2-Dielektrikum. Die Kohlenstoffverarmung erstreckt sich in die „low-k Schicht“ in Form eines gaussartigen Profils mit maximaler Kohlenstoffkonzentration in der Mitte der Schicht. Die Sauerstoffkonzentration und die mikroskopische Dichte steigen in der Nähe der Seitenwände.