Nowadays, Multi-GHz analog-to-digital converters (ADCs) are becoming more and more popular in radar systems, software-de ned radio (SDR) and wideband communications, because they can realize much higher operation speed through using many interleaved sub-ADCs to relax ADC sampling rates. Although the time interleaved ADC has some issues such as gain mismatch, o set mismatch and timing skew between each ADC channel, these deterministic errors can be solved by previous works such as digital calibration technique. However, time-interleaved ADCs require a precise sample clock to achieve an acceptable e ective-numberof- bits (ENOB) which can be degraded by jitter in the sample clock. The clock generation circuits presented in this work achieves sub-picosecond jitter performance in 180nm CMOS which is suitable for time-interleaved ADC. Two di erent test chips were fabricated in 180nm CMOS to investigate the low jitter design technique. The low jitter delay line in two chips were designed in two di erent ways, but both of them utilized the low jitter design technique. In rst test chip, the measured RMS jitter is 0.1061ps for each delay stage. The second chip uses the proposed low jitter Delay-Locked Loop can work from 80MHz to 120MHz, which means it can provide the time interleaved ADC with 2.4GHz to 3.6GHz low jitter sample clock, the measured delay stage jitter performance in second test chip is 0.1085ps.

The design of high-performance, high-speed clock generation and distribution becomes challenging in terms of phase noise, jitter and power consumption, due to the fast development of communication and computing systems. Injection locking is a promising clocking technique since it can significantly improve the energy efficiency, suppress the phase noise of the ring oscillator, enable a fast startup and conveniently generate multiple time-interleaved phases. A quasi-linear model of injection-locked ring oscillator (ILRO) is utilized to mathematically formulate the frequency and time domain characteristics of the system, as well as the phase noise shaping and jitter tracking behavior. The settling behavior of ILRO is also exploited and shows a strong dependence on the locking range and the initial phase difference of the injected and the resultant oscillation signals. A forwarded-clock synchronization based on injection locking is designed for a 10 Gb/s photonic interconnect according to the specific features of optical links. A single clock recovery can be used for all the four channels, resulting in a large amount of power and area saving. The applications of sub-harmonic and super-harmonic injection locking in wireless communications for frequency multiplying and division are also discussed. / Graduation date: 2013 / Access restricted to the OSU Community at author's request from Oct. 1, 2012 - Oct. 1, 2014

As the CMOS technology continues to scale into the deep sub-micron regime, the demand for higher frequencies and higher levels of integration poses a significant challenge for the clock generation and distribution design of microprocessors. Hence, skew optimization schemes are necessary to limit clock inaccuracies to a small fraction of the clock period. In this thesis, a crude deskew buffer (CDB) is designed to facilitate an adaptive deskewing scheme that reduces the clock skew in an ASIC clock network under manufacturing process, supply voltage, and temperature (PVT)variations. The crude deskew buffer adopts a DLL structure and functions on a 1GHz nominal clock frequency with an operating frequency range of 800MHz to 1.2GHz. An approximate 91.6ps phase resolution is achieved for all simulation conditions including various process corners and temperature variation. When the crude deskew buffer is applied to seven ASIC clock networks with each under various PVT variations, a maximum of 67.1% reduction in absolute maximum clock skew has been achieved. Furthermore, the maximum phase difference between all the clock signals in the seven networks have been reduced from 957.1ps to 311.9ps, a reduction of 67.4%. Overall, the CDB serves two important purposes in the proposed deskewing methodology: reducing the absolute maximum clock skew and synchronizes all the clock signals to a certain limit for the fine deskewing scheme. By generating various clock phases, the CDB can also be potentially useful in high speed debugging and testing where the clock duty cycle can be adjusted accordingly. Various positive and negative duty cycle values can be generated based on the phase resolution and the number of clock phases being “hot swapped”. For a 500ps duty cycle, the following values can be achieved for both the positive and negative duty cycle: 224ps, 316ps, 408ps, 592ps, 684ps, and 776ps.

As the CMOS technology continues to scale into the deep sub-micron regime, the demand for higher frequencies and higher levels of integration poses a significant challenge for the clock generation and distribution design of microprocessors. Hence, skew optimization schemes are necessary to limit clock inaccuracies to a small fraction of the clock period. In this thesis, a crude deskew buffer (CDB) is designed to facilitate an adaptive deskewing scheme that reduces the clock skew in an ASIC clock network under manufacturing process, supply voltage, and temperature (PVT)variations. The crude deskew buffer adopts a DLL structure and functions on a 1GHz nominal clock frequency with an operating frequency range of 800MHz to 1.2GHz. An approximate 91.6ps phase resolution is achieved for all simulation conditions including various process corners and temperature variation. When the crude deskew buffer is applied to seven ASIC clock networks with each under various PVT variations, a maximum of 67.1% reduction in absolute maximum clock skew has been achieved. Furthermore, the maximum phase difference between all the clock signals in the seven networks have been reduced from 957.1ps to 311.9ps, a reduction of 67.4%. Overall, the CDB serves two important purposes in the proposed deskewing methodology: reducing the absolute maximum clock skew and synchronizes all the clock signals to a certain limit for the fine deskewing scheme. By generating various clock phases, the CDB can also be potentially useful in high speed debugging and testing where the clock duty cycle can be adjusted accordingly. Various positive and negative duty cycle values can be generated based on the phase resolution and the number of clock phases being “hot swapped”. For a 500ps duty cycle, the following values can be achieved for both the positive and negative duty cycle: 224ps, 316ps, 408ps, 592ps, 684ps, and 776ps.

Denna avhandling presenterar en undersökning av orsakerna och effekterna av timingosäkerhet i Sigma-Delta Analog-Digital-Omvandlare, med speciellt fokus på Sigma-Delta av den switchade kapacitanstypen. Det undersökta området för orsakerna till timingosäkerhet är digital klockgenerering och området för effekterna är sampling. Upplösningsnivån på analysen i detta arbete börjar på beteendenivå och slutar på transistornivå. Samplingskretsen är den intuitiva komponenten att söka i efter orsakerna till effekterna av timing-osäkerhet i en Analog-Digital-Omvandlare eftersom transformationen från reell tid till digital tid sker i samplingskretsen. Därför har prestandaeffekterna av timingosäkerhet i den typiska samplingskretsen för switchad kapacitans Sigma-Delta Analog-Digital-Omvandlare analyserats utförligt, modellerats och beskrivits i denna avhandling. Under analysprocessen har idéer om förbättrade samplingskretsar med naturlig tolerans mot timing-osäkerhet utvecklats och analyserats, och presenteras även. Två typer av förbättrade samplingstopologier presenteras: parallelsamplern och Sigma-Delta-samplern. Den första erhåller tolerans mot timing-osäkerhet genom att utnyttja ett teorem inom statistiken medan den andra är tolerant mot timing-osäkerhet p.g.a. spektral formning som trycker ut brus ur signalens frekvensband. Digital klockgenerering är ett fundamentalt steg i genereringen av multipla klocksignaler som behövs t.ex. i switchade kapacitansversioner av Sigma-Delta Analog-Digital-Omvandlare. Klockgeneratorkretsarna konverterar en tidsreferens, d.v.s. en klocksignal, som vanligen kommer från en faslåst loop till multipla tidsreferenser. De två typerna av klockgenereringskretsar som behandlas i denna avhandling används för att skapa två icke-överlappande klockor från en klocksignal. Processen som undersökts och beskrivits är hur matningsspänningsbrus och substratbrus omvandlas till timing-osäkerhet då en referenssignal passerar genom en av ovannämnda klockgenereringskretsar. Resultaten i denna avhandling har erhållits genom olika analystekniker. Modelleringarna och beskrivningarna har utförts från ett matematiskt och fysikaliskt perspektiv. Detta har fördelen av att kunna förutsäga prestandainfluenser som olika kretsparametrar har utan att behöva utföra datorsimuleringar. Svårigheterna med den matematiska och fysikaliska modelleringen är balansgången mellan olöslighet och överförenkling som måste hittas. Den andra infallsvinkeln är användandet av datorbaserade simuleringsverktyg både för beskrivnings- och verifieringsändamål. Simuleringsverktygen som använts är MATLAB och Spectre/Cadence. Som nämnts har deras syfte varit både som modell- och beskrivningsverifiering och även som ett sätt att erhålla kvantitativa resultat. Generellt talat bryter simuleringsverktyg den mentala kopplingen mellan resultat och diverse kretsparametrar och det kan vara svårt att uppnå en solid prestandaförståelse. Dock är det ibland bättre att erhålla ett prestandamått utan full förståelse än inget mått alls. / This dissertation presents an investigation of the causes and effects of timing uncertainty in Sigma-Delta Analog-to-Digital Converters, with special focus on the switched-capacitor Sigma-Delta type. The investigated field for cause of timing uncertainty is digital clock generation and the field for effect is sampling. The granularity level of the analysis in this work begins at behavioral level and finishes at transistor level. The sampling circuit is the intuitive component to look for the causes to the effects of timing uncertainty in an Analog-to-Digital Converter since the transformation from real time to digital time takes place in the sampling circuit. Hence, the performance impact of timing uncertainties in a typical sampling circuit of a switched-capacitor Sigma-Delta Analog-to-Digital Converter has been thoroughly analysed, modelled, and described in this dissertation. During the analysis process, ideas of improved sampling circuits with inherent tolerance to timing uncertainties were conceived and analysed, and are also presented. Two cases of improved sampling topologies are presented: the Parallel Sampler and the Sigma- Delta sampler. The first obtains its timing uncertainty tolerance from taking advantage of a theorem in statistics whereas the second is tolerant against timing uncertainties because of spectral shaping that effectively pushes the in-band timing noise out of the signal band. Digital clock generation is a fundamental step of generating multiple clock signals that are needed for example in switched-capacitor versions of Sigma-Delta Analog-to-Digital Converters. The clock generation circuitry converts a single time reference, i.e. a clock signal, usually coming from a phase-locked loop into multiple time references. The two types of clock-generation circuits that are treated in this dissertation are used to create two nonoverlapping clocks from a single clock signal. The process that has been investigated and described is how power-supply noise and substrate noise transforms into timing uncertainty when a reference signal is passed through one of the aforementioned clock generation circuits. The results presented in this dissertation have been obtained using different analysis techniques. The modelling and descriptions have been done from a mathematical and physical perspective. This has the benefit of predicting the performance impact by different circuit parameters without the need for computer based simulations. The difficulty with the mathematical and physical modelling is the balance that has to be found between intractability and oversimplification. The other angle of approach has been the use of computer based simulations for both description and verification purposes. The simulation tools that have been used in this work are MATLAB and Spectre/Cadence. As mentioned, their purpose has been both for model and description verification and also as a means of obtaining result metrics. Generally speaking, simulation tools mentally decouple the result from the various circuit parameters and reaching a solid performance understanding can be difficult. However, obtaining a performance metric without full comprehension can at times be better than having no metric at all. / QC 20100921

It was previously shown that the BRESENHAM algorithm is well-suited for digital fractional clock generation. Specifically, it proved to be the optimal approximation of a desired clock in terms of the switching edges provided by an available reference clock. Moreover, some synthesis results for hardwired dividers on Altera FPGAs showed that this technique for clock division achieves a high performance often at or close to the maximum frequency supported by the devices for moderate bit widths of up to 16 bits. This paper extends the investigations on the clock division by the BRESENHAM algorithm. It draws out the limits encountered by the existing implementation for both FPGA and VLSI realizations. A rather unconventional adoption of the carry-save representation combined with a soft-threshold comparison is proposed to circumvent these limitations. The resulting design is described and evaluated. Mathematically appealing results on the quality of the approximation achieved by this approach are presented. The underlying proofs and technical details are provided in the appendix.

In this work concepts and circuits for local clock generation in low-power heterogeneous multiprocessor systems-on-chip (MPSoCs) are researched and developed. The targeted systems feature a globally asynchronous locally synchronous (GALS) clocking architecture and advanced power management functionality, as for example fine-grained ultra-fast dynamic voltage and frequency scaling (DVFS). To enable this functionality compact clock generators with low chip area, low power consumption, wide output frequency range and the capability for ultra-fast frequency changes are required. They are to be instantiated individually per core. For this purpose compact all digital phase-locked loop (ADPLL) frequency synthesizers are developed. The bang-bang ADPLL architecture is analyzed using a numerical system model and optimized for low jitter accumulation. A 65nm CMOS ADPLL is implemented, featuring a novel active current bias circuit which compensates the supply voltage and temperature sensitivity of the digitally controlled oscillator (DCO) for reduced digital tuning effort. Additionally, a 28nm ADPLL with a new ultra-fast lock-in scheme based on single-shot phase synchronization is proposed. The core clock is generated by an open-loop method using phase-switching between multi-phase DCO clocks at a fixed frequency. This allows instantaneous core frequency changes for ultra-fast DVFS without re-locking the closed loop ADPLL. The sensitivity of the open-loop clock generator with respect to phase mismatch is analyzed analytically and a compensation technique by cross-coupled inverter buffers is proposed. The clock generators show small area (0.0097mm2 (65nm), 0.00234mm2 (28nm)), low power consumption (2.7mW (65nm), 0.64mW (28nm)) and they provide core clock frequencies from 83MHz to 666MHz which can be changed instantaneously. The jitter performance is compliant to DDR2/DDR3 memory interface specifications. Additionally, high-speed clocks for novel serial on-chip data transceivers are generated. The ADPLL circuits have been verified successfully by 3 testchip implementations. They enable efficient realization of future low-power MPSoCs with advanced power management functionality in deep-submicron CMOS technologies. / In dieser Arbeit werden Konzepte und Schaltungen zur lokalen Takterzeugung in heterogenen Multiprozessorsystemen (MPSoCs) mit geringer Verlustleistung erforscht und entwickelt. Diese Systeme besitzen eine global-asynchrone lokal-synchrone Architektur sowie Funktionalität zum Power Management, wie z.B. das feingranulare, schnelle Skalieren von Spannung und Taktfrequenz (DVFS). Um diese Funktionalität zu realisieren werden kompakte Taktgeneratoren benötigt, welche eine kleine Chipfläche einnehmen, wenig Verlustleitung aufnehmen, einen weiten Bereich an Ausgangsfrequenzen erzeugen und diese sehr schnell ändern können. Sie sollen individuell pro Prozessorkern integriert werden. Dazu werden kompakte volldigitale Phasenregelkreise (ADPLLs) entwickelt, wobei eine bang-bang ADPLL Architektur numerisch modelliert und für kleine Jitterakkumulation optimiert wird. Es wird eine 65nm CMOS ADPLL implementiert, welche eine neuartige Kompensationsschlatung für den digital gesteuerten Oszillator (DCO) zur Verringerung der Sensitivität bezüglich Versorgungsspannung und Temperatur beinhaltet. Zusätzlich wird eine 28nm CMOS ADPLL mit einer neuen Technik zum schnellen Einschwingen unter Nutzung eines Phasensynchronisierers realisiert. Der Prozessortakt wird durch ein neuartiges Phasenmultiplex- und Frequenzteilerverfahren erzeugt, welches es ermöglicht die Taktfrequenz sofort zu ändern um schnelles DVFS zu realisieren. Die Sensitivität dieses Frequenzgenerators bezüglich Phasen-Mismatch wird theoretisch analysiert und durch Verwendung von kreuzgekoppelten Taktverstärkern kompensiert. Die hier entwickelten Taktgeneratoren haben eine kleine Chipfläche (0.0097mm2 (65nm), 0.00234mm2 (28nm)) und Leistungsaufnahme (2.7mW (65nm), 0.64mW (28nm)). Sie stellen Frequenzen von 83MHz bis 666MHz bereit, welche sofort geändert werden können. Die Schaltungen erfüllen die Jitterspezifikationen von DDR2/DDR3 Speicherinterfaces. Zusätzliche können schnelle Takte für neuartige serielle on-Chip Verbindungen erzeugt werden. Die ADPLL Schaltungen wurden erfolgreich in 3 Testchips erprobt. Sie ermöglichen die effiziente Realisierung von zukünftigen MPSoCs mit Power Management in modernsten CMOS Technologien.

In this work concepts and circuits for local clock generation in low-power heterogeneous multiprocessor systems-on-chip (MPSoCs) are researched and developed. The targeted systems feature a globally asynchronous locally synchronous (GALS) clocking architecture and advanced power management functionality, as for example fine-grained ultra-fast dynamic voltage and frequency scaling (DVFS). To enable this functionality compact clock generators with low chip area, low power consumption, wide output frequency range and the capability for ultra-fast frequency changes are required. They are to be instantiated individually per core. For this purpose compact all digital phase-locked loop (ADPLL) frequency synthesizers are developed. The bang-bang ADPLL architecture is analyzed using a numerical system model and optimized for low jitter accumulation. A 65nm CMOS ADPLL is implemented, featuring a novel active current bias circuit which compensates the supply voltage and temperature sensitivity of the digitally controlled oscillator (DCO) for reduced digital tuning effort. Additionally, a 28nm ADPLL with a new ultra-fast lock-in scheme based on single-shot phase synchronization is proposed. The core clock is generated by an open-loop method using phase-switching between multi-phase DCO clocks at a fixed frequency. This allows instantaneous core frequency changes for ultra-fast DVFS without re-locking the closed loop ADPLL. The sensitivity of the open-loop clock generator with respect to phase mismatch is analyzed analytically and a compensation technique by cross-coupled inverter buffers is proposed. The clock generators show small area (0.0097mm2 (65nm), 0.00234mm2 (28nm)), low power consumption (2.7mW (65nm), 0.64mW (28nm)) and they provide core clock frequencies from 83MHz to 666MHz which can be changed instantaneously. The jitter performance is compliant to DDR2/DDR3 memory interface specifications. Additionally, high-speed clocks for novel serial on-chip data transceivers are generated. The ADPLL circuits have been verified successfully by 3 testchip implementations. They enable efficient realization of future low-power MPSoCs with advanced power management functionality in deep-submicron CMOS technologies. / In dieser Arbeit werden Konzepte und Schaltungen zur lokalen Takterzeugung in heterogenen Multiprozessorsystemen (MPSoCs) mit geringer Verlustleistung erforscht und entwickelt. Diese Systeme besitzen eine global-asynchrone lokal-synchrone Architektur sowie Funktionalität zum Power Management, wie z.B. das feingranulare, schnelle Skalieren von Spannung und Taktfrequenz (DVFS). Um diese Funktionalität zu realisieren werden kompakte Taktgeneratoren benötigt, welche eine kleine Chipfläche einnehmen, wenig Verlustleitung aufnehmen, einen weiten Bereich an Ausgangsfrequenzen erzeugen und diese sehr schnell ändern können. Sie sollen individuell pro Prozessorkern integriert werden. Dazu werden kompakte volldigitale Phasenregelkreise (ADPLLs) entwickelt, wobei eine bang-bang ADPLL Architektur numerisch modelliert und für kleine Jitterakkumulation optimiert wird. Es wird eine 65nm CMOS ADPLL implementiert, welche eine neuartige Kompensationsschlatung für den digital gesteuerten Oszillator (DCO) zur Verringerung der Sensitivität bezüglich Versorgungsspannung und Temperatur beinhaltet. Zusätzlich wird eine 28nm CMOS ADPLL mit einer neuen Technik zum schnellen Einschwingen unter Nutzung eines Phasensynchronisierers realisiert. Der Prozessortakt wird durch ein neuartiges Phasenmultiplex- und Frequenzteilerverfahren erzeugt, welches es ermöglicht die Taktfrequenz sofort zu ändern um schnelles DVFS zu realisieren. Die Sensitivität dieses Frequenzgenerators bezüglich Phasen-Mismatch wird theoretisch analysiert und durch Verwendung von kreuzgekoppelten Taktverstärkern kompensiert. Die hier entwickelten Taktgeneratoren haben eine kleine Chipfläche (0.0097mm2 (65nm), 0.00234mm2 (28nm)) und Leistungsaufnahme (2.7mW (65nm), 0.64mW (28nm)). Sie stellen Frequenzen von 83MHz bis 666MHz bereit, welche sofort geändert werden können. Die Schaltungen erfüllen die Jitterspezifikationen von DDR2/DDR3 Speicherinterfaces. Zusätzliche können schnelle Takte für neuartige serielle on-Chip Verbindungen erzeugt werden. Die ADPLL Schaltungen wurden erfolgreich in 3 Testchips erprobt. Sie ermöglichen die effiziente Realisierung von zukünftigen MPSoCs mit Power Management in modernsten CMOS Technologien.

Silicon alternatives to quartz crystal based oscillators to electronic system clocking are explored. A study of clocking requirements reveals widely different specifications for different applications. Traditional CMOS oscillator-based solutions are optimized for low-cost fully integrated micro-controller clock applications. The frequency variability of these clock generators is studied and techniques to compensate for this variability are proposed. The efficacy of these techniques in reducing variability is proven theoretically and experimentally. MEMS-resonator based oscillators, due to their exceptional quality factors, are identified as suitable integrated replacements to quartz based oscillators for higher accuracy applications such as data converter clocks. The frequency variation in these oscillators is identified and techniques to minimize the same are proposed and demonstrated. The sources of short-term variation (phase noise) in these oscillators are discussed and an inclusive theory of phase noise is developed. Techniques to improve phase noise are proposed. Findings from this research indicate that MEMS resonator based oscillators, may in future, outperform quartz based solutions in certain applications such as voltage controlled oscillators. The implications of these findings and potential directions for future research are identified.

Today’s microprocessors with millions of transistors perform high-complexitycomputing at multi-gigahertz clock frequencies. Clock generation and clockdistribution are crucial tasks which determine the overall performance of amicroprocessor. The ever-increasing power density and speed call for newmethodologies in clocking circuitry, as the conventional techniques exhibit manydrawbacks in the advanced VLSI chips. A significant percentage of the total dynamicpower consumption in a microprocessor is dissipated in the clock distributionnetwork. Also since the chip dimensions increase, clock jitter and skew managementbecome very challenging in the framework of conventional methodologies. In such asituation, new alternative techniques to overcome these limitations are demanded. The main focus in this thesis is on new circuit techniques, which treat thedrawbacks of the conventional clocking methodologies. The presented research in thisthesis can be divided into two main parts. In the first part, challenges in design ofclock generators have been investigated. Research on oscillators as central elements inclock generation is the starting point to enter into this part. A thorough analysis andmodeling of the injection-locking phenomenon for on-chip applications show greatpotential of this phenomenon in noise reduction and jitter suppression. In thepresented analysis, phase noise of an injection-locked oscillator has been formulated.The first part also includes a discussion on DLL-based clock generators. DLLs haverecently become popular in design of clock generators due to ensured stability,superior jitter performance, multiphase clock generation capability and simple designprocedure. In the presented discussion, an open-loop DLL structure has beenproposed to overcome the limitations introduced by DLL dithering around the averagelock point. Experimental results reveals that significant jitter reduction can beachieved by eliminating the DLL dithering. Furthermore, the proposed structuredissipates less power compared to the traditional DLL-based clock generators.Measurement results on two different clock generators implemented in 90-nm CMOSshow more than 10% power savings at frequencies up to 2.5 GHz. In the second part of this thesis, resonant clock distribution networks have beendiscussed as low-power alternatives for the conventional clocking schemes. In amicroprocessor, as clock frequency increases, clock power is going to be thedominant contributor to the total power dissipation. Since the power-hungry bufferstages are the main source of the clock power dissipation in the conventional clock distribution networks, it has been shown that the bufferless solution is the mosteffective resonant clocking method. Although resonant clock distribution shows greatpotential in significant clock power savings, several challenging issues have to besolved in order to make such a clocking strategy a sufficiently feasible alternative tothe power-hungry, but well-understood, conventional clocking schemes. In this part,some of these issues such as jitter characteristics and impact of tank quality factor onoverall performance have been discussed. In addition, the effectiveness of theinjection-locking phenomenon in jitter suppression has been utilized to solve the jitterpeaking problem. The presented discussion in this part is supported by experimentalresults on a test chip implemented in 130-nm CMOS at clock frequencies up to 1.8GHz. / Mikroprocessorer till dagens datorer innehåller hundratals miljoner transistorersom utför åtskilliga miljarder komplexa databeräkningar per sekund. I stort settalla operationer i dagens mikroprocessorer ordnas genom att synkronisera demmed en eller flera klocksignaler. Dessa signaler behöver ofta distribueras överhela chippet och driva alla synkroniseringskretsar med klockfrekvenser pååtskilliga miljarder svängningar per sekund. Detta utgör en stor utmaning förkretsdesigners på grund av att klocksignalerna behöver ha en extremt högtidsnoggranhet, vilket blir svårare och svårare att uppnå då chippen blir större.Idealt ska samma klocksignal nå alla synkroniseringskretsar exakt samtidigt föratt uppnå optimal prestanda, avvikelser ifrån denna ideala funktionalitet innebärlägre prestanda. Ytterliggare utmaningar inom klockning av digitala chip, är atten betydande andel av processorns totala effekt förbrukas i klockdistributionen.Därför krävs nya innovativa kretslösningar för att lösa problemen med bådeonoggrannheten och den växande effektförbrukningen i klockdistributionen. att lösa de problem som finns i dagens konventionella kretslösningar förklocksignaler på chip. I den första delen av denna avhandling presenterasforskningsresultat på oscillatorer vilka utgör mycket viktiga komponenter igeneringen av klocksignalerna på chippen. Teoretiska studier avfaslåsningsfenomen i integrerade klockoscillatorer har presenterats. Studiernahar visat att det finns stor potential för reducering av tidsonoggrannhet iklocksignalerna med hjälp av faslåsning till en annan signal. I avhandlingensförsta del presenteras även en diskussion om klockgeneratorer baserade påfördröjningslåsta element. Dessa fördröjningslåsta elementen, kända som DLLkretsar, har egenskapen att de kan fördröja en klocksignal med en bestämdfördröjning, vilket möjliggör skapandet av multipla klockfaser. En nykretsteknik har introducerats för klockgenerering av multipla klockfaser vilken reducerar effektförbrukningen och onoggranheten i DLL-baseradeklockgeneratorer. I denna teknik används en övervakningskrets vilken ser till attalla delar i klockgeneratorn utnyttjas effektivt och att oanvända kretsarinaktiveras. Baserat på experimentalla mätresultat från tillverkade testkretsar ikisel har en effektbesparing på mer än 10% uppvisats vid klockfrekvenser påupp till 2.5 GHz tillsammans med en betydande ökning av klocknoggranheten. I avhandlingens andra del diskuteras en klockdistributionsteknik som baseraspå resonans, vilken har visat sig vara ett lovande alternativ till konventionllabufferdrivna klockningstekniker när det gäller minskande effektförbrukning.Principen bakom tekniken är att återanvända den energi som utnyttjas till attladda upp klocklasten. Teoretiska resonemang har visat att storaenergibesparingar är möjliga, och praktiska mätningar på tillverkadeexperimentchip har visat att effektförbrukingen kan mer än halveras. Ettproblem med den föreslagna klockningstekniken är att data som används iberäkningarna kretsen direkt påverkar klocklasten, vilket även påverkarnoggranheten på klocksignalen. För att komma till rätta med detta problemetpresenteras en teknik, baserad på forskning inom ovan nämndafaslåsningsfenomen, som kan minska onoggrannheten på klocksignalen medöver 50%. Både effektbesparingen och förbättringen av tidsnoggranheten harverifierats med hjälp av mätningar på tillverkade chip vid frekvenser upp mot1.8 GHz.