The implementation of highly integrated multi-bands and multi-standards reconfigurable radio transceivers is one of the great challenges in the area of integrated circuit technology today. In addition the rapid market growth and high quality demands that require cheaper and smaller solutions, the technical requirements for the transceiver function of a typical wireless device are considerably multi-dimensional. The major key performance metrics facing RFIC designers are power dissipation, speed, noise, linearity, gain, and efficiency. Beside the difficulty of the circuit design due to the trade-offs and correlations that exist between these parameters, the situation becomes more and more challenging when dealing with multi-standard radio systems on a single chip and applications with different requirements on the radio software and hardware aiming at highly flexible dynamic spectrum access. In this dissertation, different solutions are proposed to improve the linearity, reduce the noise and power consumption in analog and RF circuits and systems. A system level design digital approach is proposed to compensate the harmonic distortion components produced by transmitter circuits’ nonlinearities. The approach relies on polyphase multipath scheme uses digital baseband phase rotation pre-distortion aiming at increasing harmonic cancellation and power consumption reduction over other reported techniques. New low power design techniques to enhance the noise and linearity of the receiver front-end LNA are also presented. The two proposed LNAs are fully differential and have a common-gate capacitive cross-coupled topology. The proposed LNAs avoids the use of bulky inductors that leads to area and cost saving. Prototypes are implemented in IBM 90 nm CMOS technology for the two LNAs. The first LNA covers the frequency range of 100 MHz to 1.77 GHz consuming 2.8 mW from a 2 V supply. Measurements show a gain of 23 dB with a 3-dB bandwidth of 1.76 GHz. The minimum NF is 1.85 dB while the input return loss is greater than 10 dB across the entire band. The second LNA covers the frequency range of 100 MHz to 1.6 GHz. A 6 dBm third-order input intercept point, IIP3, is measured at the maximum gain frequency. The core consumes low power of 1.55 mW using a 1.8 V supply. The measured voltage gain is 15.5 dB with a 3-dB bandwidth of 1.6 GHz. The LNA has a minimum NF of 3 dB across the whole band while achieving an input return loss greater than 12 dB. Finally, A CMOS single supply operational transconductance amplifier (OTA) is reported. It has high power supply rejection capabilities over the entire gain bandwidth (GBW). The OTA is fabricated on the AMI 0.5 um CMOS process. Measurements show power supply rejection ratio (PSRR) of 120 dB till 10 KHz. At 10 MHz, PSRR is 40 dB. The high performance PSRR is achieved using a high impedance current source and two noise reduction techniques. The OTA offers a very low current consumption of 25 uA from a 3.3 V supply.

Future wireless communication devices must support multiple standards and features on a single-chip. The trend towards software-defined radio requires flexible and efficient RF building blocks which justifies the adoption of broadband receiver front-ends in modern and future communication systems. The broadband receiver front-end significantly reduces cost, area, pins, and power, and can process several signal channels simultaneously. This research is mainly focused on the analysis and realization of the broadband receiver architecture and its various building blocks (LNA, Active Balun-LNA, Mixer, and trans-impedance amplifier) for multi-standard applications. In the design of the mobile DTV tuner, a direct-conversion receiver architecture is adopted achieving low power, low cost, and high dynamic-range for DVB-H standard. The tuner integrates a single-ended RF variable gain amplifier (RFVGA), a current-mode passive mixer, and a combination of continuous and discrete-time baseband filter with built-in anti-aliasing. The proposed RFVGA achieves high dynamic-range and gain-insensitive input impedance matching performance. The current-mode passive mixer achieves high gain, low noise, and high linearity with low power supplies. A wideband common-gate LNA is presented that overcomes the fundamental trade-off between power and noise match without compromising its stability. The proposed architecture can achieve the minimum noise figure over the previously reported feedback amplifiers in common-gate configuration. The proposed architecture achieves broadband impedance matching, low noise, large gain, enhanced linearity, and wide bandwidth concurrently by employing an efficient and reliable dual negative-feedback. For the wideband Inductorless Balun-LNA, active single-to-differential architecture has been proposed without using any passive inductor on-chip which occupies a lot of silicon area. The proposed Balun-LNA features lower power, wider bandwidth, and better gain and phase balance than previously reported architectures of the same kind. A surface acoustic wave (SAW)-less direct conversion receiver targeted for multistandard applications is proposed and fabricated with TSMC 0.13?m complementary metal-oxide-semiconductor (CMOS) technology. The target is to design a wideband SAW-less direct coversion receiver with a single low noise transconductor and current-mode passive mixer with trans-impedance amplifier utilizing feed-forward compensation. The innovations in the circuit and architecture improves the receiver dynamic range enabling highly linear direct-conversion CMOS front-end for a multi-standard receiver.

For the past 40 years, relentless focus on Moore’s Law transistor scaling has provided ever-increasing transistor performance and density. In order to continue the technology scaling beyond 22nm node, it is clear that conventional bulk-MOSFET needs to be replaced by new device architectures, most promising being the Multiple-Gate MOSFETs (MuGFET). Intel in mid 2011 announced the use of bulk Tri-Gate FinFETs in 22nm high volume logic process for its next-gen IvyBridge Microprocessor. It is expected that soon other semiconductor companies will also adopt the MuGFET devices. As like bulk-MOSFET, an accurate and physical compact model is important for MuGFET based circuit design. Compact modeling effort for MuGFET started in late nineties with planar double gate MOSFET(DGFET),as it is the simplest structure that one can conceive for MuGFET devices. The models so far proposed for DG MOSFETs are applicable for common gate symmetric DG (SDG) MOSFETs where both the gates have equal oxide thicknesses. However, for practical devices at nanoscale regime, there will always be some amount of asymmetry between the gate oxide thicknesses due to process variations and uncertainties, which can affect device performance significantly. At the same time, Independently controlled DG(IDG) MOSFETs have gained tremendous attention owing to its ability to modulate threshold voltage and transconductance dynamically. Due to the asymmetric nature of the electrostatic, developing efficient compact models for asymmetric/independent DG MOSFET is a daunting task. In this thesis effort has been put to provide some solutions to this challenge. We propose simple surface-potential based compact terminal charge models, applicable for Asymmetric Double gate MOSFETs (ADG) in two configurations1) Common-gate 2) Independent-gate. The charge model proposed for the common-gate ADG (CDG) MOSFET is seamless between the symmetric and asymmetric devices and utilizes the unique so-far-unexplored quasi-linear relationship between the surface potentials along the channel. In this model, the terminal charges could be computed by basic arithmetic operations from the surface potentials and applied biases, and can be easily implemented in any circuit simulator and extendable to short-channel devices. The charge model proposed for independent ADG(IDG)MOSFET is based on a novel piecewise linearization technique of surface potential along the channel. We show that the conventional “charge linearization techniques that have been used over the years in advanced compact models for bulk and double-gate(DG) MOSFETs are accurate only when the channel is fully hyperbolic in nature or the effective gate voltages are same. For other bias conditions, it leads to significant error in terminal charge computation. We demonstrate that the amount of nonlinearity that prevails between the surface potentials along the channel for a particular bias condition actually dictates if the conventional charge linearization technique could be applied or not. We propose a piecewise linearization technique that segments the channel into multiple sections where in each section, the assumption of quasi-linear relationship between the surface potentials remains valid. The cumulative sum of the terminal charges obtained for each of these channel sections yield terminal charges of the IDG device. We next present our work on modeling the non-ideal scenarios like presence of body doping in CDG devices and the non-planar devices like Tri-gate FinFETs. For a fully depleted channel, a simple technique to include body doping term in our charge model for CDG devices, using a perturbation on the effective gate voltage and correction to the coupling factor, is proposed. We present our study on the possibility of mapping a non-planar Tri-gate FinFET onto a planar DG model. In this framework, we demonstrate that, except for the case of large or tall devices, the generic mapping parameters become bias-dependent and an accurate bias-independent model valid for geometries is not possible. An efficient and robust “Root Bracketing Method” based algorithm for computation of surface potential in IDG MOSFET, where the conventional Newton-Raphson based techniques are inefficient due to the presence of singularity and discontinuity in input voltage equations, is presented. In case of small asymmetry for a CDG devices, a simple physics based perturbation technique to compute the surface potential with computational complexity of the same order of an SDG device is presented next. All the models proposed show excellent agreement with numerical and Technology Computer-Aided Design(TCAD) simulations for all wide range of bias conditions and geometries. The models are implemented in a professional circuit simulator through Verilog-A, and simulation examples for different circuits verify good model convergence.

The prevalence of wireless standards and the introduction of dynamic standards/applications, such as software-defined radio, necessitate the next generation wireless devices that integrate multiple standards in a single chip-set to support a variety of services. To reduce the cost and area of such multi-standard handheld devices, reconfigurability is desirable, and the hardware should be shared/reused as much as possible. This research proposes several novel circuit topologies that can meet various specifications with minimum cost, which are suited for multi-standard applications. This doctoral study has two separate contributions: 1. The low noise amplifier (LNA) for the RF front-end; and 2. The analog-to-digital converter (ADC). The first part of this dissertation focuses on LNA noise reduction and linearization techniques where two novel LNAs are designed, taped out, and measured. The first LNA, implemented in TSMC (Taiwan Semiconductor Manufacturing Company) 0.35Cm CMOS (Complementary metal-oxide-semiconductor) process, strategically combined an inductor connected at the gate of the cascode transistor and the capacitive cross-coupling to reduce the noise and nonlinearity contributions of the cascode transistors. The proposed technique reduces LNA NF by 0.35 dB at 2.2 GHz and increases its IIP3 and voltage gain by 2.35 dBm and 2dB respectively, without a compromise on power consumption. The second LNA, implemented in UMC (United Microelectronics Corporation) 0.13Cm CMOS process, features a practical linearization technique for high-frequency wideband applications using an active nonlinear resistor, which obtains a robust linearity improvement over process and temperature variations. The proposed linearization method is experimentally demonstrated to improve the IIP3 by 3.5 to 9 dB over a 2.5–10 GHz frequency range. A comparison of measurement results with the prior published state-of-art Ultra-Wideband (UWB) LNAs shows that the proposed linearized UWB LNA achieves excellent linearity with much less power than previously published works. The second part of this dissertation developed a reconfigurable ADC for multistandard receiver and video processors. Typical ADCs are power optimized for only one operating speed, while a reconfigurable ADC can scale its power at different speeds, enabling minimal power consumption over a broad range of sampling rates. A novel ADC architecture is proposed for programming the sampling rate with constant biasing current and single clock. The ADC was designed and fabricated using UMC 90nm CMOS process and featured good power scalability and simplified system design. The programmable speed range covers all the video formats and most of the wireless communication standards, while achieving comparable Figure-of-Merit with customized ADCs at each performance node. Since bias current is kept constant, the reconfigurable ADC is more robust and reliable than the previous published works.